Field-programmable analog array: Difference between revisions

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{{Short description|Integrated device containing configurable analog blocks and interconnects between these blocks}}

A '''field-programmable analog array''' ('''FPAA''') is an [[Integrated circuit|integrated circuit device]] containing computational [[Analog signal|analog]] blocks (CABCABs)<ref>{{cite journalbook |last1=Hall |first1=Tyson |last2=Twigg |first2=Christopher |last3=Hassler |first3=Paul |last4=Anderson |first4=David |title=APPLICATION2004 PERFORMANCEIEEE OFInternational ELEMENTSSymposium INon ACircuits FLOATING–GATEand FPAASystems (IEEE Cat. No.04CH37512) |journalchapter=IEEEApplication performance of elements in a floating-Iscasgate 2004FPAA |date=2004 |volume=II |pages=589–592 |doi=10.1109/ISCAS.2004.1329340 |isbn=0-7803-8251-X |s2cid=17212868 }}</ref><ref>{{cite journal |last1=Baskaya |first1=F. |last2=Reddy |first2=S. |last3=Sung |first3=Kyu Lim |last4=Anderson |first4=D.V. |title=Placement for large-scale floating-gate field-programable analog arrays |journal=IEEE Transactions on Very Large Scale Integration (VLSI) Systems |date=August 2006|volume=14 |issue=8 |pages=906–910 |url=https://www.computer.org/csdl/trans/si/2006/08/01664910-abs.html|doi=10.1109/TVLSI.2006.878477 |s2cid=16583629 |url-access=subscription }}</ref> and interconnects between these blocks offering [[field-programmability]]. Unlike their [[Digital signal|digital]] cousin, the [[Field-programmable gate array|FPGA]], the devices tend to be more application driven than general purpose as they may be [[Current-mode logic|current mode]] or voltage mode devices. For voltage mode devices, each block usually contains an [[operational amplifier]] in combination with programmable configuration of passive components. The blocks can, for example, act as [[Analog adder|summers]] or [[integrator]]s.

FPAAs usually operate in one of two modes: [[Discrete time and continuous time|''continuous time'' and ''discrete time'']].

*''Discrete-time devices'' possess a [[Clock signal|system sample clock]]. In a [[switched capacitor]] design, all blocks sample their input signals with a [[sample and hold]] circuit composed of a semiconductor switch and a capacitor. This feeds a programmable [[Operational amplifier|op amp]] section which can be routed to a number of other blocks. This design requires more complex [[semiconductor]] construction. An alternative, switched-current design, offers simpler construction and does not require the input capacitor, but can be less accurate, and has lower [[fan-out]] - it can drive only one following block. Both discrete-time device types must compensate for switching noise, aliasing at the system sample rate, and sample-rate limited bandwidth, during the design phase.

*''Continuous-time devices'' work more like an array of [[transistor]]s or op amps which can operate at their full [[Bandwidth (signal processing)|bandwidth]]. The components are connected in a particular arrangement through a configurable array of switches. During [[circuit design]], the switch matrix's [[Parasitic element (electrical networks)|parasitic]] inductance, capacitance and [[Noise (signal processing)|noise]] contributions must be taken into account.

Currently there are very few manufactures of FPAAs. On-chip resources are still very limited when compared to that of an [[FPGA]]. This resource deficit is often cited by researchers as a limiting factor in their research.

== History ==

[[File:LYAPUNOV-1 circuit board.jpg|thumb|The LYAPUNOV-1 uses a 4x8 grid of FPAA chips.]]

The term ''FPAA'' was first used in 1991 by Lee and Gulak.<ref name="1 Lee and Gulak">{{cite journal |author=E. K. F. Lee |author2=P. G. Gulak |date=December 1991 |title=A CMOS Field-programmable analog array," |journal=IEEE Journal of Solid-State Circuits |volume=26 |issue=12 |pages=1860–1867 |doi=10.1109/4.104162|bibcode=1991IJSSC..26.1860L |s2cid=5323561 }}</ref> They put forward the concept of CABs that are connected via a routing network and configured digitally. Subsequently, in 1992<ref name="2 Lee and Gulak">{{citecitation documentneeded|titledate=FieldJuly programmable analogue array based on MOSFET transconductors|s2cid=157026162023}}</ref> and 1995<ref name="3 Lee and Gulak">{{cite book|title=A transconductor-based field programmable analog array|chapter=A transconductor-based field-programmable analog array|doi=10.1109/ISSCC.1995.535521|isbn=0-7803-2495-1|year=1995|last1=Lee|first1=E.K.F.|last2=Gulak|first2=P.G.|title=Proceedings ISSCC '95 - International Solid-State Circuits Conference |pages=198–199|s2cid=56613166}}</ref> they further elaborated the concept with the inclusion of op-amps, capacitors, and resistors. This original chip was manufactured using 1.2&nbsp;µmμm CMOS technology and operates in the 20&nbsp;kHz range at a power consumption of 80&nbsp;mW.

However, the concept of a user-definable analog array dates back 20 years earlier, to the mask-programmable analog "Monochip" invented by the designer of the famous 555 timer chip, Hans Camenzind, and his company Interdesign (later acquired by Ferranti in 1977). The Monochip was the basis for a pioneering line of chips for music synthesizers, sold by Curtis Electromusic (CEM). <ref>{{Cite web |last=matrix |title=Pictures of dead CEM chips |url=https://www.matrixsynth.com/2008/06/pictures-of-dead-cem-chips.html |access-date=2025-03-27}}</ref><ref>{{Cite web |date=2017-05-03 |title=Interdesign, Inc. |url=https://sdiy.info/wiki/Interdesign,_Inc. |access-date=2025-03-27 |website=Synth DIY Wiki |language=en}}</ref><ref>{{Cite web |last=tluong |date=2012-09-21 |title=Hans Camenzind: Remembering a “Wizard of Analog” |url=https://computerhistory.org/blog/hans-camenzind-remembering-a-wizard-of-analog/?key=hans-camenzind-remembering-a-wizard-of-analog |access-date=2025-03-27 |website=CHM |language=en}}</ref><ref>{{Cite web |title=Home |url=https://www.curtiselectromusic.com/ |access-date=2025-03-27 |website=Curtis Electromusic |language=en}}</ref>

Pierzchala et al introduced a similar concept named '''electronically-programmable analog circuit''' ('''EPAC''').<ref name="4 Pierzchala">{{cite book|title=Current Mode amplifier/integrator for field programmable analog array|chapter=Current-mode amplifier/Integrator for a field-programmable analog array|doi=10.1109/ISSCC.1995.535520|isbn=0-7803-2495-1|year=1995|last1=Pierzchala|first1=E.|last2=Perkowski|first2=M.A.|last3=Van Halen|first3=P.|last4=Schaumann|first4=R.|pages=196–197|s2cid=60724962}}</ref> It featured only a single integrator. However, they proposed a local interconnect [[Network architecture|architecture]] in order to try to avoid the bandwidth limitations.

Pierzchala et al introduced a similar concept named '''electronically-programmable analog circuit''' ('''EPAC''').<ref name="4 Pierzchala">{{cite book|title=Current Mode amplifier/integrator for field programmable analog array|chapter=Current-mode amplifier/Integrator for a field-programmable analog array|doi=10.1109/ISSCC.1995.535520|isbn=0-7803-2495-1|year=1995|last1=Pierzchala|first1=E.|last2=Perkowski|first2=M.A.|last3=Van Halen|first3=P.|last4=Schaumann|first4=R.|title=Proceedings ISSCC '95 - International Solid-State Circuits Conference |pages=196–197|s2cid=60724962}}</ref> It featured only a single integrator. However, they proposed a local interconnect [[Network architecture|architecture]] in order to try to avoid the bandwidth limitations.

The '''reconfigurable analog signal processor''' ('''RASP''') and a second version were introduced in 2002 by Hall et al.<ref name="6 Hall">{{cite book|title=Field Programmable Analog Arrays: A Floating-Gate Approach|chapter=Field-Programmable Analog Arrays: A Floating—Gate Approach|series=Lecture Notes in Computer Science|year=2002|doi=10.1007/3-540-46117-5_45|s2cid=596774|last1=Hall|first1=Tyson S.|last2=Hasler|first2=Paul|last3=Anderson|first3=David V.|volume=2438|pages=424–433|hdl=1853/5071 |isbn=978-3-540-44108-3|url=http://uilis.unsyiah.ac.id/opentheses/items/show/3084}}</ref><ref name="7 Hall">{{cite journal|title=Large scale field programmable analog arrays for analog signal processing|doi=10.1109/TCSI.2005.853401|year=2005|last1=Hall|first1=T.S.|last2=Twigg|first2=C.M.|last3=Gray|first3=J.D.|last4=Hasler|first4=P.|last5=Anderson|first5=D.V.|journal=IEEE Transactions on Circuits and Systems I: Regular Papers|volume=52|issue=11|pages=2298–2307|s2cid=1148361}}</ref> Their design incorporated high-level elements such as second order [[Band-pass filter|bandpass filters]] and 4 by 4 vector matrix multipliers into the CABs. Because of its architecture, it is limited to around 100&nbsp;kHz and the chip itself is not able to support independent reconfiguration.

In 2004 Joachim Becker picked up the [[parallel connection]] of OTAs (operational transconductance amplifiers) and proposed its use in a hexagonal local interconnection architecture.<ref name="8 Becker">{{cite journalCiteSeerX |title=.,"A continuous-time field programmable analog array (FPAA) consisting of digitally reconfigurable GM-cells |citeseerx = 10.1.1.444.8748}}{{clarify|reason= "title=" does not match title at citeseerx;|date=July 2023}}</ref> It did not require a routing network and eliminated switching the signal path that enhances the frequency response.

In 2005 Fabian Henrici worked with Joachim Becker to develop a switchable and invertible OTA which doubled the maximum FPAA bandwidth.<ref name="9 Becker">{{cite journalCiteSeerX |title=A Continuous-Time Hexagonal Field-Programmable Analog Array in 0.13 µmμm CMOS with 186MHz GBW|citeseerx = 10.1.1.444.8748}}{{clarify|reason= "title=" does not match title at citeseerx;|date=July 2023}}</ref> This collaboration resulted in the first manufactured FPAA in a [[130 nanometer|0.13&nbsp;µmμm]] [[CMOS]] technology.

In 2016 Dr. Jennifer Hasler from Georgia Tech designed a FPAA system on a chip that uses analog technology to achieve unprecedented power and size reductions.<ref name="11 Hasler">{{cite journal |date=June 2016 |author=Suma George |author2=Sihwan Kim |author3=Sahil Shah |author4=Jennifer Hasler |author5=Michelle Collins |author6=Farhan Adil |author7=Richard Wunderlich |author8=Stephen Nease |author9=Shubha Ramakrishnan |title=A Programmable and Configurable Mixed-Mode FPAA SoC, Jennifer|journal=IEEE HaslerTransactions eton al.,Very GeorgiaLarge Tech.,Scale JanuaryIntegration 7,(VLSI) Systems |volume=24 |issue=6 |pages=2253–2261 2016|doi=10.1109/TVLSI.2015.2504119|s2cid=14027246}}</ref>

==See also==

* [[Field-programmable RF]] – Fieldfield programmable radio frequency devices

* [[Complex programmable logic device|Complex programmable logic device (CPLD)]]

* [[CPLD]]: Complex Programmable Logic Device

* [[PSoC]]: Programmable– Systemprogrammable system-on-Chipchip

* [[Network on a chip|NoC]]: Network– network on a Chipchip

* [[Network architecture]]

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==External links==

* [http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=205916545 "Analog's Answer to FPGA Opens Field to Masses"] Sunny Bains, ''EE Times'', February 21, 2008. Issue 1510.

* [http://opencircuitdesign.com/~tim/research/fpaa/fpaa.html "Field programmable analog arrays"] Tim Edwards, [[Johns Hopkins University]] project, 1999.

* [https://www.imtek.de/professuren/mikroelektronik/forschung/low-power-mixed "Field programmable analog arrays" ] Joachim Becker, et al., [[University of Freiburg]], Department of Microsystems Engineering. Hex FPAA Research Project.

* [https://www.anadigm.com/fpaa.asp] Field programmable analog arrays (FPAAs) from Anadigm

* [http://hasler.ece.gatech.edu/ "Integrated Computational Electronics (ICE) Laboratory"] [[Georgia Institute of Technology]] Project

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