Transistor model: Difference between revisions

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{{Short description|Simulation of physical processes taking place in an electronic device}}

{{More inlinefootnotes needed|date=January 2015}}

[[Transistor]]s are simple devices with complicated behavior{{citation needed|date=November 2022}}. In order to ensure the reliable operation of circuits employing transistors, it is necessary to [[Scientific modelling|scientifically model]] the physical phenomena observed in their operation using '''transistor models'''. There exists a variety of different [[Model (abstract)|models]] that range in complexity and in purpose. Transistor models divide into two major groups: models for device design and models for circuit design.

==Models for device design==

The modern transistor has an internal structure that exploits complex physical mechanisms. Device design requires a detailed understanding of how device manufacturing processes such as [[ion implantation]], [[Atomic diffusion|impurity diffusion]], [[Thermal oxidation|oxide growth]], [[Annealing (metallurgy)#Diffusion annealing of semiconductors|annealing]], and [[Etching (microfabrication)|etching]] affect device behavior. [[Semiconductor process simulation|Process models]] simulate the manufacturing steps and provide a microscopic description of device "geometry" to the [[Semiconductor device modeling|device simulator]]. "Geometry" does not mean readily identified geometrical features such as a planar or wrap-around gate structure, or raised or recessed forms of source and drain (see Figure 1 for a [[NVRAM#The floating-gate transistor|memory device]] with some unusual modeling challenges related to charging the floating gate by an avalanche process). It also refers to details inside the structure, such as the [[doping]] profiles after completion of device processing.

[[File:FAMOS esq.png|thumbnail|Figure 1: Floating-gate avalanche injection memory device FAMOS]]

With this information about what the device looks like, the device simulator models the physical processes taking place in the device to determine its electrical behavior in a variety of circumstances: DC current-voltagecurrent–voltage behavior, transient behavior (both large-signal and small-signal), dependence on device layout (long and narrow versus short and wide, or interdigitated versus rectangular, or isolated versus proximate to other devices). These simulations tell the device designer whether the device process will produce devices with the electrical behavior needed by the circuit designer, and is used to inform the process designer about any necessary process improvements. Once the process gets close to manufacture, the predicted device characteristics are compared with measurement on test devices to check that the process and device models are working adequately.

Although long ago the device behavior modeled in this way was very simple{{sndspaced en dash}} mainly drift plus diffusion in simple geometries{{sndspaced en dash}} today many more processes must be modeled at a microscopic level; for example, leakage currents<ref name=":0">{{Cite patent|number=WO2000077533A3|title=Semiconductor device simulation method and simulator|gdate=2001-04-26|invent1=Lui|inventor1-first=Basil|url=https://patents.google.com/patent/WO2000077533A3/en?inventor=Basil+Lui}}</ref> in junctions and oxides, complex transport of carriers including [[velocity saturation]] and ballistic transport, quantum mechanical effects, use of multiple materials (for example, [[SiGe#SiGe Transistors|Si-SiGe]] devices, and stacks of different [[high-κ_dielectricκ dielectric|dielectrics]]) and even the statistical effects due to the probabilistic nature of ion placement and carrier transport inside the device. Several times a year the technology changes and simulations have to be repeated. The models may require change to reflect new physical effects, or to provide greater accuracy. The maintenance and improvement of these models is a business in itself.

These models are very computer intensive, involving detailed spatial and temporal solutions of coupled partial differential equations on three-dimensional grids inside the device.<ref name=Jacoboni>

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|___location=Wien

|isbn=3-211-82110-4

|url=https://books.google.com/books?id=3cWnyhKmACEC&pg=PP1&dq=isbn=3-211-82110-4&sigpg=TCFY-o_l5gLj8OblcwGgQeB4XtsPP1}}

</ref><ref name=Selberherr>

{{cite book

|author=[[Siegfried Selberherr]]

|author-link=Siegfried Selberherr

|title=Analysis and Simulation of Semiconductor Devices

|year= 1984

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|___location=Wien

|isbn=3-211-81800-6

|url=https://books.google.com/books?id=EE4HlRZTYi4C&pg=PA97&dq=isbn=3-211-81800-6&sigpg=19_iT2-C0gy8WdBIPcLc7gRAXw8#PPP1,M1PA97}}

</ref><ref name=Grasser>

{{cite book

|authoreditor=Tibor Grasser (Editor)

|title=Advanced Device Modeling and Simulation (Int. J. High Speed Electron. and Systems)

|year= 2003

|publisher=World Scientific

|isbn=981-238-607-6

|url=https://books.google.com/books?id=HBkA3_pZMp4C&dqq=%22MOSFET++simulation%22&as_brr=0}}

</ref><ref name=Kramer>

{{cite book

|author1=Kramer, Kevin M. |author2=Hitchon, W. Nicholas G.

|lastauthorampname-list-style=yesamp |title=Semiconductor devices: a simulation approach

|year= 1997

|publisher=Prentice Hall PTR

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</ref><ref name=Vasileska>

{{cite book

|author1=Dragica Vasileska|author1-link=Dragica Vasileska |author2=Stephen Goodnick |title=Computational Electronics

|year= 2006

|page=.83

|publisher=Morgan & Claypool

|isbn=1-59829-056-8

|url=https://books.google.com/books?id=DBPnzqy5Fd8C&printsec=frontcover&dqq=%22gate+tunneling%22&as_brr=0#PPA83,M1}}

</ref>

Such models are slow to run and provide detail not needed for circuit design. Therefore, faster transistor models oriented toward circuit parameters are used for circuit design.

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Transistor models are used for almost all modern [[electronic design]] work. [[Analog circuit]] [[Electronic circuit simulation|simulators]] such as [[SPICE]] use models to predict the behavior of a design. Most design work is related to [[integrated circuit design]]s which have a very large tooling cost, primarily for the [[photomask]]s used to create the devices, and there is a large economic incentive to get the design working without any iterations. Complete and accurate models allow a large percentage of designs to work the first time.

Modern circuits are usually very complex, sweet music playing in the dark- be still my foolish heart don't ruin this for me. The performance of such circuits is difficult to predict without accurate computer models, including but not limited to models of the devices used. The device models include effects of transistor layout: width, length, interdigitation, proximity to other devices; transient and DC [[current-voltagecurrent–voltage characteristic]]s; parasitic device capacitance, resistance, and inductance; time delays; and temperature effects; to name a few items.<ref name=Schneider>

{{cite book

|author1=Carlos Galup-Montoro |author2=Mǻrcio C Schneider |title=Mosfet Modeling for Circuit Analysis And Design

|year= 2007

|publisher=World Scientific

|isbn=978-981-256-810-76

|url=https://books.google.com/books?id=yrrDcRm9bfUC&pg=PA293&dq=%22gate+tunneling%22&as_brrpg=0&sig=SJv5PSqaLbMdw10sEQPFd3ykN8E#PPA1,M1PA293}}

</ref>

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|page=Chapter 1

|publisher=World Scientific

|isbn=978-981-256-862-X5

|url=https://books.google.com/books?id=SkT2xOuvpuYC&dqq=%22table+lookup+model%22&as_brr=0

|noppno-pp=true}}

</ref><ref name=Tsividis>

{{cite book

|author=Yannis Tsividis

|title=Operational Modeling of the MOS Transistor

|year= 1999

|edition=Second

|publisher=McGraw-Hill

|___location=New York

|isbn=0-07-065523-5

|url=httphttps://worldcatarchive.org/isbndetails/0070655235}}isbn_9780073032313

|url-access=registration

}}

</ref>

====Physical models====

: These are [[Semiconductor device modeling|models based upon device physics]], based upon approximate modeling of physical phenomena within a transistor.<ref name=":0" /><ref>{{Cite journal |last1=Lui |first1=Basil |last2=Migliorato |first2=P |date=1997-04-01 |title=A new generation-recombination model for device simulation including the Poole-Frenkel effect and phonon-assisted tunnelling |url=https://www.sciencedirect.com/science/article/pii/S0038110196001487 |journal=Solid-State Electronics |language=en |volume=41 |issue=4 |pages=575–583 |doi=10.1016/S0038-1101(96)00148-7 |bibcode=1997SSEle..41..575L |issn=0038-1101|url-access=subscription }}</ref> Parameters<ref>{{Cite journal |last1=Lui |first1=Basil |last2=Tam |first2=S. W. B. |last3=Migliorato |first3=P. |date=1998 |title=A Polysilicon Tft Parameter Extractor |url=https://www.cambridge.org/core/journals/mrs-online-proceedings-library-archive/article/abs/polysilicon-tft-parameter-extractor/AFB82CB806F1140E9249C5FA90285B66 |journal=MRS Online Proceedings Library |language=en |volume=507 |pages=365 |doi=10.1557/PROC-507-365 |issn=0272-9172|url-access=subscription }}</ref><ref>{{Cite journal |last1=Kimura |first1=Mutsumi |last2=Nozawa |first2=Ryoichi |last3=Inoue |first3=Satoshi |last4=Shimoda |first4=Tatsuya |last5=Lui |first5=Basil |last6=Tam |first6=Simon Wing-Bun |last7=Migliorato |first7=Piero |date=2001-09-01 |title=Extraction of Trap States at the Oxide-Silicon Interface and Grain Boundary for Polycrystalline Silicon Thin-Film Transistors |url=https://iopscience.iop.org/article/10.1143/JJAP.40.5227/meta |journal=Japanese Journal of Applied Physics |language=en |volume=40 |issue=9R |pages=5227 |doi=10.1143/JJAP.40.5227 |bibcode=2001JaJAP..40.5227K |s2cid=250837849 |issn=1347-4065|url-access=subscription }}</ref> within these models are based upon physical properties such as oxide thicknesses, substrate doping concentrations, carrier mobility, etc.<ref>{{Cite journal |last1=Lui |first1=Basil |last2=Tam |first2=S. W.-B. |last3=Migliorato |first3=P. |last4=Shimoda |first4=T. |date=2001-06-01 |title=Method for the determination of bulk and interface density of states in thin-film transistors |url=https://aip.scitation.org/doi/abs/10.1063/1.1361244 |journal=Journal of Applied Physics |volume=89 |issue=11 |pages=6453–6458 |doi=10.1063/1.1361244 |bibcode=2001JAP....89.6453L |issn=0021-8979|url-access=subscription }}</ref> In the past these models were used extensively, but the complexity of modern devices makes them inadequate for quantitative design. Nonetheless, they find a place in hand analysis (that is, at the conceptual stage of circuit design), for example, for simplified estimates of signal-swing limitations.

====Empirical models====

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===Small-signal linear models===

[[Small-signal model|Small-signal]] or [[Linear system|linear]] models are used to evaluate [[BIBO stability|stability]], [[Gain (electronics)|gain]], [[Electronic noise|noise]] and [[Bandwidth (signal processing)|bandwidth]], both in the conceptual stages of circuit design (to decide between alternative design ideas before computer simulation is warranted) and using computers. A small-signal model is generated by taking derivatives of the current-voltagecurrent–voltage curves about a bias point or [[Q-point]]. As long as the signal is small relative to the nonlinearity of the device, the derivatives do not vary significantly, and can be treated as standard linear circuit elements.

A bigAn advantage of small signal models is they can be solved directly, while large signal nonlinear models are generally solved iteratively, with possible [[Numerical ordinary differential equations#Analysis|convergence or stability]] issues. By simplification to a linear model, the whole apparatus for solving linear equations becomes available, for example, [[simultaneous equations]], [[determinant]]s, and [[Matrix (mathematics)|matrix theory]] (often studied as part of [[linear algebra]]), especially [[Cramer's rule]]. Another advantage is that a linear model is easier to think about, and helps to organize thought.

====Small-signal parameters====

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* [[Gummel–Poon model]]

* [[Bipolar junction transistor#Ebers–Moll model|Ebers–Moll model]]

* [http://www-device.eecs.berkeley.edu/bsim/?page=BSIM3 BSIM3] (see [[BSIM]])

* [http://www-device.eecs.berkeley.edu/bsim/?page=BSIM4 BSIM4]

* [http://www-device.eecs.berkeley.edu/bsim/?page=BSIMSOI BSIMSOI]

* [[EKV MOSFET Model]] (see also [http://ekv.epfl.ch/ its web site] at [[École Polytechnique Fédérale de Lausanne|EPFL]])

* [http://www.cea.fr/cea-tech/leti/pspsupport/ PSP]

* [http://www.iee.et.tu-dresden.de/iee/eb/hic_new/hic_start.html HICUM]

* [http://mextram.ewi.tudelft.nl/ MEXTRAM]

* [[Hybrid-pi model]]

* [[Bipolar junction transistor#h-parameter model|H-parameter model]]

==See also==

* [[{{section link|Bipolar junction transistor#|Theory and modeling]]}}

* [[Safe operating area]]

* [[Electronic design automation]]

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==References==

{{Reflist}}

<references/>

==External links==

*''Agilent EEsof EDA, IC-CAP Parameter Extraction and Device Modeling Software [https://www.keysight.com/en/pc-1297149/ic-cap-device-modeling-software-measurement-control-and-parameter-extraction?cc=US&lc=eng http://eesof.tm.agilent.com/products/iccap_main.html] ''

[[Category:Electronic engineering]]

[[Category:Transistor modeling]]''