Bit-serial architecture: Difference between revisions

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{{Short description|Computational system in which data are sent one bit at a time down a wire}}

In [[digital logic]] applications, '''bit-serial architectures''' send data one bit at a time, along a single wire, in contrast to [[Parallel transmission|bit-parallel]] [[word (computer architecture)|word]] architectures, in which data values are sent all bits or a word at once along a group of wires.

{{Use dmy dates|date=November 2022|cs1-dates=y}}

{{Use list-defined references|date=November 2022}}

In [[digitalcomputer logicarchitecture]] applications, '''bit-serial architectures''' send data one bit at a time, along a single wire, in contrast to [[Parallel transmission|bit-parallel]] [[word (computer architecture)|word]] architectures, in which data values are sent all bits or a word at once along a group of wires.

All computers before 1951, and most of the early [[massively parallel (computing)|massive parallel processing]] machines used a bit-serial architecture—they were [[serial computer]]s.

All digital computers built before 1951, and most of the early [[massively parallel (computing)|massive parallel processing]] machines used a bit-serial architecture—they were [[serial computer]]s.

Bit-serial architectures were developed for [[digital signal processing]] in the 1960s through 1980s, including efficient structures for bit-serial multiplication and accumulation.<ref>

{{cite book

| title = VLSI signal processing: a bit-serial approach

| author = [[Peter B. Denyer]] and David Renshaw

| publisher = Addison-Wesley

| year = 1985

| isbn = 978-0-201-13306-6

| url = http://www.google.com/search?tbm=bks&tbo=1&q=intitle%3A%22bit-serial%22+jackson+kaiser+macdonald&btnG=Search+Books#sclient=psy&hl=en&tbo=1&tbm=bks&source=hp&q=intitle:%22bit-serial%22+jackson+kaiser+mcdonald&aq=f&aqi=&aql=&oq=&pbx=1&bav=on.2,or.r_gc.r_pw.&fp=93266f80b0a6b0fe&biw=1261&bih=660

}}</ref>

Bit-serial architectures were developed for [[digital signal processing]] in the 1960s through 1980s, including efficient structures for bit-serial multiplication and accumulation.<ref name="Denyer_1995"/>

Often N serial processors will take less FPGA area and have a higher total performance than a single N-bit parallel processor.<ref>

Raymond J. Andraka.

The [[HP Nut]] processor used in many [[Hewlett-Packard calculator]]s operated bit-serially.<ref name="Smith_2023"/>

[http://www.fpga-guru.com/files/supercn.pdf "Building a High Performance Bit Serial Processor in an FPGA"].

</ref>

OftenAssuming ''N'' is an arbitrary integer number, ''N'' serial processors will often take less [[Field-programmable gate array|FPGA]] area and have a higher total performance than a single ''N''-bit parallel processor.<ref name="Andraka"/>

==See also==

* [[Serial computer]]<!-- with possibilities -->

* [[1-bit computing]]

* [[Bit banging]]

* [[Bit slicing]]

* [[BKM algorithm]]

* [[CORDIC]]

==References==

{{reflist}}|refs=

<ref name="Denyer_1995">

{{cite book |title=VLSI signal processing: a bit-serial approach |series=VLSI systems series |author-first1=Peter B. |author-last1=Denyer |author-link1=Peter B. Denyer |author-first2=David |author-last2=Renshaw |publisher=[[Addison-Wesley]] |date=1985 |isbn=978-0-201-13306-6 |url=https://books.google.com/books?id=EklTAAAAMAAJ}}</ref>

<ref name="Andraka">{{cite web |title=Building a High Performance Bit Serial Processor in an FPGA |author-first=Raymond J. |author-last=Andraka. |url=http://www.fpga-guru.com/files/supercn.pdf}}</ref>

<ref name="Smith_2023">{{cite web |title=HP-15C CE woes: 1 bug, 2 limitations, 3 questions |author-first=Eric L. "brouhaha" |author-last=Smith |date=2023-08-09 |work=MoHPC - The Museum of HP Calculators |url=https://www.hpmuseum.org/forum/thread-20281.html |access-date=2023-09-24 |url-status=live |archive-url=https://web.archive.org/web/20230810144726/https://www.hpmuseum.org/forum/thread-20281.html |archive-date=2023-08-10}}</ref>

}}

==External links==

* [http://portal.acm.org/citation.cfm?id=503063 Application of [[FPGA]] technology to accelerate the [[finite-difference time-___domain]] (FDTD) method]

* [http://portal.acm.org/citation.cfm?id=741014 BIT-Serial [[FIR filter]]sfilters with CSD Coefficients for FPGAs]

{{CPU technologies}}

[[Category:Data transmission]]

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