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{{Short description|Computer architecture bit width}}
{{Multiple issues|{{primary sources|date=July 2013}}{{More citations needed|date=April 2023}}}}
{{n-bit|512|(64 [[octet (computing)|octets]])}}
There are currently no mainstream general-purpose [[CPU|processors]] built to operate on 512-bit integers or addresses, though a number of processors do operate on 512-bit data. {{As of|2013}}, the [[Xeon Phi|Intel Xeon Phi]] has a [[vector processing unit]] with 512-bit vector registers, each one holding sixteen 32-bit elements or eight 64-bit elements, and a single instruction can operate on all these values in parallel. However, the Xeon Phi's vector processing unit does not operate on individual numbers that are 512 bits in length.<ref>{{cite web|url=https://software.intel.com/sites/default/files/managed/09/07/xeon-phi-coprocessor-system-software-developers-guide.pdf|title=Intel Xeon Phi Coprocessor System Software Developers Guide|publisher=[[Intel]]|date=March 2014|access-date=April 30, 2019}}</ref>▼
There are currently no mainstream general-purpose [[CPU|processors]] built to operate on 512-bit integers or addresses, though a number of processors do operate on 512-bit data.
A 512-bit register can store 2<sup>512</sup> different values. The range of [[integer]] values that can be stored in 512 bits depends on the [[Integer (computer science)#Value%20and%20representation|integer representation]] used.▼
== Representation ==
▲A 512-bit register can store 2<sup>512</sup> different values. The range of [[integer]] values that can be stored in 512 bits depends on the [[Integer (computer science)#Value
The maximum value of a signed 512-bit integer is {{nowrap|2<sup>511</sup> − 1}}, written in decimal as {{zwsp|6,|703,|903,|964,|971,|298,|549,|787,|012,|499,|102,|923,|063,|739,|682,|910,|296,|196,|688,|861,|780,|721,|860,|882,|015,|036,|773,|488,|400,|937,|149,|083,|451,|713,|845,|015,|929,|093,|243,|025,|426,|876,|941,|405,|973,|284,|973,|216,|824,|503,|042,|047}} (approximately {{val|6.7039|e=153}}).
[[File:Sapphire Radeon R9 290X-front oblique PNr°0437.jpg|thumb|The AMD [[Radeon R9]] 290X (Sapphire OEM version pictured here) uses a 512 bit memory bus]]▼
* Some GPUs such as the [[AMD]] [[Radeon_HD_2000_series#Radeon_HD_2900|Radeon HD 2900XT]], the [[Nvidia]] GTX 280,<ref>{{cite web|url=http://www.geforce.com/hardware/desktop-gpus/geforce-gtx-280/specifications |title=GTX 280 | Specifications |publisher=GeForce |access-date=2013-08-13}}</ref> GTX 285,<ref>{{cite web|url=http://www.geforce.com/hardware/desktop-gpus/geforce-gtx-285/specifications |title=GTX 285 | Specifications |publisher=GeForce |access-date=2013-08-13}}</ref> Quadro FX 5800<ref>{{cite web|url=http://www.nvidia.com/object/product_quadro_fx_5800_us.html |title=NVIDIA® Quadro® FX 5800 provides professionals with visual supercomputing from their desktops delivering results that push visualization beyond traditional 3D |publisher=Nvidia.com |access-date=2013-08-13}}</ref> and several [[Nvidia Tesla]] products move data across a 512-bit memory bus. Then [[AMD Radeon Rx 200 Series#Radeon R9 290|AMD Radeon R9 290, R9 290X and 295X2]] followed.▼
* Many [[hash functions]], such as [[SHA-512]] and [[SHA3-512]], have a 512-bit output.▼
* [[AVX-512]] are 512-bit extensions to the 256-bit [[Advanced Vector Extensions]] SIMD instructions for x86 [[instruction set architecture]] proposed by Intel in July 2013, and released on 2016 with [[Xeon Phi#Knights Landing|Knights Landing]], and in 2017 on the HEDT and consumer server platform, with Skylake-X and [[Skylake (microarchitecture)#"Skylake-SP" (14 nm) Scalable Performance|Skylake-SP]] respectively.▼
==
▲[[File:Sapphire Radeon R9 290X-front oblique PNr°0437.jpg|thumb|The AMD [[Radeon R9]] 290X (Sapphire OEM version pictured here) uses a 512
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{{CPU technologies}}▼
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== Software ==
== References ==
{{Reflist}}
[[Category:Data unit]]
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