512-bit computing: Difference between revisions

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{{Short description|Computer architecture bit width}}

{{primary sources|date=July 2029}}

{{Multiple issues|{{primary sources|date=July 2013}}{{More citations needed|date=April 2023}}}}

{{n-bit|512|(64 [[octet (computing)|octets]])}}

There are currently no mainstream general-purpose [[CPU|processors]] built to operate on 512-bit integers or addresses, though a number of processors do operate on 512-bit data.

== Representation ==

A 512-bit register can store 2⁵¹² different values. The range of [[integer]] values that can be stored in 512 bits depends on the [[Integer (computer science)#Value%20and%20representation and representation|integer representation]] used.

The maximum value of ana unsignedsigned 512-bit integer is 13{{nowrap|2⁵¹¹ − 1}},407 written in decimal as {{zwsp|6,807|703,929|903,942|964,597|971,099|298,574|549,024|787,998|012,205|499,846|102,127|923,479|063,365|739,820|682,592|910,393|296,377|196,723|688,561|861,443|780,|721,764|860,030|882,073|015,546|036,976|773,801|488,874|400,298|937,166|149,903|083,427|451,690|713,031|845,858|015,186|929,486|093,050|243,853|025,753|426,882|876,811|941,946|405,569|973,946|284,433|973,649|216,006|824,084|503,095|042,|047}} (2⁵¹² − 1) or approximately 1{{val|6.34078 x 10¹⁵⁴7039|e=153}}).

== Hardware ==

[[File:Sapphire Radeon R9 290X-front oblique PNr°0437.jpg|thumb|The AMD [[Radeon R9]] 290X (Sapphire OEM version pictured here) uses a 512 -bit memory bus.]]

The Intel [[Xeon Phi|Intel Xeon Phi]] has a [[vector processing unit]] with 512-bit vector registers, each one holding sixteen [[32-bit computing|32-bit]] elements or eight [[64-bit computing|64-bit]] elements, and a singleone instruction can operate on all these values in parallel. However, the Xeon Phi's vector processing unit does not operate on individual numbers that are 512 bits in lengthlong.<ref>{{cite web|url=https://software.intel.com/sites/default/files/managed/09/07/xeon-phi-coprocessor-system-software-developers-guide.pdf|title=Intel Xeon Phi Coprocessor System Software Developers Guide|publisher=[[Intel]]|date=March 2014|access-date=April 30, 2019}}</ref>

Some GPUs, such as the [[AMDAdvanced Micro Devices]] (AMD) [[Radeon_HD_2000_seriesRadeon HD 2000 series#Radeon_HD_2900Radeon HD 2900|Radeon HD 2900XT]], the [[Nvidia]] GTX 280,<ref>{{cite web|url=http://www.geforce.com/hardware/desktop-gpus/geforce-gtx-280/specifications |title=GTX 280 &#124;: Specifications |publisher=GeForce |access-date=2013-08-13}}</ref> GTX 285,<ref>{{cite web|url=http://www.geforce.com/hardware/desktop-gpus/geforce-gtx-285/specifications |title=GTX 285 &#124;: Specifications |publisher=GeForce |access-date=2013-08-13}}</ref> Quadro FX 5800,<ref>{{cite web|url=http://www.nvidia.com/object/product_quadro_fx_5800_us.html |title=NVIDIA®Nvidia Quadro® FX 5800 provides professionals with visual supercomputing from their desktops delivering results that push visualization beyond traditional 3D |publisher=Nvidia.com |access-date=2013-08-13 |archive-url=https://web.archive.org/web/20190611163640/http://www.nvidia.com/object/product_quadro_fx_5800_us.html |archive-date=2019-06-11 |url-status=dead}}</ref> and several [[Nvidia Tesla]] products, move data across a 512-bit memory bus. Then [[AMD Radeon Rx 200 Series#Radeon R9 290|AMD Radeon R9 290, R9 290X and 295X2]] followed.

[[AVX-512]] are 512-bit extensions to the 256-bit [[Advanced Vector Extensions]] SIMD instructions for x86 [[instruction set architecture]] proposed by Intel in July 2013, and released onin 2016 with [[Xeon Phi#Knights Landing|Knights Landing]], and in 2017 on the HEDT and consumer server platform, with Skylake-X and [[Skylake (microarchitecture)#"Skylake-SP" (14 nm) Scalable Performance|Skylake-SP]] respectively.

== Software ==

Many [[hash functions]], such as [[SHA-512]] and [[SHA3-512]], have a 512-bit output.

== References ==

{{reflistReflist}}

{{CPUProcessor technologies}}

[[Category:Data unit]]