Content deleted Content added
→Possible malicious link in article: new section |
Guy Harris (talk | contribs) →External links: Results of reviewing those pages. |
||
| (19 intermediate revisions by 8 users not shown) | |||
Line 1:
{{Talk header}}
{{WikiProject
{{WikiProject Computing |importance=mid |software=yes |software-importance=Mid}} {{WikiProject Technology}}
{{WikiProject Computer science}}
{{WikiProject Software}}
}}
== Changed "lowest" to "lower" ==
Line 78 ⟶ 83:
<div class="boilerplate" style="background-color: #efe; margin: 2em 0 0 0; padding: 0 10px 0 10px; border: 1px dotted #aaa;"><!-- Template:polltop -->
:''The following discussion is an archived debate of the {{{type|proposal}}}. <
{{{result|The result of the debate was}}} '''Move'''. —[[User:wknight94|Wknight94]] ([[User talk:wknight94|talk]]) 02:24, 5 August 2006 (UTC)
Line 100 ⟶ 105:
*'''Don't Care''': To me, the terms are interchangeable, perhaps a reflection of being a contractor who migrates from client to client who use different terminologies. As far as I know, I've never been misunderstood using the "other" term. As long as the typed word redirects to a relevant article, it doesn't matter which way it goes. —[[User:EncMstr|EncMstr]] 04:07, 2 August 2006 (UTC)
**It matters because [[Wikipedia:Naming conventions (common names)| WP naming policy ]] says use the most common name, and redirects are for less common usage. Thus you'd redirect from microprogram to microcode, not vice versa as now. [[User:Joema|Joema]] 17:14, 2 August 2006 (UTC)
:''The above discussion is preserved as an archive of the debate. <
== Intel Core Microarchitecture ==
Line 219 ⟶ 224:
:Indeed. Properly speaking microcode is used to impliment an instruction set, but from the 1960's IBM referred to VLIW code used for other purposes as microcode. Further, on the low end [[IBM System/360]] and [[IBM System/370|S/370]] machines, IBM used the same hardware instruction set to simulate the architect instructions and to implement the I/O channels.
:To add to the confusion, other terms have been used for code and instruction sets used to simulate another instruction set, e.g., ''logand'' and ''logram'' on the [[TRW]]-130; see [http://www.bitsavers.org/pdf/trw/trw-130/ bitsavers] for manuals. [[User:Chatul|Shmuel (Seymour J.) Metz Username:Chatul]] ([[User talk:Chatul|talk]]) 16:38, 7 August 2012 (UTC)
== History ==
Line 299 ⟶ 304:
== Possible malicious link in article ==
When I click on the link in reference 2 (Fog, Agner), Malwarebytes reports "Website blocked due to a Trojan." Can anyone verify this? <!-- Template:Unsigned --><small class="autosigned">— Preceding [[Wikipedia:Signatures|unsigned]] comment added by [[User:Paul C. Anagnostopoulos|Paul C. Anagnostopoulos]] ([[User talk:Paul C. Anagnostopoulos#top|talk]] • [[Special:Contributions/Paul C. Anagnostopoulos|contribs]]) 01:10, 14 January 2020 (UTC)</small> <!--Autosigned by SineBot-->
:Is it still doing that? It might just have been a false positive. [[User:Guy Harris|Guy Harris]] ([[User talk:Guy Harris|talk]]) 06:23, 24 May 2022 (UTC)
== Why is this in Category:Microcontrollers? ==
There well be [[microcontroller]]s where the CPU is implemented using microcode, but if that's a sufficient reason to put this article into {{Cl|Microcontrollers}}, that would also be sufficient reason to put this in {{Cl|Mainframe computers}}, {{Cl|Minicomputers}}, and {{Cl|Microprocessors}}.
Or is the idea that, in some cases, a peripheral might have an embedded microcontroller, and the code in that microcontroller is referred to as microcode for the peripheral? [[User:Guy Harris|Guy Harris]] ([[User talk:Guy Harris|talk]]) 06:21, 24 May 2022 (UTC)
== Intro and definition ==
{{diff2|1099255239|1099254707|Jul 19, 2022, 20:21}} - ''«Overview: add more sane definition of instructions microops»''<br/><br>
I've added a more sane definition to the overview along with a source. The intro one is too technical. <span style="font-weight: bold" >[[User:Alexander_Davronov|<span style="color:#a8a8a8;">AXO</span><span style="color:#000">NOV</span>]] [[User talk:Alexander_Davronov|(talk)]] [[Special:Contributions/Alexander_Davronov|⚑]]</span> 20:22, 19 July 2022 (UTC)
:[[Micro-operation]]s, in modern CISC processors such as [[P6 (microarchitecture)|P6]]-microarchitecture and later [[x86]] processors and at least some IBM [[System/390]] and [[z/Architecture]] microprocessors, are different from traditional microcode. Traditional microcode isn't generated on the fly from decoded instructions, but most micro-operations in modern processors are - some x86 microcode may consist of micro-ops stored on-chip, but I'm not sure whether modern IBM mainframe processors have any microcode such as that, instead relying on [[millicode]], which is composed of instructions from a subset of the S/390 or z/Architecture instruction set plus processor-specific extensions, to implement complex operations. [[User:Guy Harris|Guy Harris]] ([[User talk:Guy Harris|talk]]) 22:16, 19 July 2022 (UTC)
::{{diff2|1099262619|1099255239|Jul 19, 2022, 21:15}} - ''«Instruction decoding microcode: Micro-ops are different from traditional microcode. Traditional fully-microcoded processors fetch, decode, and execute operations were done by microcode; in micro-op processors, hardware fetches and decodes instructions, emitting a sequence of one or more micro-ops that are scheduled for execution. Intel's document is not authoritative here; it's focused on modern CISC processors.)»''<br/>
:::{{re|Guy Harris}} The source says: {{bquote|''«collection of microps (or μ-instructions) make up a microcode»''[https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/secure-coding/xucode-implementing-complex-instruction-flows.html]}}
::: The term ''μ-op'' and ''microcode'' are not the same but are mutually related. That's enough per source. See also:[https://www.google.ru/books/edition/Essentials_of_Computer_Architecture/ORINDgAAQBAJ?hl=en&gbpv=1&dq=instruction+microcode&pg=PA148&printsec=frontcover]{{rp|148}}
::: {{tqi|[…] Intel's document is not authoritative here […] }} See additional source above. The source is talking specifically about instructions-decoding microcode which simply map macro-instructions into a circuitry (e.g. ALU) that process data specified by macro-instructions. The microcode sits between decode & execute stages in the [[instruction cycle]]. It works like a microcontroller that treats MCU instructions as data and interprets it. I propose we keep my edit. Best.
:: <span style="font-weight: bold" >[[User:Alexander_Davronov|<span style="color:#a8a8a8;">AXO</span><span style="color:#000">NOV</span>]] [[User talk:Alexander_Davronov|(talk)]] [[Special:Contributions/Alexander_Davronov|⚑]]</span> 08:21, 20 July 2022 (UTC)
:::The source says:
:::{{quote| In a Complex Instruction Set (CISC) machine like x86, the stream of instructions read from memory are decoded into small operations known as micro-ops (μops).}}
:::In fully microcoded pre-P6 processors, the stream of instructions are read from memory by microcode and decoded by microcode, which then, based on the opcode, jumps to the microcode that executes the instruction in question. The instructions are not directly decoded into microinstructions/micro-ops. (The microcode that fetches and decodes the instructions, and the microcode that executes the instructions, may be executed by different processors, as per the VAX 8800 example and possibly other processors.)
:::In other processors, the instructions might be fetched and decoded by hardware, and that hardware may direct other hardware to execute some instructions and direct microcode to execute others, as per, for example, the [[Intel 80486]].
:::In the P6, instructions are fetched and decoded, probably by hardware. and translated on the fly into micro-ops that are scheduled for execution. This is the way all non-Atom x86 processors since the Pentium Pro work (I don't know whether the Atom processors work the same way or not).
:::If that's what the author of the document meant by "the stream of instructions read from memory are decoded into small operations known as micro-ops (μops)", then it's certainly true of all those x86 processors, and true (given IBM's use of the term "microop") of at least some z/Architecture processors, but it was ''not'' true of, for example, any of the IBM System/360 processors, probably not true of most if not all System/370 processors, not true of any microcoded PDP-11 processors not true of some if not all VAX processors and not, as far as I know, true of any Intel processors up to the 80386 (and possibly including the 80486 and original Pentium).
:::I.e., if that's what they meant, their statement does '''''NOT''''' apply to a large number of microcoded processors.
:::"The source is talking specifically about instructions-decoding microcode which simply map macro-instructions into a circuitry (e.g. ALU) that process data specified by macro-instructions. The microcode sits between decode & execute stages in the instruction cycle. It works like a microcontroller that treats MCU instructions as data and interprets it." is not at all clear:
:::I have ''no'' idea what it means to "map macro-instructions into a circuitry (e.g. ALU) that process data specified by macro-instructions."; which of the various types of processor I mention above does it refer, and how does it do so?
:::"It works like a microcontroller that treats MCU instructions as data and interprets it." is referring to the "In fully microcoded pre-P6 processors", ''not'' to the processors in which hardware reads macroinstructions and translates them to generated-on-the-fly micro-operations.
:::So I propose we ignore any edit that cannot distinguish between "microcode as simulator for an instruction set" (traditional microcode) and "micro-operations generated on the fly by the instruction decoder" (modern x86 and z/Architecture processors). [[User:Guy Harris|Guy Harris]] ([[User talk:Guy Harris|talk]]) 08:52, 20 July 2022 (UTC)
::::BTW, your other source's link informs me that I "have either reached a page that is unavailable for viewing or reached [my] viewing limit for this book", so I just bought it on Apple Books.
::::Section 8.9 "Microcoded Instructions" is discussing a traditional microcoded processor. Section 8.10 "Microcode Variations" says that "“On some CPUs, microcode implements the entire fetch-execute cycle — the microcode interprets the opcode, fetches operands, and performs the specified operation.", which is what I referred to as a "fully-microcoded processor", and which also implies that there are alternatives, such as "hardware directly fetches and decodes instructions and fetches some or all operands, and then jumps to microcode to implement the instruction".
::::Unfortunately, the book doesn't cover the way most general-purpose processors work these days; the word "superscalar" appears nowhere in the book, according to the Books app, and "out-of-order" only appears in one section with one paragraph. The stuff that processors from smartphones to supercomputers do is in sections 8.19 through 8.21, with very little detail. [[User:Guy Harris|Guy Harris]] ([[User talk:Guy Harris|talk]]) 09:19, 20 July 2022 (UTC)
:::::As for micro-operations in the P6-and-later sense, the [[P6 (microarchitecture)]] page says:
:::::{{quote|P6 processors dynamically translate [[IA-32]] instructions into sequences of buffered RISC-like [[micro-operation]]s, then analyze and reorder the micro-operations to detect parallelizable operations that may be issued to more than one [[execution unit]] at once.<ref>{{cite journal |last1=Gwennap |first1=Linley |title=Intel's P6 Uses Decoupled Scalar Design |journal=Microprocessor Report |date=16 February 1995 |volume=9 |issue=2 |url=http://www.cs.cmu.edu/afs/cs.cmu.edu/academic/class/15213-f01/docs/mpr-p6.pdf}}</ref> The Pentium Pro was the first x86 microprocessor designed by Intel to use this technique, though the NexGen [[Nx586]], introduced in 1994, did so earlier.}}
:::::The reference says that
:::::{{quote|The decoders translate x86 instructions into uops. P6 uops have a fixed length of 118 bits, using a regular structure to encode an operation, two sources, and a destination. The source and destination fields are each wide enough to contain a 32-bit operand. Like RISC instructions, uops use a load/store model; x86 instructions that operate on memory must be broken into a load uop, an ALU uop, and possibly a store uop.}}
:::::which is a description of a "generate micro-operations on the fly" processor, not a traditional "microcode as instruction set simulator" processor. [[User:Guy Harris|Guy Harris]] ([[User talk:Guy Harris|talk]]) 09:29, 20 July 2022 (UTC)
== Overview/Microcode ==
The '''Microcode''' subsection within the '''Overview''' section contains the following:
''Using microcode, all that changes is the code stored in the associated read only memory (ROM). This makes it much easier to fix problems in a microcode system. It also means that there is no effective limit to the complexity of the instructions, it is only limited by the amount of ROM one is willing to use.''
Since microcode can be updated, is it actually stored in ROM? I presume the answer is, "No," but I don't know what type of memory should be mentioned, so I didn't change the text.
--[[Special:Contributions/141.162.101.52|141.162.101.52]] ([[User talk:141.162.101.52|talk]]) 16:41, 26 September 2024 (UTC)
:{{tq|Since microcode can be updated}} ''Some'' microcode can be easily updated. Other microcode cannot be easily updated, such as the microcode in the [[IBM System/360 Model 30]], [[IBM System/360 Model 40]], and [[IBM System/360 Model 50]], which use capacitor read-only storage, [[transformer read-only storage]], (balanced) capacitor read-only storage, respectively; it may be possible to replace that ROM, or (in the case of the capacitor ROM) remove a component and replace it, but it can't be electronically updated, only manually updated. Other processors may have had microcode in on-chip ROM in a single-chip CPU, which can be replaced only by replacing the entire CPU.
:{{tq|is it actually stored in ROM?}} Yes on some systems, no on others. [[User:Guy Harris|Guy Harris]] ([[User talk:Guy Harris|talk]]) 18:01, 26 September 2024 (UTC)
::Fixed in [https://en.wikipedia.org/w/index.php?title=Microcode&diff=1247933799&oldid=1247898843 this edit]; I just spoke of the memory holding the microcode (which could be ROM, EEPROM, RAM, or secondary storage from which the microcode is loaded into RAM). [[User:Guy Harris|Guy Harris]] ([[User talk:Guy Harris|talk]]) 20:17, 26 September 2024 (UTC)
{{reflist-talk}}
==External links==
{{See| Wikipedia: External links}}
:Some things just grow during incremental edits and sometimes get out of hand. The "External links" section, one of the optional appendices, was expanded to 9 entries. Three seems to be an acceptable number, and of course, everyone has their favorite to try to add for a fourth. [[WP:consensus|Consensus]] needs to determine this. A tag indicates concerns.
:However, none is needed for article promotion.
:Some links may be included in [[WP:ELNO]], or [[WP:What Wikipedia is not|What Wikipedia is not]] (policy) such as [[WP:NOTREPOSITORY]] or [[WP:NOTGUIDE]].
*[[WP:ELDEAD]] may apply.
*In some cases [[WP:ELCITE|'''ELCITE''']] applies: {{tq|'''Do not use {{tl|cite web}}''' or other citation templates in the External links section. Citation templates are permitted in the Further reading section}}. Others, listed below:
*[[WP:ELPOINTS|'''ELpoints #3)''']] states: {{tq|Links in the "External links" section should be kept to a minimum. A lack of external links or a small number of external links is not a reason to add external links.}}
*[[WP:LINKFARM|'''LINKFARM''']] states: {{tq|There is nothing wrong with adding one or more useful content-relevant links to the external links section of an article; however, excessive lists can dwarf articles and detract from the purpose of Wikipedia. On articles about topics with many fansites, for example, including a link to one major fansite may be appropriate.}}
*[[WP:ELMIN|'''ELMIN''']]: {{tq|Minimize the number of links}}.
:The [[WP:External links|External links]]''' guideline '''This page in a nutshell''': {{tq|External links in an article can be helpful to the reader, but they should be kept minimal, meritable, and directly relevant to the article. With rare exceptions, external links should not be used in the body of an article.}}
:Second paragraph, {{tq|acceptable external links include those that contain further research that is accurate and on-topic, information that could not be added to the article for reasons such as copyright or amount of detail, or other meaningful, relevant content that is not suitable for inclusion in an article for reasons unrelated to its accuracy.}}
**'''Please also note''':
*[[WP:ELBURDEN]]: {{tq|'''Disputed links should be excluded by default''' unless and until there is a consensus to include them}}. Please do not add back more links without consensus. Simple solution to facilitate career maintenance tag. Move links here for discussion.
:'''Moved links''':
* [https://web.archive.org/web/20050124004424/http://www-03.ibm.com/ibm/history/exhibits/attic3/attic3_016.html Transformer Read-only Store]
* [http://people.cs.clemson.edu/~mark/uprog.html A Brief History of Microprogramming]
* [https://lists.debian.org/debian-user/2013/09/msg00126.html Intel processor microcode security update] (fixes the issues when running 32-bit virtual machines in PAE mode)
* [https://web.archive.org/web/20150907195925/http://inertiawar.com/microcode/hawkes_intel_microcode.pdf Notes on Intel Microcode Updates], March 2013, by Ben Hawkes, archived from the original on September 7, 2015
* [https://web.archive.org/web/20030309102752/http://www.eetimes.com/news/97/963news/hole.html Hole seen in Intel's bug-busting feature], ''[[EE Times]]'', 2002, by Alexander Wolfe, archived from the original on March 9, 2003
* [http://www.securiteam.com/securityreviews/5FP0M1PDFO.html Opteron Exposed: Reverse Engineering AMD K8 Microcode Updates], July 26, 2004
* [https://ieeexplore.ieee.org/document/8662722 WepSIM: An Online Interactive Educational Simulator Integrating Microdesign, Microprogramming, and Assembly Language Programming], July 26, 2022 -- [[User:Otr500|Otr500]] ([[User talk:Otr500|talk]]) 21:21, 5 July 2025 (UTC)
::Well, the [https://web.archive.org/web/20050124004424/http://www-03.ibm.com/ibm/history/exhibits/attic3/attic3_016.html Transformer Read-only Store] link would belong in [[Transformer read-only storage]], not in [[Microcode]].
::[http://people.cs.clemson.edu/~mark/uprog.html A Brief History of Microprogramming] strikes me as something that might be worthy of being in a "Further reading" section, if it's not already being used as a reference.
::Unless [https://lists.debian.org/debian-user/2013/09/msg00126.html Intel processor microcode security update] serves as a reference, it strikes me as an irrelevant detail about a particular microcode update for a particular processor; unless some article mentions that update, and uses it as a reference, I'm not convinced it's useful.
::[https://web.archive.org/web/20150907195925/http://inertiawar.com/microcode/hawkes_intel_microcode.pdf Notes on Intel Microcode Updates] might be worthy of a "Further reading" section in [[Intel microcode]], but not here.
::[https://web.archive.org/web/20030309102752/http://www.eetimes.com/news/97/963news/hole.html Hole seen in Intel's bug-busting feature] could be a reference for a claim that writable microcode has risks, rather than as an "External links" item.
::A version of [http://www.securiteam.com/securityreviews/5FP0M1PDFO.html Opteron Exposed: Reverse Engineering AMD K8 Microcode Updates] at https://web.archive.org/web/20210802224145/https://securiteam.com/securityreviews/5FP0M1PDFO/ might belong on an AMD microcode" page if it existed.
::[https://ieeexplore.ieee.org/document/8662722 WepSIM: An Online Interactive Educational Simulator Integrating Microdesign, Microprogramming, and Assembly Language Programming] might be of some interest somewhere, given that [https://wepsim.github.io WepSIM] still appears to be around, but I'm not sure where. [[User:Guy Harris|Guy Harris]] ([[User talk:Guy Harris|talk]]) 02:29, 6 July 2025 (UTC)
| |||