Execute instruction: Difference between revisions

Revision as of 20:03, 30 July 2021

Latest revision as of 15:57, 7 July 2025

(47 intermediate revisions by 10 users not shown)

Line 1:

{{shortShort description|MachineComputer instruction executing another instruction}}

{{Machine code}}

In a [[Instruction set architecture|computer instruction set architecture (ISA)]], an '''execute instruction''' is a [[machine code|machine language instruction]] which treats data as a machine instruction and executes it.

It can be considered a fourth mode of instruction sequencing after [[program counter|ordinary sequential execution]], [[branch (computer science)|branching]], and [[interrupt|interrupting]]ing.<ref name="brooks">{{cite journal|first=F.P.|last=Brooks|author-link=Fred Brooks|title=The execute operations—a fourth mode of instruction sequencing|journal=Communications of the ACM|volume=3|issue=3|pages=168-170168–170|date=March 1960|doi=10.1145/367149.367168|s2cid=37725430|doi-access=free}}</ref> Since it is an instruction that operates on other instructions like the [[repeat instruction]], it has also been classified as a meta-instruction.<ref>{{cite journal|first=George E.|last=Rossman|title=A Course of Study in Computer Hardware Architecture|journal=IEEE Computer|volume=8|issue=12|pages=44–63|date=December 1975|doi=10.1109/C-M.1975.218835|s2cid=977792}}, p. 50<!--no way to mention specific page as well as page range in Cite journal template?--></ref>

==Computer models==

Many computer families introduced in the 1950s and 1960s include ''execute'' instructions: the [[IBM 7030709]]<ref Stretchname="brooks"/> and [[IBM 7090]] (mnemonic:[[Assembly <code>EX</code>,language#Mnemonics|op <code>EXIC</code> mnemonic]]: {{mono|XEC}}),<ref>{{cite manual|publisher=[[IBM]]|title=Reference Manual, 7030IBM 7090 Data Processing System|date=AugustMarch 19611962|page=5036|url=http://www.bitsavers.org/pdf/ibm/70307090/22-65306528-2_7030RefMan4_7090Manual.pdf}}</ref><ref name="brooks"/> the [[IBM 709]]<ref7030 name="brooks"/> and [[IBM 7090Stretch]] (<code>XEC</code>{{mono|EX}}, {{mono|EXIC}}),<ref>{{cite manual|publisher=[[IBM]]|title=Reference Manual, IBM 70907030 Data Processing System|date=MarchAugust 19621961|page=3650|url=http://www.bitsavers.org/pdf/ibm/70907030/22-65286530-4_7090Manual2_7030RefMan.pdf}}</ref>,<ref name="brooks"/> the [[PDP-1]]/[[PDP-4|-4]]/[[PDP-7|-7]]/[[PDP-9|-9]]/[[PDP-15|-15]] (<code>{{mono|XCT</code>}}),<ref>{{cite manual|publisher=[[Digital Equipment Corporation]]|title=Programmed Data Processor-1 Manual|date=1961|page=14|url=http://gordonbell.azurewebsites.net/digital/pdp%201%20manual%201961.pdf}}</ref><ref>{{cite web|first=Bob|last=Supnik|title=Architectural Evolution in DEC's 18b Computers|page=8 (page numbers not shown)|url=http://simh.trailing-edge.com/docs/architecture18b.pdf}}</ref> the [[CDC_1604#The_924UNIVAC 1100/2200 series|CDCUNIVAC 9241100/2200]] (<code>XEC</code>{{mono|EXRI}}),<ref name=924Man>{{cite manual

|url=http://www.bitsavers.org/pdf/univac/1107/UT-2463_CPU_Nov61.pdf

|title=Univac 1107 Central Computer |date=November 1961|page=12{{hyphen}}1}}</ref> the [[CDC 1604#The 924|CDC 924]] ({{mono|XEC}}),<ref name=924Man>{{cite manual

|url=http://bitsavers.informatik.uni-stuttgart.de/pdf/cdc/924/168B_CDC_924_Reference_Manual_Oct62.pdf

|title=Control Data 924 Computer Reference Manual |date=October 1962|page=2{{hyphen}}41}}</ref> the [[PDP-6]]/[[PDP-10|-10]] (<code>{{mono|XCT</code>}}), the [[IBM System/360]] (<code>{{mono|EX</code>}}),<ref name="s360">{{cite manual|publisher=[[IBM]]|title=IBM System/360 Principles of Operation|id=A22-6821-0|date=1964|page=65|url=http://bitsavers.trailing-edge.com/pdf/ibm/360/princOps/A22-6821-0_360PrincOps.pdf}}</ref><!--16, 32, or 48--> the [[GE-600 series|GE-600]]/[[Honeywell 6000 series|Honeywell 6000]] (<code>{{mono|XEC</code>}}, <code>{{mono|XED</code>}}),<ref name="GE635">{{cite manual|publisher=General Electric Computer Department|title=GE-635 System Manual|date=July 1964|page=A{{hyphen}}5|url=http://www.bitsavers.org/pdf/ge/GE-6xx/CPB-371A_GE-635_System_Man_Jul64635_System_Man_196407.pdf}}</ref> the [[SDS 9 Series|SDS-9xx]] (<code>{{mono|EXU</code>}}).,<ref>{{cite manual|publisher=[[Scientific Data Systems]]|title=SDS 92940 ComputerTheory of Operation|id=SDS-98-01-26A|date=JuneMarch 19651967|page=2{{hyphen}}612|url=https://usermanualdoc.wikilagout.org/Documentscience/900505CSDS92ReferenceJun65.31992045100_Computer%20Science/view0_Computer%20History/old-hardware/sds/9xx/940/980126A_940_TheoryOfOperation_Mar67.pdf}}</ref> the [[SDS 92]] ({{mono|EXU}}),<ref>{{cite manual|publisher=[[Scientific Data Systems]]|title=SDS 94092 Theory of Operation|id=SDS-98-01-26AComputer|date=MarchJune 19671965|page=2{{hyphen}}126|url=https://docusermanual.lagoutwiki/Document/900505CSDS92ReferenceJun65.org3199204510/scienceview}}</0_Computer%20Scienceref> and the [[SDS Sigma series]] ({{mono|EXU}}).<ref>{{Cite book |url=http:/0_Computer%20History/old-hardwarewww.bitsavers.org/pdf/sds/9xxsigma/940sigma7/980126A_940_TheoryOfOperation_Mar67900950J_Sigma7_RefMan_Oct73.pdf |title=Xerox SIGMA 7 Computer: Reference Manual |date=October 1973 |publisher=Xerox Corporation |others=90 09 5J; XG46, File No: 1X03 |edition=0 |pages=70–71}}</ref>

Fewer 1970s designs include ''execute'' instructions. An ''execute'' instruction was proposed for: the [[PDP-11ND812|Nuclear Data 812]] inminicomputer 1970,<ref(1971) name="pdp11x">({{cite webmono|first=Ad|last=van de Goor|title=The Execute Instruction|id=PDP-11/40 Technical Memorandum 18|date=September 21, 1970|url=http://bitsavers.informatik.uni-stuttgart.de/pdf/dec/pdp11/memos/700921_The_Execute_Instruction.pdfXCT}}),</ref> but never implemented for it;<ref name="pdp11">{{cite manual|publisher=[[DigitalNuclear EquipmentData, CorporationInc.]]|title=PDP11Principles Processorof Handbook: PDP11/04/34a/44/60/60|date=1979|url=http://bitsavers.org/pdf/dec/pdp11/handbooks/PDP11_Handbook1979.pdf}}</ref> its successor,Programming the [[VAX]], also had no ''execute'' instruction.<ref>{{cite manual|publisher=[[CompaqND812 Computer Corporation]]|titledate=VAX MACRO and Instruction Set Reference Manual1971|idpage=AA-PS6GD-TE|date=April 20014{{hyphen}}4|url=httpshttp://wwwbitsavers.ecetrailing-edge.lsu.educom/ee4720pdf/docnd/vaxND812/ND812_Prog.pdf}}</ref> Architectures with an ''execute'' instruction include: the [[ND812|NuclearHP Data 8123000]] minicomputer (19711972) (<code>XCT</code>{{mono|XEQ}}),<ref>{{cite manual|publisher=[[Nuclear Data, Inc.Hewlett-Packard]]|title=PrinciplesHP of3000 ProgrammingComputer theSystem: ND812Machine ComputerInstruction Set Reference Manual|date=19711980|page=42{{hyphen}}431|url=http://www.bitsavers.trailing-edge.comorg/pdf/ndhp/ND8123000/instrSet/ND812_Prog30000-90022_InsSetRef_Feb80.pdf}}</ref> and the Texas Instruments [[TI-990]] (1975) (<code>X</code>),<ref>{{cite manual|publisher=[[Texas Instruments]]|title=990 Computer Family Systems Handbook|page=3{{hyphen}}28|url=http://www.bitsavers.org/pdf/ti/990/945250-9701_990_Computer_Family_Systems_Handbook_3ed_May76.pdf}}</ref> and theits microprocessor implementation of the same instruction set architectureversion, the [[TMS9900]] microprocessor (1976) (<code>{{mono|X</code>}}).<ref>{{cite manual|publisher=[[Texas Instruments]]|title=TMS 9900 Microprocessor Data Manual|date=December 1976|page=24|url=http://datasheets.chipdb.org/TI/9900/TMS9900_DataManual.pdf}}</ref> The [[Signetics 8X300]] (1976) is a rare microprocessor design with an execute instruction. XEC executes one instruction from a table of 1 to 255 instructions. Most instructions act as single instruction subroutines but branches are used to implement [[jump table]]s.<ref>{{cite web|title=SL8X305 Microcontroller

|url=http://lansdale.com/datasheets/sl8x305_rev0.pdf|publisher=Lansdale Semiconductor Inc.|accessdate=20 June 2017}}</ref> An ''execute'' instruction was proposed for the [[PDP-11]] in 1970,<ref name="pdp11x">{{cite web |last=van de Goor |first=Ad |date=September 21, 1970 |title=The Execute Instruction |url=http://bitsavers.informatik.uni-stuttgart.de/pdf/dec/pdp11/memos/700921_The_Execute_Instruction.pdf |id=PDP-11/40 Technical Memorandum 18}}</ref> but never implemented for it<ref name="pdp11">{{cite manual |url=http://bitsavers.org/pdf/dec/pdp11/handbooks/PDP11_Handbook1979.pdf |title=PDP11 Processor Handbook: PDP11/04/34a/44/60/60 |date=1979 |publisher=[[Digital Equipment Corporation]]}}</ref> or its successor, the [[VAX]].<ref>{{cite manual |url=https://www.ece.lsu.edu/ee4720/doc/vax.pdf |title=VAX MACRO and Instruction Set Reference Manual |date=April 2001 |publisher=[[Compaq Computer Corporation]] |id=AA-PS6GD-TE}}</ref>

Modern instruction sets do not include ''execute'' instructions because they interfere with [[instruction pipeline|pipelining]], [[Prefetch input queue|prefetching]], and other optimizations.{{citation needed|date=July 2021}}

==Semantics==

Line 19 ⟶ 22:

The instruction to be executed, the target instruction, may be in a register or fetched from memory. Some architectures allow the target instruction to itself be an ''execute'' instruction; others do not.

The target instruction is executed as if it were in the memory ___location of the ''execute'' instruction. If, for example, it is a subroutine call instruction, execution is transferred to the subroutine, with the return ___location being the ___location after the ''execute'' instruction. However, some architectures implement variants of the ''execute'' instruction which inhibit branches.<ref name="brooks"/>

The System/360 supports variable-length target instructions. It also supports modifying the target instruction in various ways before executing it. The target instruction [[data alignment|must start on an even-numbered byte]].<ref name="s360"/>

SomeThe architecturesGE-600 supportseries supports execution of a two-instruction sequence of instructionssequences, notablywhich themust GE-600 series. The target instructionsbe [[data alignment#4|must start on an evendoubleword-numbered wordaligned]].<ref name="GE635"/>

Some architectures support an ''execute'' instruction which operates in a different [[Protection ring|protection and address relocation mode]]. For example, the [[Incompatible Timesharing System|ITS]] PDP-10 paging device supports a [[Protection ring|privileged-mode]] <code>{{mono|XCTR</code>}} 'execute relocated' instruction which allows memory reads, writes, or both to use the user-mode page mappings.<ref>{{cite web|first=J.|last=Holloway|title=Hardware Memo 2 - PDP-10 Paging Device|publisher=[[MIT AI Lab]]|date=February 20, 1970|page=11|url=http://www.bitsavers.org/pdf/mit/ai/ai_600dpi/HW_Memo_2_PDP-10_Paging_Device_Feb1970.pdf}}</ref> Similarly, the [[PDP-10#KL10|KL10]] variant of the PDP-10 supports the privileged instruction <code>{{mono|PXCT</code>}} 'previous context XCT'.<ref name="pdp10">{{cite manual|publisher=[[Digital Equipment Corporation]]|title=DECsystem-10, DECSYSTEM-20 Processor Reference Manual|id=AA-H391A-TK, AD-H391A-T1|date=June 1982|page=2{{hyphen}}63|url=https://www.livingcomputers.org/UI/UserDocs/Tops-10-v7-04/3_DECsystem-10_DECSYSTEM-20_Processor_Reference.pdf}}</ref>

The ''execute'' instruction can cause several problems when anone ''execute'' instruction points to another one and so on:

* the processor may be uninterruptableuninterruptible for multiple [[clock cycles]] if the ''execute'' instruction cannot be interrupted in the middle of execution;

* similarly, the processor may go into an infinite loop if the series of ''execute'' instructions is circular and uninterruptableuninterruptible;

* if the ''execute'' instructions are on different [[Page (computer memory)|swap pages]], all of the pages need to be swapped in for the instruction to complete, which can cause [[thrashing (computer science)|thrashing]].

Similar issues arise with [[Addressing mode#multilevel memory indirect|multilevel indirect addressing modes]].

==Applications==

The ''execute'' instruction has several applications:<ref name="brooks"/>

* Functioning as a single-instruction [[subroutine]] without the usual [[Calling convention|overhead of subroutine calls]]; that instruction may call a full subroutine if necessary.<ref name="brooks"/>

* [[Late binding]]

** Implementation of [[call by name]] and other [[thunks]].<ref name="brooks"/>

** A table of execute targets may be used for [[dynamic dispatch]] of the [[method (computer science)|methods]] or [[virtual function]]s of an [[object (computer science)|object]] or [[class (computer science)|class]], especially when the method or function may often be implementable as a single instruction.<ref name="pdp11"/>

** An execute target may contain a [[hooking|hook]] for adding functionality or for debugging; it is normally initialized as a [[NOP (code)|NOP]] which may be overridden dynamically.

** An execute target may change between a fast version of an operation and a fully traced version.<ref>{{cite book|first=Richard P.|last=Gabriel|author-link=Richard P. Gabriel|title=Performance and Evaluation of Lisp Systems|date=August 1985|isbn=9780262070935|page=32|publisher=MIT Press |url=https://www.dreamsongs.com/Files/Timrep.pdf}}</ref><ref>{{cite manual|first=Kent M.|last=Pitman|author-link=Kent Pitman|title=The Revised Maclisp Manual, Sunday Morning Edition|url=https://www.maclisp.info/pitmanual/|section-url=https://www.maclisp.info/pitmanual/system.html#:~:text=Now%20when%20running,the%20ITS%20implementationPURE|atsection=Section "PURE"}}</ref><ref>{{cite manual|first=David A.|last=Moon|author-link=David A. Moon|title=Maclisp Reference Manual|version=Revision 0|date=April 1974|page=181|url=http://www.softwarepreservation.com/projects/LISP/MIT/Moon-MACLISP_Reference_Manual-Apr_08_1974.pdf}}</ref>

* Tracing, monitoring, and emulation

** This may maintain a pseudo-[[program counter]], leaving the normal program counter unchanged.<ref name="brooks"/>

* Executing dynamically generated code, especially when [[memory protection]] prevents executable code from being writable.

* Emulating self-modifying code, especially when it must be [[reentrancy (computing)|reentrant]] or read-only.<ref name="pdp11x"/>

* In the IBM System/360, the ''execute'' instruction can modify bits 8-15 of the target instruction, effectively turning an instruction with a fixed argument (e.g., a length field) into an instruction with a variable argument.

* Privileged-mode ''execute'' instructions as on the KL10 are used by [[Kernel (operating system)|operating system kernels]] to execute operations such as block copies within the virtual space of user processes.

==Notes==