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| name = Network interface controller
| image = Network card.jpg
| caption = A 1990s [[Ethernet]] network interface
| invent-date =
| invent-name =
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| via2_3 = [[Fibre Channel]]
| via2_4 = [[Asynchronous Transfer Mode|ATM]]
| via2_5 = [[
| via2_6 = [[Token Ring]]
| via2_7 = [[ARCNET]]
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| class2 = {{bulleted list|10 Mbit/s|100 Mbit/s|1 Gbit/s}}
| class3 = [[Full-duplex]]:<ref>{{Cite web|title=Port speed and duplex mode configuration|url=http://docs.ruckuswireless.com/fastiron/08.0.70/fastiron-08070-managementguide/GUID-EDD7D44C-A627-4B76-A9FE-D7657FFF62D3.html|access-date=2020-09-25|website=docs.ruckuswireless.com|language=en-US}}</ref><ref>{{Cite web|last=Admin|first=Arista|date=2020-04-23|title=Section 11.2: Ethernet Standards - Arista|url=https://www.arista.com/en/um-eos/eos-section-11-2-ethernet-standards|access-date=2020-09-28|website=Arista Networks|language=en-gb}}</ref>
| class4 = {{bulleted list|2.5 Gbit/s|5 Gbit/s|10 Gbit/s|up to {{nowrap|160 Gbit/s}}}}
| manuf1 = [[Intel]]
| manuf2 = [[Realtek]]
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}}
A '''network interface controller''' ('''NIC''',<!--"Controller" is correct; once upon a time, they might all have been add-in cards, and called "network interface cards", but most of them are probably on the motherboard or in the SoC these days.--> also known as a '''network interface card''',<ref name="Dell"/> '''network adapter''', '''LAN adapter'''
|url = http://www.windowsnetworking.com/articles_tutorials/networking-basics-part1.html
|title = Networking Basics: Part 1 - Networking Hardware
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}}</ref>
Early network interface controllers were commonly implemented on [[expansion card]]s that plugged into a [[computer bus]]. The low cost and ubiquity of the [[Ethernet]] standard means that most newer computers have a network interface built into the [[motherboard]], or is contained into a [[USB]]-connected [[dongle]], although network cards remain available.
Modern network interface controllers offer advanced features such as [[interrupt]] and [[Direct memory access|DMA]] interfaces to the host processors, support for multiple receive and transmit queues, partitioning into multiple logical interfaces, and on-controller network traffic processing such as the [[TCP offload engine]].
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== Implementation ==
[[File:12 early PC network cards.jpg|thumb|12 early ISA 8 bit and 16 bit PC network cards. The lower right-most card is an early wireless network card, and the central card with partial beige plastic cover is a PSTN [[modem]].]]
[[File:Intel Ophir 82571 Dual Port Gigabit Ethernet Controller Die Shot.png|thumb|Intel Ophir 82571 dual-port Gigabit Ethernet controller [[Die (integrated circuit)|die]]]]
Network controllers were originally implemented as expansion cards that plugged into a computer bus. The low cost and ubiquity of the Ethernet standard means that most new computers have a network interface controller built into the motherboard. Newer [[Server (computing)|server]] motherboards may have multiple network interfaces built-in. The Ethernet capabilities are either [[Integrated circuit|integrated]] into the motherboard [[chipset]] or implemented via a low-cost dedicated Ethernet chip. A separate network card is typically no longer required unless additional independent network connections are needed or some non-Ethernet type of network is used. A general trend in computer hardware is towards [[System on a chip|integrating the various components of systems on a chip]], and this is also applied to network interface cards.
An Ethernet network controller typically has an [[8P8C]] socket where the network cable is connected. Older NICs also supplied [[BNC connector|BNC]], or [[Attachment Unit Interface|AUI]] connections. Ethernet network controllers typically support 10 [[
[[File:Qle3442-cu 10gbe nic.jpg|thumb|A [[Qlogic]] QLE3442-CU SFP+ dual-port NIC]]
Modular designs like [[Small
[[
The NIC may include [[ROM]] to store its factory-assigned [[MAC address]].<ref>{{cite web |url=https://www.itprotoday.com/cloud-computing/how-can-i-change-network-adapter-cards-mac-address |title=How can I change a network adapter card's MAC address? |author=John Savill |date=Nov 12, 2000 |access-date=2023-11-06}}</ref>
The NIC may use one or more of the following techniques to indicate the availability of packets to transfer:
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== {{Anchor|RSS|XPS|MULTIQUEUE|NPAR|FLOW-DIRECTOR}}Performance and advanced functionality ==
[[File:ForeRunnerLE 25 ATM Network Interface (1).jpg|thumb|right|An [[Asynchronous Transfer Mode]] (ATM) network interface
[[File:An Intel 82574L Gigabit Ethernet NIC, PCI Express x1 card.jpg|thumb|right|[[Intel]] 82574L [[Gigabit Ethernet]] NIC, a PCI Express ×1 card, which provides two hardware receive queues<ref>{{cite web
| url = http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf
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}}</ref>]]
'''Multiqueue NICs''' provide multiple transmit and receive [[Queue (abstract data type)|queues]], allowing packets received by the NIC to be assigned to one of its receive queues. The NIC may distribute incoming traffic between the receive queues using a [[hash function]]. Each receive queue is assigned to a separate [[interrupt]]; by routing each of those interrupts to different [[CPU]]s or [[Multi-core processor|CPU cores]], processing of the interrupt requests triggered by the network traffic received by a single NIC can be distributed improving performance.<ref name="linux-net-scaling">{{cite web
| url = https://www.kernel.org/doc/Documentation/networking/scaling.txt
| title = Linux kernel documentation: Documentation/networking/scaling.txt
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| publisher = [[Intel]] }}</ref>
The hardware-based distribution of the interrupts, described above, is referred to as
| url = http://www.intel.com/content/dam/technology-provider/secure/us/en/documents/product-marketing-information/tst-grantley-launch-presentation-2014.pdf
| title = Intel Look Inside: Intel Ethernet
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| archive-url = https://web.archive.org/web/20150326095816/http://www.intel.com/content/dam/technology-provider/secure/us/en/documents/product-marketing-information/tst-grantley-launch-presentation-2014.pdf
| archive-date = March 26, 2015
}}</ref>{{rp|82}} Purely software implementations also exist, such as the [[receive packet steering]] (RPS)
| url = https://www.kernel.org/doc/Documentation/networking/ixgbe.txt
| title = Linux kernel documentation: Documentation/networking/ixgbe.txt
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| title = Introduction to Intel Ethernet Flow Director and Memcached Performance
| date = October 14, 2014 | access-date = October 11, 2015
| publisher = [[Intel]] }}</ref> Further performance improvements can be achieved by routing the interrupt requests to the CPUs or cores executing the applications that are the ultimate destinations for [[network packet]]s that generated the interrupts. This technique improves [[locality of reference]] and results in higher overall performance, reduced latency and better hardware utilization because of the higher utilization of [[CPU cache]]s and fewer required [[context switch]]es.
With multi-queue NICs, additional performance improvements can be achieved by distributing outgoing traffic among different transmit queues. By assigning different transmit queues to different CPUs or CPU cores, internal operating system contentions can be avoided. This approach is usually referred to as '''transmit packet steering''' (XPS).<ref name="linux-net-scaling" />
Some products feature '''NIC partitioning''' ('''NPAR''', also known as '''port partitioning''') that uses [[SR-IOV]] virtualization to divide a single 10 Gigabit Ethernet NIC into multiple discrete virtual NICs with dedicated bandwidth, which are presented to the firmware and operating system as separate [[PCI device function]]s.<ref name="Dell">{{cite web
| url = http://www.dell.com/downloads/global/products/pedge/en/Dell-Broadcom-NPAR-White-Paper.pdf
| title = Enhancing Scalability Through Network Interface Card Partitioning
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| date = September 2011 | access-date = September 24, 2015
| author1 = Patrick Kutch | author2 = Brian Johnson | author3 = Greg Rose
| publisher = [[Intel]] }}</ref>
Some NICs provide a [[TCP offload engine]]
| url = https://lwn.net/Articles/243949/
| title = Large receive offload
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{{Anchor|SOLARFLARE|OPENONLOAD|USER-LEVEL-NETWORKING}}
Some NICs offer integrated [[field-programmable gate array]]s (FPGAs) for user-programmable processing of network traffic before it reaches the host computer, allowing for significantly reduced [[Latency (engineering)|latencies]] in time-sensitive workloads.<ref>{{cite web|title=High Performance Solutions for Cyber Security|url=http://newwavedv.com/markets/defense/cyber-security/|website=New Wave Design & Verification|publisher=New Wave DV}}</ref> Moreover, some NICs offer complete low-latency [[TCP/IP stack]]s running on integrated FPGAs in combination with [[userspace]] libraries that intercept networking operations usually performed by the [[operating system kernel]]; Solarflare's open-source '''OpenOnload''' network stack that runs on [[Linux]] is an example. This kind of functionality is usually referred to as '''user-level networking'''.<ref>{{cite web
| url = https://www.theregister.co.uk/2012/02/08/solarflare_application_onload_engine/
| title = Solarflare turns network adapters into servers: When a CPU just isn't fast enough
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