Automatic test pattern generation: Difference between revisions

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{{Short description|Electronic design automation method}}

'''ATPG''' (acronym for both '''A'''utomaticautomatic '''T'''esttest '''P'''atternpattern generation'''G'''eneration and '''A'''utomaticautomatic '''T'''esttest '''P'''atternpattern generator'''G'''enerator) is an [[electronic design automation]] method/ or technology used to find an input (or test) sequence that, when applied to a [[digital circuit]], enables [[automatic test equipment]] to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects. The generated patterns are used to test semiconductor devices after manufacture, or to assist with determining the cause of failure ([[failure analysis]]<ref>{{cite conference| last=Crowell| first=G| author2=Press, R.| title=Using Scan Based Techniques for Fault Isolation in Logic Devices| booktitlebook-title=Microelectronics Failure Analysis | pages= 132–8}}</ref>). The effectiveness of ATPG is measured by the number of modeled defects, or [[fault models]], detectable and by the number of generated patterns. These metrics generally indicate [[test quality]] (higher with more fault detections) and test application time (higher with more patterns). ATPG efficiency is another important consideration that is influenced by the fault model under consideration, the type of circuit under test ([[Scan chain|full scan]], synchronous sequential, or asynchronous sequential), the level of abstraction used to represent the circuit under test (gate, register-transfer, switch), and the required [[Fault coverage|test quality]].

== Basics ==

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* The '''D Algorithm''' was the first practical test generation [[algorithm]] in terms of memory requirements. The D Algorithm [proposed by Roth 1966] introduced '''D Notation''' which continues to be used in most ATPG algorithms. D Algorithm tries to propagate the stuck at fault value denoted by D (for SA0) or {{overline|D}} (for SA1) to a primary output.

* '''Path-Oriented Decision Making''' (PODEM) is an improvement over the D Algorithm. PODEM was created in 1981, by [[Prabhu Goel]], when shortcomings in D Algorithm became evident when design innovations resulted in circuits that D Algorithm could not realize.

* '''Fan-Out Oriented''' ([[FAN Algorithmalgorithm]]) is an improvement over PODEM. It limits the ATPG search space to reduce computation time and accelerates backtracing.

*Methods based on [[Boolean satisfiability]] are sometimes used to generate test vectors.

*'''Pseudorandom test generation''' is the simplest method of creating tests. It uses a [[pseudorandom]] number generator to generate test vectors, and relies on [[logic simulation]] to compute good machine results, and fault simulation to calculate the fault coverage of the generated vectors.

* '''Wavelet Automatic Spectral Pattern Generator''' (WASP) is an improvement over spectral algorithms for sequential ATPG. It uses wavelet heuristics to search space to reduce computation time and accelerate the compactor. It was put forward by [[Suresh kumar Devanathan]] from Rake Software and Michael Bushnell, Rutgers University. [[Suresh kumar Devanathan]] invented WASP as a part of his thesis at Rutgers.{{citation needed|date=November 2019}}

== Relevant conferences ==

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*{{cite book| title=Microelectronics Failure Analysis | year=2004 |publisher=ASM International | ___location=Materials Park, Ohio| isbn= 0-87170-804-3 }}

<references/>

== Further reading==

[[Category:Electronic circuit verification]]