Pulse transition detector: Difference between revisions

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{{short description|Flip-flop logic gate}}

{{Unreferenced stub|auto=yes|date=December 2009}}

{{Article issuesUnreferenced|wikify date=December 2009|orphan =November 2006}}

A '''Pulsepulse transition detector'''<ref>{{cite web |title=T Is for Toggle: Understanding the T Flip-Flop - Technical Articles |url=https://www.allaboutcircuits.com/technical-articles/t-is-for-toggle-understanding-the-t-flip-flop/ |website=allaboutcircuits.com |access-date=22 July 2025 |language=en}}</ref> is used in [[Flip-flop (electronics)|flip flops]] in order to achieve [[signal edge|edge]] triggering in the [[Electronic circuit|circuit]]. It merely converts the [[clock signal]]'s [[Clock edge|rising edge]] to a very narrow pulse.

The PTD consists of a delay gate (which delays the [[clock signal]]) and the clock signal itself passed through a [[NAND gate]] and then inverted.

The benefit of edge triggering is that it removes the problems of zeroes and ones catching associated with pulse triggered flipflopsflip-flops (ege.g. [[Flip-flop_(electronics)#Master.E2.80.93slave_.28pulseMaster–slave edge-triggered.29_D_flip D flip-flop|master slave flip flops]]).

The PTD consists of a delay gate (which delays the [[clock signal]]) and the clock signal itself passed through a [[NAND gate]] and then inverted.

==References==

The benefit of edge triggering is that it removes the problems of zeroes and ones catching associated with pulse triggered flipflops (eg. [[Flip-flop_(electronics)#Master.E2.80.93slave_.28pulse-triggered.29_D_flip-flop|master slave flip flops]]).

{{Reflist}}

{{DEFAULTSORT:Pulse Transition Detector}}