Content deleted Content added
JohnGDallman (talk | contribs) →Features: Clarify floating point register numbers. |
|||
| (42 intermediate revisions by 16 users not shown) | |||
Line 4:
| designer = [[IBM]]
| bits = 32-bit
| introduced = {{Start date and age|1964|4|7}}
| version =
| design = [[Complex instruction set computing|CISC]]
| type = Register-Register<br />Register-Memory<br />Memory-Memory
| encoding = Variable <small>(2, 4 or 6 bytes long)</small>
Line 39:
| style="width:.5%; text-align:left; border-style: none none none none;" |
| colspan=32 | Two's complement value
| style="width:.5%; text-align:left; border-style: none none none none;" |
|-
| style="width:.5%; text-align:left; border-style: none none none none;" |
Line 78 ⟶ 79:
| style="border-style: none;" |
{| class="wikitable" style="font-size:75%"
|+ Floating Point Registers 0
|-
| colspan=34 style="border-style: none;" | <br>
Line 86 ⟶ 87:
| colspan=7 | Biased exponent
| colspan=24 | Mantissa
| style="width:.5%; text-align:left; border-style: none none none none;" |
|-
| style="width:.5%; text-align:left; border-style: none none none none;" |
Line 125 ⟶ 127:
|-
| style="width:.5%; text-align:left; border-style: none none none none;" |
| style="width:.5%; text-align:left; border-style: none none none none;" |
|-
Line 217 ⟶ 219:
| style="width:.5%; text-align:left; border-style: none none none none;" |
|-
| colspan=34 style="border-style: none;" | <br>
|-
| style="width:.5%; text-align:left; border-style: none none none none;" |
Line 224 ⟶ 226:
| colspan=4 | Program<br>Mask
| colspan=24 | Instruction Address
| style="width:.5%; text-align:left; border-style: none none none none;" |
|-
| style="width:.5%; text-align:left; border-style: none none none none;" |
Line 316 ⟶ 319:
|
{| class="wikitable mw-collapsible autocollapse"
|+ style="text-align: left; font-size:95%" | {{nowrap|Program Mask}}
! Bit
! Meaning
Line 354 ⟶ 357:
==Memory==
Memory (''storage'') in System/360 is addressed in terms of [[8-bit]] bytes. Various instructions operate on larger units called ''halfword'' (2 bytes), ''fullword'' (4 bytes), ''doubleword'' (8 bytes), ''quad word'' (16 bytes) and 2048 byte storage block, specifying the leftmost (lowest address) of the unit. Within a halfword, fullword, doubleword or quadword, low numbered bytes are more significant than high numbered bytes; this is sometimes referred to as [[
The original architecture of System/360 provided for up to 2<sup>24</sup> = 16,777,216 bytes of memory. The later [[IBM System/360 Model 67|Model 67]] extended the architecture to allow up to 2<sup>32</sup> = 4,294,967,296
==Addressing==
Line 366 ⟶ 369:
| publisher = Sperry Rand Corporation
}}
</ref> That means that instructions do not contain complete addresses, but rather specify a base register and a positive offset from the addresses in the base registers. In the case of System/360 the base address is contained in one of 15
==Data formats==
Line 390 ⟶ 393:
{{main|Program Status Word}}
The '''Program Status Word''' ('''PSW''')<ref name=A22-6821-7/>{{rp|pages=71–72}} contains a variety of controls for the currently operating program. The 64-bit PSW describes (among other things) the address of the current instruction being executed, condition code and interrupt masks.
{| class="wikitable collapsible"
Line 401 ⟶ 404:
| align=center valign=top | 0-7
| valign=top style="align:left;" | {{anchor|System_Mask}}System Mask
| valign=top | bits 0-5: enable channels 0-5, bit 6: enable all remaining channels,{{
|-
| align=center valign=top | 8-11
Line 409 ⟶ 412:
| align=center valign=top | 12{{anchor|AMWP}}
| valign=top | ASCII mode
| enable ASCII mode for packed decimal instructions, never used by IBM software
|-
| align=center valign=top | 13
Line 425 ⟶ 428:
| align=center valign=top | 16-31
| valign=top | {{anchor|Interruption_Code}}Interruption Code
| code to indicate the type of interruption, inserted when the PSW is stored, during IPLoad, this is the address of the device from which the program was loaded
|-
| align=center valign=top | 32-33
Line 437 ⟶ 440:
| align=center valign=top | 36-39
| valign=top | {{anchor|Program_Mask}}Program Mask
| bit 36: enable fixed-point overflow, bit 37: decimal overflow, bit 38: exponent underflow, bit 39: significance
|-
| align=center valign=top|40-63
Line 448 ⟶ 451:
==Interruption system==
The architecture<ref name=A22-6821-7/>{{rp|pages=77–83}} defines 5 classes of [[interrupt]]ion. An interruption is a mechanism for automatically changing the program state; it is used for both synchronous
{| class="wikitable"
|-
! rowspan="2" | Interruption class !! colspan="2" | Old PSW !! colspan="2" | New PSW
! rowspan="2" | Priority
|-
!
|-
| [[#Input/Output interruption|Input/Output]]
|-
| [[#Program interruption|Program]]
|-
| [[#Supervisor Call interruption|Supervisor Call]]
|-
| [[#External interruption|External]]
|-
| [[#Machine Check interruption|Machine Check]]
|}
Line 471 ⟶ 476:
===Input/Output interruption===
An I/O interruption
===Program interruption===
A Program interruption<ref name=A22-6821-7/>{{rp|pages=16,79–80.1}} occurs when an instruction encounters one{{
On 360/65,<ref name=A22-6884/>{{rp|page=12}} 360/67<ref name=GA27-2719/>{{rp|page=46}} and 360/85<ref name=A22-6916/>{{rp|page=12}} the Protection Exception and Addressing Exception interruptions can be imprecise, in which case they store an Instruction Length Code of 0.
The Interruption code may be any of
Line 488 ⟶ 493:
| align=right valign=top | 0
|
Imprecise interruption
{| class="wikitable collapsible collapsed"
|+ {{nowrap|Old PSW bits for multiple imprecise interruption codes}}
Line 502 ⟶ 507:
|-
| 18
| Specification
|-
| 19
Line 526 ⟶ 531:
|-
| 26
| Decimal Overflow
|-
| 27
| Decimal Divide
|}
|-
| align=right | 1
| align=right | 1
| [[#Operation exception|Operation]]
|-
| align=right | 2
| align=right | 2
| [[#Privileged operation exception|Privileged operation]]
|-
| align=right | 3
| align=right | 3
| [[#Execute exception|Execute]]
|-
| align=right | 4
| align=right | 4
| [[#Protection exception|Protection]]
|-
| align=right | 5
| align=right | 5
| [[#Addressing exception|Addressing]]
|-
| align=right | 6
| align=right | 6
| [[#Specification exception|Specification]]
|-
| align=right | 7
| align=right | 7
| [[#Data exception|Data]]
|-
| align=right | 8
| align=right | 8
| [[#Fixed-point overflow exception|Fixed-point overflow]]
|-
| align=right | 9
| align=right | 9
| [[#Fixed-point divide exception|Fixed-point divide]]
|-
| align=right | A
| align=right | 10
| [[#Decimal overflow exception|Decimal overflow]]
|-
| align=right | B
| align=right | 11
| [[#Decimal divide exception|Decimal divide]]
|-
| align=right | C
| align=right | 12
| [[#Exponent overflow exception|Exponent overflow]]
|-
| align=right | D
| align=right | 13
| [[#Exponent underflow exception|Exponent underflow]]
|-
| align=right | E
| align=right | 14
| [[#Significance exception|Significance]]
|-
| align=right | F
| align=right | 15
| [[#Floating-point divide exception|Floating-point divide]]
|-
| align=right | 10
| align=right | 16
|
Segment Translation<ref name=GA27-2719/>{{rp|page=17}}
|-
| align=right | 11
| align=right | 17
|
Page Translation<ref name=GA27-2719/>{{rp|page=17}}
|-
| align=right | 12
| align=right | 18
|
SSM Exception<ref name=A22-6884/>
|}
* An '''operation exception'''
* A '''privileged operation exception'''
* An '''execute exception'''
* A '''protection exception'''
* An '''addressing exception'''
*A '''specification exception'''
* A '''data exception'''
* A '''fixed-point overflow exception'''
* A '''fixed-point divide exception'''
* A '''decimal overflow exception'''
* A '''decimal divide exception'''
* An '''exponent overflow exception'''
* An '''exponent underflow exception'''
* A '''significance exception'''
* A '''floating-point divide exception'''
===Supervisor Call interruption===
A Supervisor Call interruption
===External interruption===
An External
{| class="wikitable collapsible"
Line 670 ⟶ 675:
===Machine Check interruption===
A Machine Check interruption
==Input/Output==
{{further|topic=physical interface|Bus and Tag}}
This article describes I/O from the CPU perspective. It does not discuss the channel cable or connectors,
| title = I/O Channel Interface
| id = FIPS PUB 60-2
| date = July 29, 1983
| url = https://nvlpubs.nist.gov/nistpubs/Legacy/FIPS/fipspub60-2.pdf
| publisher = [[National Technical Information Service]]
| access-date = May 18, 2023
}}
</ref>
I/O is carried out by a conceptually separate processor called a channel. Channels have their own instruction set, and access memory independently of the program running on the CPU. On the smaller models (through [[IBM System/360 Model 50|360/50]]) a single microcode engine runs both the CPU program and the channel program. On the larger models the channels are in separate cabinets and have their own interfaces to memory. A channel may contain multiple '''subchannel'''s, each containing the status of an individual channel program. A subchannel associated with multiple devices that cannot concurrently have channel programs is referred to as '''shared'''; a subchannel representing a single device is referred to as '''unshared'''.
Line 681 ⟶ 695:
* {{anchor|IBM_Byte_Mux}}A '''byte multiplexer channel''' is capable of executing multiple '''CCW'''s concurrently; it is normally used to attach slow devices such as card readers and telecommunications lines. A byte multiplexer channel could have a number of selector subchannels, each with only a single subchannel, which behave like low-speed selector channels.
* {{anchor|IBM_Sel}}A '''selector channel''' has only a single subchannel, and hence is only capable of executing one channel command at a time. It is normally used to attach fast devices that are not capable of exploiting a block multiplexer channel to suspend the connection, such as magnetic tape drives.
* {{anchor|IBM_Blk_Mux}}A '''block multiplexer channel''' is capable of concurrently running multiple channel programs, but only one at a time can be active. The control unit can request suspension at the end of a channel command and can later request resumption. This is intended for devices in which there is a mechanical delay after completion of data transfer, e.g., for seeks on moving-head DASD. The block multiplexer channel was a late addition to the System/360 architecture; early machines had only byte multiplexer channels and selector channels. The block multiplexer channel
Conceptually peripheral equipment is attached to a S/360 through ''control units'', which in turn are attached through channels. However, the architecture does not require that control units be physically distinct, and in practice they are sometimes integrated with the devices that they control. Similarly, the architecture does not require the channels to be physically distinct from the processor, and the smaller S/360 models (through 360/50) have integrated channels that [[Cycle stealing|steal cycles]] from the processor.
Peripheral devices are addressed with 16-bit
Control units are assigned an address "capture" range. For example, a CU might be assigned range 20-2F or 40-7F. The purpose of this is to assist with the connection and prioritization of multiple control units to a channel. For example, a channel might have three disk control units at 20-2F, 50-5F, and 80-8F. Not all of the captured addresses need to have an assigned physical device. Each control unit is also marked as High or Low priority on the channel.
Device selection progresses from the channel to each control unit in the order they are physically attached to their channel. At the end of the chain the selection process continues in reverse back towards the channel. If the selection returns to the channel then no control unit accepted the command and SIO returns Condition Code 3. Control units marked as High Priority check the outbound CUU to be within their range. If so, then the I/O
There are three storage fields reserved for I/O; a double word I/O old PSW, a doubleword I/O new PSW and a fullword ''Channel Address Word'' ('''CAW'''). Performing an I/O normally requires the following:
* initializing the '''CAW''' with the storage key and the address of the first CCW
* issuing a ''Start I/O'' ('''SIO''') instruction that specifies the ''cuu'' for the operation
* waiting
* handling any unusual conditions indicated in the ''Channel Status Word'' ('''CSW''')
Line 706 ⟶ 720:
===Channel status===
These conditions are detected by the channel and indicated in the [[#Channel Status Word|CSW]].
* {{Anchor|Program-controlled_interruption status|PCI status}}'''[[#CSW_Program-controlled_interruption status|Program-controlled interruption]]'''
* {{Anchor|Incorrect length|IL}}'''[[#CSW_Incorrect_length|Incorrect length]]'''
* '''[[#CSW_Program_check|Program check]]'''
** Nonzero bits where zeros are required
** An invalid data or CCW address
** The CAW or a TIC refers to a TIC
* {{Anchor|Protection check}}'''[[#CSW_Protection_check|Protection check]]'''
* {{Anchor|Channel data check|CDC}}'''[[#CSW_Channel_data_check|Channel data check]]'''
* {{Anchor|Channel control check|CCC}}'''[[#CSW_Channel_control_check|Channel control check]]'''
* {{Anchor|Interface control check|ICC}}'''[[#CSW_Interface_control_check|Interface control check]]'''
* {{Anchor|Chaining check}}'''[[#CSW_Chaining_check|Chaining check]]'''
===Unit status===
These conditions are presented to the channel by the control unit or device.
* {{Anchor|Attention}}'''[[#CSW_Attention|Attention]]'''
* {{Anchor|Status modifier|SM}}'''[[#CSW_Status_modifier|Status modifier]]'''
** A Test I/O instruction was issued to a device that does not support it.
** A [[#Busy|Busy]] status refers to the control unit rather than to the device.
Line 738 ⟶ 752:
:: where the TIC causes the channel to refetch the search until the device indicates a successful search by raising SM.
* {{Anchor|Control unit end}}'''[[#CSW_Control_unit_end|Control unit end]]'''
* {{Anchor|Busy}}'''[[#CSW_Busy|Busy]]'''
* {{Anchor|Channel end|CE}}'''[[#CSW_Channel_end|Channel end]]'''
* {{Anchor|Device end|DE}}'''[[#CSW_Device_end|Device end]]'''
* {{Anchor|Unit check|UC}}'''[[#CSW_Unit_check|Unit check]]'''
* {{Anchor|Unit exception|UE}}'''[[#CSW_Unit_exception|Unit exception]]'''
===Channel Address Word===
Line 750 ⟶ 764:
===Channel Command Word===
A ''Channel Command Word'' is a doubleword containing the following:
* an 8-bit channel [[#CCW Command codes|Command Code]]
* a 24-bit address
* a 5-bit flag field
* an unsigned halfword Count field
====CCW Command codes====
Line 767 ⟶ 781:
|-
| style="font-family:monospace" | MMMM 0100
| Sense
|-
| style="font-family:monospace" | **** 1000
| Transfer in Channel (TIC)
|-
| style="font-family:monospace" | MMMM 1100
| Read Backward
|-
| style="font-family:monospace" | MMMM MM01
| Write
|-
| style="font-family:monospace" | MMMM MM10
| Read
|-
| style="font-family:monospace" | MMMM MM11
| Control
|}
Line 807 ⟶ 821:
| valign=top | {{anchor|CCW-CD}}CD
| valign=top | {{anchor|CCW-ChainData}}Chain-Data
| Continue operation using the storage area defined by the next CCW.
|-
|-
Line 813 ⟶ 827:
| valign=top | {{anchor|CCW-CC}}CC
| valign=top | {{anchor|CCW-ChainCommand}}Chain-Command
| Continue with the Command in the next CCW.
|-
| align=right valign=top | 34
| valign=top | {{anchor|CCW-SLI}}SLI
| valign=top | {{anchor|CCW-SuppressLengthindication}}Suppress-Length-Indication
| Continue channel program after count mis-match.
|-
| align=right valign=top | 35
| valign=top | {{anchor|CCW-SKIP}}SKIP
| valign=top | Skip
| Do not read from or write into storage.| Do not read from or write into storage.
|-
| align=right valign=top | 36
| valign=top | {{anchor|CCW-PCI}}PCI
| valign=top | {{anchor|CCW-ProgramControlledInterupt}}Program-Controlled-Interruption
| Request interruption when fetching CCW.
|}
Line 841 ⟶ 855:
|-
| align=right | 0-3
| Key
|-
| align=right | 4-7
Line 847 ⟶ 861:
|-
| align=right | 8-31
| Command Address
|-
| align=right | 32-47
| Status
|-
| align=right valign=top | 32-39
| valign=top |
: Unit Status Conditions
: Detected by the device or control unit
|-
| align=right | {{anchor|CSW_Attention}}32
|
: [[#Attention|Attention]]
|-
| align=right | {{anchor|CSW_Status_modifier}}33
|
: [[#Status modifier|Status modifier]]
|-
| align=right | {{anchor|CSW_Control_unit_end}}34
|
: [[#Control unit end|Control unit end]]
|-
| align=right | {{anchor|CSW_Busy}}35
|
: [[#Busy|Busy]]
|-
| align=right | {{anchor|CSW_Channel_end}}36
|
: [[#Channel end|Channel end]]
|-
| align=right | {{anchor|CSW_Device_end}}37
|
: [[#Device end|Device end]]
|-
| align=right | {{anchor|CSW_Unit_check}}38
|
: [[#Unit check|Unit check]]
|-
| align=right | {{anchor|CSW_Unit_exception}}39
|
: [[#Unit exception|Unit exception]]
|-
| align=right valign=top | 40-47
| valign=top |
: Channel Status Conditions
: Detected by the channel.
|-
| align=right | {{anchor|CSW_Program-controlled_interruption_status}}40
|
: [[#Program-controlled interruption status|Program-controlled interruption]]
|-
| align=right | {{anchor|CSW_Incorrect_length}}41
|
: [[#Incorrect length|Incorrect length]]
|-
| align=right | {{anchor|CSW_Program_check}}42
|
: [[#Program check|Program check]]
|-
| align=right | {{anchor|CSW_Protection_check}}43
|
: [[#Protection check|Protection check]]
|-
| align=right | {{anchor|CSW_Channel_data_check}}44
|
: [[#Channel data check|Channel data check]]
|-
| align=right | {{anchor|CSW_Channel_control_check}}45
|
: [[#Channel control check|Channel control check]]
|-
| align=right | {{anchor|CSW_Interface_control_check}}46
|
: [[#Interface control check|Interface control check]]
|-
| align=right | {{anchor|CSW_Chaining_check}}47
|
: [[#Chaining check|Chaining check]]
|-
| align=right | 48-63
| Count
|}
* The '''Protection Key''' field contains the protect key from the CAW at the time that the I/O operation was initiated for I/O complete or PCI interruptions.
* The '''Command Address''' field contains the address+8 of the last CCW fetched for an I/O complete or PCI interruption. However, there are 9 exceptions
* The '''Status''' field contains one byte of [[#Channel status|Channel status]] bits, indicating conditions detected by the channel
* The '''Residual Count''' is a half word that gives the number of bytes in the area described by the CCW that have not been transferred to or from the channel
===I/O instructions===
The S/360 has four{{sfn|S360|loc=[http://bitsavers.org/pdf/ibm/360/princOps/A22-6821-7_360PrincOpsDec67.pdf#page=105 Control of Input/Output Devices]|pp=93-98}} I/O instructions: Start I/O (SIO), Test I/O (TIO), Halt I/O (HIO) and Test Channel (TCH). All four are privileged and thus will cause a privileged operation program interruption if used in problem state. The B<sub>1</sub> (base) and D<sub>1</sub> (displacement) fields are used to calculate the cuu (channel and device number); bits 8-15 of the instructions are unused and should be zero for compatibility with the S/370.
====Start I/O (SIO)====
SIO{{sfn|S360|loc=[http://bitsavers.org/pdf/ibm/360/princOps/A22-6821-7_360PrincOpsDec67.pdf#page=106 Start I/O]|pp=94-95}} attempts to start the channel program pointed to by the [[#Channel Address Word|CAW]], using the storage protection key in the CAW.
====Test I/O (TIO)====
TIO{{sfn|S360|loc=[http://bitsavers.org/pdf/ibm/360/princOps/A22-6821-7_360PrincOpsDec67.pdf#page=107 Test I/O]|pp=95-96}} tests the status of a channel and device. It may also store a [[# Channel Status Word|CSW]], in which case it completes with condition code 1.
====Halt I/O (HIO)====
HIO{{sfn|S360|loc=[http://bitsavers.org/pdf/ibm/360/princOps/A22-6821-7_360PrincOpsDec67.pdf#page=108 Halt I/O]|pp=96-98}} attempt to terminate an active channel program. It may also store a [[# Channel Status Word|CSW]], in which case it completes with condition code 1.
====Test Channel (TCH)====
TCH{{sfn|S360|loc=[http://bitsavers.org/pdf/ibm/360/princOps/A22-6821-7_360PrincOpsDec67.pdf#page=110 Test Channel]|p=98}} tests the status of a channel. It does not affect the status of an active channel program and does not store a [[# Channel Status Word|CSW]],
==Operator controls==
Line 941 ⟶ 971:
* '''System Reset''' sends a reset signal on every I/O channel and clears the processor state; all pending interruptions are cancelled. System Reset is not guaranteed to correct parity errors in general registers, floating point registers or storage. System Reset does not reset the state of shared I/O devices.
* '''{{anchor|Initial_Program_Load}}Initial Program Load''' (IPL)
:: As part of the IPL facility the operator has a means of specifying a 12-bit
:: Initial program loading is typically done from a tape, a card reader, or a disk drive. Generally, the operating system was loaded from a disk drive; IPL from tape or cards was used only for diagnostics or for installing an operating system on a new computer.
* '''Emergency pull switch'''
* '''Power on'''
* '''Power off'''
* The '''Interrupt''' key
* The '''Wait light'''
* The '''Manual light'''
* The '''System light'''
* The '''Test light'''
* The '''Load light'''
* The '''Load unit'''
* The '''Load Key'''
* The '''Prefix Select Key Switch'''
* The '''System-Reset Key'''
* The '''Stop Key'''
* The '''Rate Switch'''
** PROCESS
** INSTRUCTION STEP
* The '''Start Key'''
* The '''Storage-Select Switch'''
** Main storage
** General registers
** Floating-point registers
* The '''Address Switches'''
* The '''Data Switches'''
* The '''Store Key'''
* The '''Display Key'''
* The '''Set IC='''
* The '''Address-Compare Switches'''
* The '''Alternate-Prefix Light'''
==Optional features==
===Byte-aligned operands===
On some models, e.g., the [[IBM System/360 Model 85|S/360-85]],<ref name=A22-6916/> the alignment requirements for some problem-state instructions were relaxed. There is no mechanism to turn off this feature, and programs depending on receiving a program check type 6 (alignment) on those instructions must be modified.
===Decimal arithmetic===
Line 985 ⟶ 1,015:
===Direct Control===
The ''Direct Control''
===Floating-point arithmetic===
Line 994 ⟶ 1,024:
===Multi-system operation===
''Multi-system operation''
===Storage protection===
Line 1,018 ⟶ 1,048:
==Notes==
{{notelist}}
==References==
;'''S360'''
:{{cite
| title = IBM System/360 Principles of Operation
| id = A22-6821-7
Line 1,028 ⟶ 1,058:
| edition = Eighth
| ref = {{sfnref|S360}}
|
| publisher = IBM
}}
<!-- See http://en.wikipedia.org/wiki/Wikipedia:Footnotes on how to create references using <ref></ref> tags which will then appear here automatically -->
{{Reflist| refs=
<ref name=A22-6821>{{cite
| author = IBM
| title = IBM System/360 Principles of Operation
Line 1,042 ⟶ 1,072:
| mode = cs2
}}</ref>
<ref name=A22-6821-7>{{cite
| author = IBM
| title = IBM System/360 Principles of Operation
| id = A22-6821-7
| ref = {{sfnref|PoOps}}
| date = September 1968
| version = Eighth Edition
| url = http://bitsavers.org/pdf/ibm/360/princOps/A22-6821-7_360PrincOpsDec67.pdf
| mode = cs2
}} Revised by {{cite
| author = IBM
| title = ibid.
Line 1,057 ⟶ 1,087:
| date = May 12, 1970
| mode = cs2
}} and {{cite
| author = IBM
| title = ibid.
Line 1,064 ⟶ 1,094:
| mode = cs2
}}</ref>
<ref name=A22-6843>{{cite
| author = IBM
| title = IBM System/360 I/O Interface Channel to Control Unit Original Equipment Manufacturers' Information
Line 1,073 ⟶ 1,103:
| mode = cs2
}}</ref>
<ref name=A22-6845>{{cite
| author = IBM
| title = IBM System/360 Direct Control and External Interrupt Features Original Equipment Manufacturers' Information
Line 1,081 ⟶ 1,111:
| mode = cs2
}}</ref>
<ref name=A22-6884>{{cite
| author = IBM
| title = IBM System/360 Model 65 Functional Characteristics
Line 1,092 ⟶ 1,122:
| mode = cs2
}}</ref>
<ref name=A22-6907>{{cite
| author = IBM
| title = IBM System/360 Model 91 Functional Characteristics
Line 1,102 ⟶ 1,132:
| mode = cs2
}}</ref>
<ref name=A22-6916>{{cite
| author = IBM
| title = IBM System/360 Model 85 Functional Characteristics
Line 1,111 ⟶ 1,141:
| mode = cs2
}}</ref>
<ref name=A22-6943>{{cite
| author = IBM
| title = IBM System/360 Model 195 Functional Characteristics
Line 1,120 ⟶ 1,150:
| mode = cs2
}}</ref>
<ref name=GA27-2719>{{cite
| author = IBM
| title = IBM System/360 Model 67 Functional Characteristics
Line 1,141 ⟶ 1,171:
| isbn = 0070506868
| url-access = registration
| url = https://archive.org/details/ibmmainframesarc00pras}} {{mdash}} Chapter 3 (pp.
* {{cite conference
| conference = SHARE 117 in Orlando
| conference-url = https://share.confex.com/share/117/webprogram/start.html
| title = Evolution of The IBM Mainframe Architecture
| id = Session 9220
| first = Dan
| last = Greiner
| date = August 10, 2011
| section = IBM z/Architecture CPU Features - A Historical Perspective
| section-url = https://share.confex.com/share/117/webprogram/Handout/Session9220/IBM%20zArchitecture%20CPU%20History.pdf
| url = https://share.confex.com/share/117/webprogram/Session9220.html
| publisher = [[SHARE (computing)|SHARE]]
| access-date = February 7, 2023
}}
==External links==
Line 1,147 ⟶ 1,191:
{{DEFAULTSORT:Ibm System 360 Architecture}}
[[Category:Computing platforms]]
[[Category:IBM System/360 mainframe line|architecture]]
[[Category:
[[Category:Computer-related introductions in 1964]]
| |||