|
| style="border-style: none;" |
{| class="wikitable" style="font-size:75%"
|+ Floating Point Registers 0-, 2, 4 and 6
|-
| colspan=34 style="border-style: none;" | <br>
|
{| class="wikitable mw-collapsible autocollapse"
|+ style="text-align: left; font-size:95%" | {{nowrap|Program Mask}}
! Bit
! Meaning
Memory (''storage'') in System/360 is addressed in terms of [[8-bit]] bytes. Various instructions operate on larger units called ''halfword'' (2 bytes), ''fullword'' (4 bytes), ''doubleword'' (8 bytes), ''quad word'' (16 bytes) and 2048 byte storage block, specifying the leftmost (lowest address) of the unit. Within a halfword, fullword, doubleword or quadword, low numbered bytes are more significant than high numbered bytes; this is sometimes referred to as [[big-endian]]. Many uses for these units require aligning them on the corresponding boundaries. Within this article the unqualified term ''word'' refers to a ''fullword''.
The original architecture of System/360 provided for up to 2<sup>24</sup> = 16,777,216 bytes of memory. The later [[IBM System/360 Model 67|Model 67]] extended the architecture to allow up to 2<sup>32</sup> = 4,294,967,296<ref group=NB>{{efn|Twice the size of the later System/370</ref>}} bytes of virtual memory.
==Addressing==
| publisher = Sperry Rand Corporation
}}
</ref> That means that instructions do not contain complete addresses, but rather specify a base register and a positive offset from the addresses in the base registers. In the case of System/360 the base address is contained in one of 15<ref group=NB>{{efn|A specification of general register 0 yield a base address of zero rather than the register content.</ref>}} general registers. In some instructions, for example shifts, the same computations are performed for 32-bit quantities that are not addresses.
==Data formats==
| align=center valign=top | 0-7
| valign=top style="align:left;" | {{anchor|System_Mask}}System Mask
| valign=top | bits 0-5: enable channels 0-5, bit 6: enable all remaining channels,{{#tag:refefn|On a processor that complies with the S/360 architecture, the highest channel number is 6. Eleven bits are sufficient to identify the cuu, and seven bits are sufficient to provide masking of I/O interruptions. However, on a 360/67-2 with two 2846 channel controllers, channels are numbered 0-6 and 8-14;<ref name=GA27-2719/>{{rp|page=15}} similarly, the 360/195 had an extended channel feature<ref name=A22-6943/>{{rp|page=21}} but numbered the channels 0 through 13.<ref name=A22-6943/>{{rp|page=25}} I/O interruptions for Channel Controller 1 on the 360/67-2 were masked using control registers, and the 360/195 used bit 7 (Channel 6) of the System Mask as a summary mask bit for channels 6 and up. ''Interruptions from More than Seven Channels''<sup>[[#PoOps|PoOps]]</sup>{{rpsfn|pagePoOps|p=121.4}} describes the summary masking for additional channels, but other text in Principles of Operation still refers to a limit of 7 channels. Standard software supported channels 0-F.|group=NB|name=ChanNum}} bit 7: enable External interruptions (timer, interrupt key, and external signal)<sup class=reference>[[#Pops{{sfn|PoOps]]</sup>{{rp|page=71}}
|-
| align=center valign=top | 8-11
| align=center valign=top | 12{{anchor|AMWP}}
| valign=top | ASCII mode
| enable ASCII mode for packed decimal instructions, never used by IBM software<ref group=NB>{{efn|Because the design of the S/360 occurred simultaneously with the development of ASCII, IBM's ASCII support did not match the standard that was ultimately adopted.</ref>}}
|-
| align=center valign=top | 13
| align=center valign=top | 16-31
| valign=top | {{anchor|Interruption_Code}}Interruption Code
| code to indicate the type of interruption, inserted when the PSW is stored, during IPLoad, this is the address of the device from which the program was loaded<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=77}}
|-
| align=center valign=top | 32-33
| align=center valign=top | 36-39
| valign=top | {{anchor|Program_Mask}}Program Mask
| bit 36: enable fixed-point overflow, bit 37: decimal overflow, bit 38: exponent underflow, bit 39: significance<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=71}}
|-
| align=center valign=top|40-63
==Interruption system==
The architecture<ref name=A22-6821-7/>{{rp|pages=77–83}} defines 5 classes of [[interrupt]]ion. An interruption is a mechanism for automatically changing the program state; it is used for both synchronous<ref group=NB>{{efn|The S/360 literature does not use the terms fault or [[Trap (computing)|trap]]</ref>}} and [[asynchrony (computing)|asynchronous]] events.
{| class="wikitable" collapsiblestyle="text-align: right;"
|-
! rowspan="2" | Interruption class !! colspan="2" | Old PSW !! colspan="2" | New PSW
! rowspan="2" | Priority
|-
! Interruption classhex !! Olddec PSW<br!! />hex dec !! New PSW<br />hex dec
! align=right valign=top | Priority
|-
| [[#Input/Output interruption|Input/Output]]<sup class=reference>[[#PoOps|PoOps]]</sup>{{rpsfn|pagesPoOps|pp=78–7978-79}} || 38 || 56 || 78 120 || align=right120 || 4
|-
| [[#Program interruption|Program]]<sup class=reference>[[#PoOps|PoOps]]</sup>{{rpsfn|pagesPoOps|pp=79–80.1}} || 28 || 40 || 68 104 || align=right104 || 2
|-
| [[#Supervisor Call interruption|Supervisor Call]]<sup class=reference>[[#PoOps|PoOps]]</sup>{{rpsfn|pagesPoOps|pp=80.1–81}} || 20 || 32 || 60 96 || align=right96 || 2
|-
| [[#External interruption|External]]<sup class=reference>[[#PoOps|PoOps]]</sup>{{rpsfn|pagesPoOps|pp=81–82}} || 18 || 24 || 58 88 || align=right88 || 3
|-
| [[#Machine Check interruption|Machine Check]]<sup class=reference>[[#PoOps|PoOps]]</sup>{{rpsfn|pagesPoOps|pp=82–83}} || 30 || 48 || 70 112 || align=right112 || 1
|}
===Input/Output interruption===
An I/O interruption<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=78–79}} occurs at the completion of a channel program, after fetching a CCW with the PCI bit set and also for [[asynchrony (computing)|asynchronous]] events detected by the device, control unit or channel, e.g., completion of a mechanical movement. The system stores the device address into the interruption code and stores channel status into the [[#Channel Status Word|CSW]] at ___location 64 ('40'X).
===Program interruption===
A Program interruption<ref name=A22-6821-7/>{{rp|pages=16,79–80.1}} occurs when an instruction encounters one{{#tag:refefn|On the 360/91,<ref name=A22-6907/>{{rp|page=15}} 360/95 and 360/195<ref name=A22-6943/>{{rp|page=14}} a Program interruption may occur for multiple imprecise exceptions. The ILC in the Program Old PSW is 0, bits 26-31 are 0 and bits 16-27 are a mask indicating which exceptions occurred; there is no provision for reporting multiple occurrences of the same exception. Reporting of multiple imprecise exceptions is not part of the S/360 architecture.|group=NB|name=multimpr}} of 15{{#tag:refefn|There are 17 possible exceptions on the 360/67,<ref name=GA27-2719/>{{rp|page=17}} but page exception and segment exception are not part of the S/360 architecture; similarly, interruption code 18 ('0012'X) on a 360/65 multiprocessor is not part of the S/360 architecture.|group=NB|name=NotArchExc}} exceptions; however, if the [[#Program Mask|Program Mask]] bit corresponding to an exception is 0 then there is no interruption for that exception.
On 360/65,<ref name=A22-6884/>{{rp|page=12}} 360/67<ref name=GA27-2719/>{{rp|page=46}} and 360/85<ref name=A22-6916/>{{rp|page=12}} the Protection Exception and Addressing Exception interruptions can be imprecise, in which case they store an Instruction Length Code of 0.
The Interruption code may be any of
| align=right valign=top | 0
|
Imprecise interruption<ref group=NB {{efn|name=multimpr/>}} on 360/91,<ref name=A22-6907/>{{rp|page=15}} 360/95 or 360/195<ref name=A22-6943/>{{rp|page=14}}
{| class="wikitable collapsible collapsed"
|+ {{nowrap|Old PSW bits for multiple imprecise interruption codes}}
|-
| 18
| Specification<ref group=NB>{{efn|The Specification bit is not used for imprecise interruptions on the 360/195</ref>}}
|-
| 19
|-
| 26
| Decimal Overflow<ref group=NB {{efn|name=NoDec>|Not Used on 360/91</ref>}}
|-
| 27
| Decimal Divide<ref group=NB {{efn|name=NoDec/>}}
|}
|-
| align=right | 1
| align=right | 1
| [[#Operation exception|Operation]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=79}}
|-
| align=right | 2
| align=right | 2
| [[#Privileged operation exception|Privileged operation]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=79}}
|-
| align=right | 3
| align=right | 3
| [[#Execute exception|Execute]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=79}}
|-
| align=right | 4
| align=right | 4
| [[#Protection exception|Protection]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=79}}
|-
| align=right | 5
| align=right | 5
| [[#Addressing exception|Addressing]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=79–80}}
|-
| align=right | 6
| align=right | 6
| [[#Specification exception|Specification]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=80}}
|-
| align=right | 7
| align=right | 7
| [[#Data exception|Data]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=80}}
|-
| align=right | 8
| align=right | 8
| [[#Fixed-point overflow exception|Fixed-point overflow]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=80}}
|-
| align=right | 9
| align=right | 9
| [[#Fixed-point divide exception|Fixed-point divide]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=80}}
|-
| align=right | A
| align=right | 10
| [[#Decimal overflow exception|Decimal overflow]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=80}}
|-
| align=right | B
| align=right | 11
| [[#Decimal divide exception|Decimal divide]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=80}}
|-
| align=right | C
| align=right | 12
| [[#Exponent overflow exception|Exponent overflow]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=80}}
|-
| align=right | D
| align=right | 13
| [[#Exponent underflow exception|Exponent underflow]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=80}}
|-
| align=right | E
| align=right | 14
| [[#Significance exception|Significance]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=80}}
|-
| align=right | F
| align=right | 15
| [[#Floating-point divide exception|Floating-point divide]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=80.1}}
|-
| align=right | 10
| align=right | 16
|
Segment Translation<ref name=GA27-2719/>{{rp|page=17}}<ref group=NB {{efn|name=NotArchExc/>}}
|-
| align=right | 11
| align=right | 17
|
Page Translation<ref name=GA27-2719/>{{rp|page=17}}<ref group=NB {{efn|name=NotArchExc/>}}
|-
| align=right | 12
| align=right | 18
|
SSM Exception<ref name=A22-6884/><ref group=NB {{efn|name=NotArchExc/>}}
|}
* An '''operation exception'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=79}} is recognized when a program attempts to execute an instruction with an opcode that the computer does not implement. In particular, an operation exception is recognized when a program is written for an optional feature, e.g., floating point, that is not installed.
* A '''privileged operation exception'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=79}} is recognized when a program attempts to execute a privileged instruction when the problem state bit in the PSW is 1.
* An '''execute exception'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=79}} is recognized when the operand of an [[Execute instruction|EXECUTE instruction (EX)]] is another EXECUTE instruction.
* A '''protection exception'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=79}} is recognized when a program attempts to store into a ___location whose storage protect key does not match<ref group=NB>{{efn|A PSW key of 0 matches any storage key.</ref>}} the PSW key, or to fetch from a fetch protected ___location whose storage protect key does not match the PSW key.
* An '''addressing exception'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=79–80}} is recognized when a program attempts to access a storage ___location that is not currently available. This normally occurs with an address beyond the capacity of the machine, but it may also occur on machines that allow blocks of storage to be taken offline.
*A '''specification exception'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=80}} is recognized when an instruction has a length or register field with values not permitted by the operation, or when it has an operand address that does not satisfy the alignment requirements of the opcode, e.g., a LH instruction with an odd operand address on a machine without the byte alignment feature.
* A '''data exception'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=80}} is recognized when a decimal instruction specifies invalid operands, e.g., invalid data, invalid overlap.
* A '''fixed-point overflow exception'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=80}} is recognized when significant bits are lost in a fixed point arithmetic or shift instruction, other than divide.
* A '''fixed-point divide exception'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=80}} is recognized when significant bits are lost in a fixed point divide or Convert to Binary instruction.
* A '''decimal overflow exception'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=80}} is recognized when significant digits are lost in a decimal arithmetic instruction, other than divide.
* A '''decimal divide exception'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=80}} is recognized when significant bits are lost in a decimal divide instruction. The destination is not altered.
* An '''exponent overflow exception'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=80}} is recognized when the characteristic in a floating-point arithmetic operation exceeds 127 and the fraction is not zero.
* An '''exponent underflow exception'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=80}} is recognized when the characteristic in a floating-point arithmetic operation is negative and the fraction is not zero.
* A '''significance exception'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=80}} is recognized when the fraction in a floating-point add or subtract operation is zero.
* A '''floating-point divide exception'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=80.1}} is recognized when the fraction in the divisor of a floating-point divide operation is zero.
===Supervisor Call interruption===
A Supervisor Call interruption<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=80.1–81}} occurs as the result of a [[Supervisor Call instruction]]; the system stores bits 8-15 of the SVC instruction as the Interruption Code.
===External interruption===
An External<sup class=reference>[[#PoOps|PoOps]]</sup>{{rpsfn|pagePoOps|p=81}}<ref group=NB>{{efn|Even though a timer expiration is an internal event, it causes an External interruption and for this reason, this interruption is usually referred to as a timer/external interruption.</ref>}} interruption occurs as the result of certain asynchronous events. Bits 16-24 of the External Old PSW are set to 0 and one or more of bits 24-31 is set to 1
{| class="wikitable collapsible"
===Machine Check interruption===
A Machine Check interruption<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=82–83}} occurs to report unusual conditions associated with the channel or CPU that cannot be reported by another class of interruption. The most important class of conditions causing a Machine Check is a hardware error such as a parity error found in registers or storage, but some models may use it to report less serious conditions. Both the interruption code and the data stored in the scanout area at '80'x (128 decimal) are model dependent.
==Input/Output==
* {{anchor|IBM_Byte_Mux}}A '''byte multiplexer channel''' is capable of executing multiple '''CCW'''s concurrently; it is normally used to attach slow devices such as card readers and telecommunications lines. A byte multiplexer channel could have a number of selector subchannels, each with only a single subchannel, which behave like low-speed selector channels.
* {{anchor|IBM_Sel}}A '''selector channel''' has only a single subchannel, and hence is only capable of executing one channel command at a time. It is normally used to attach fast devices that are not capable of exploiting a block multiplexer channel to suspend the connection, such as magnetic tape drives.
* {{anchor|IBM_Blk_Mux}}A '''block multiplexer channel''' is capable of concurrently running multiple channel programs, but only one at a time can be active. The control unit can request suspension at the end of a channel command and can later request resumption. This is intended for devices in which there is a mechanical delay after completion of data transfer, e.g., for seeks on moving-head DASD. The block multiplexer channel was a late addition to the System/360 architecture; early machines had only byte multiplexer channels and selector channels. The block multiplexer channel wasis an optional feature only on the models 85 and 195. The block multiplexor channel wasis also available on the later [[IBM System/370|System/370]] computers.
Conceptually peripheral equipment is attached to a S/360 through ''control units'', which in turn are attached through channels. However, the architecture does not require that control units be physically distinct, and in practice they are sometimes integrated with the devices that they control. Similarly, the architecture does not require the channels to be physically distinct from the processor, and the smaller S/360 models (through 360/50) have integrated channels that [[Cycle stealing|steal cycles]] from the processor.
Peripheral devices are addressed with 16-bit<ref group=NB>{{efn|Because of the limits on the channel number, S/360 and early S/370 software only used 12 bits to store device addresses.</ref>}} addresses.,<ref name=A22-6821-7/>{{rp|page=89}} referred to as ''cua'' or ''cuu''; this article will use the term ''cuu''. The high 8 bits identify a channel, numbered from 0 to 6,<ref group=NB {{efn|name=ChanNum/>}} while the low 8 bits identify a device on that channel. A device may have multiple ''cuu'' addresses.
Control units are assigned an address "capture" range. For example, a CU might be assigned range 20-2F or 40-7F. The purpose of this is to assist with the connection and prioritization of multiple control units to a channel. For example, a channel might have three disk control units at 20-2F, 50-5F, and 80-8F. Not all of the captured addresses need to have an assigned physical device. Each control unit is also marked as High or Low priority on the channel.
Device selection progresses from the channel to each control unit in the order they are physically attached to their channel. At the end of the chain the selection process continues in reverse back towards the channel. If the selection returns to the channel then no control unit accepted the command and SIO returns Condition Code 3. Control units marked as High Priority check the outbound CUU to be within their range. If so, then the I/O wasis processed. If not, then the selection wasis passed to the next outbound CU. Control units marked as Low Priority check for inbound (returning) CUU to be within their range. If so, then the I/O is processed. If not, then the selection is passed to the next inbound CU (or the channel). The connection of three controls unit to a channel might be physically -A-B-C and, if all are marked as High then the priority would be ABC. If all are marked low then the priority would be CBA. If B was marked High and AC low then the order would be BCA. Extending this line of reasoning then the first of N controllers would be priority 1 (High) or 2N-1 (Low), the second priority 2 or 2N-2, the third priority 3 or 2N-3, etc. The last physically attached would always be priority N.
There are three storage fields reserved for I/O; a double word I/O old PSW, a doubleword I/O new PSW and a fullword ''Channel Address Word'' ('''CAW'''). Performing an I/O normally requires the following:
* initializing the '''CAW''' with the storage key and the address of the first CCW
* issuing a ''Start I/O'' ('''SIO''') instruction that specifies the ''cuu'' for the operation
* waiting<ref group=NB>{{efn|But continuing with unrelated work.</ref>}} for an I/O interruption
* handling any unusual conditions indicated in the ''Channel Status Word'' ('''CSW''')
===Channel status===
These conditions are detected by the channel and indicated in the [[#Channel Status Word|CSW]].<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=116–118}}
* {{Anchor|Program-controlled_interruption status|PCI status}}'''[[#CSW_Program-controlled_interruption status|Program-controlled interruption]]'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=116–117}} indicates that the channel has fetched a CCW with the PCI bit set. The channel continues processing; this interruption simply informs the CPU of the channel's progress. An example of the use of Program-controlled interruption is in the "Program Fetch" function of Contents Supervision, whereby the control program is notified that a Control/Relocation Record has been read. To ensure that this record has been completely read into main storage, a "disabled bit spin", one of the few which remains in the control program, is initiated. Satisfaction of the spin indicates that the Control/Relocation Record is completely in main storage and the immediately preceding Text Record may be relocated. After relocation, a NOP CCW is changed to a TIC and the channel program continues. In this way, an entire load module may be read and relocated while utilizing only one [[EXCP]], and possibly only one revolution of the disk drive. PCI also has applications in teleprocessing access method buffer management.
* {{Anchor|Incorrect length|IL}}'''[[#CSW_Incorrect_length|Incorrect length]]'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=117}} indicates that the data transfer for a command completed before the Count was exhausted. This indication is suppressed if the [[#CCW-SuppressLengthIndication|Suppress-Length-Indication]] bit in the CCW is set.
* '''[[#CSW_Program_check|Program check]]'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=117}} indicates one of the following errors
** Nonzero bits where zeros are required
** An invalid data or CCW address
** The CAW or a TIC refers to a TIC
* {{Anchor|Protection check}}'''[[#CSW_Protection_check|Protection check]]'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=117–118}} indicates that the protection key in the CAW is non-zero and does not match the storage protection key.
* {{Anchor|Channel data check|CDC}}'''[[#CSW_Channel_data_check|Channel data check]]'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=118}} indicates a parity error during a data transfer.
* {{Anchor|Channel control check|CCC}}'''[[#CSW_Channel_control_check|Channel control check]]'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=118}} indicates a channel malfunction other than [[#Channel data check|Channel data check]] or [[#Interface control check|Interface control check]].
* {{Anchor|Interface control check|ICC}}'''[[#CSW_Interface_control_check|Interface control check]]'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=118}} indicates an invalid signal in the channel to control unit interface.
* {{Anchor|Chaining check}}'''[[#CSW_Chaining_check|Chaining check]]'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=118}} indicates lost data during data chaining.
===Unit status===
These conditions are presented to the channel by the control unit or device.<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=113–116}} In some cases they are handled by the channel and in other cases they are indicated in the [[#Channel Status Word|CSW]]. There is no distinction between conditions detected by the control unit and conditions detected by the device.
* {{Anchor|Attention}}'''[[#CSW_Attention|Attention]]'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=113}} indicates an unusual condition not associated with an ongoing channel program. It often indicates some sort of operator action like requesting input, in which case the CPU would respond by issuing a read-type command, most often a sense command (04h) from which additional information could be deduced. Attention is a special condition, and requires specific operating system support, and for which the operating system has a special attention table<ref group=NB>{{efn|The OS uses the attention index in a [[Unit Control Block]] (UCB) as an index into the attention table.</ref>}} with a necessarily limited number of entries.
* {{Anchor|Status modifier|SM}}'''[[#CSW_Status_modifier|Status modifier]]'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=113–114}} (SM) indicates one of three unusual conditions
** A Test I/O instruction was issued to a device that does not support it.
** A [[#Busy|Busy]] status refers to the control unit rather than to the device.
:: where the TIC causes the channel to refetch the search until the device indicates a successful search by raising SM.
* {{Anchor|Control unit end}}'''[[#CSW_Control_unit_end|Control unit end]]'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=114}} indicates that a previous control unit busy status has been cleared.
* {{Anchor|Busy}}'''[[#CSW_Busy|Busy]]'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=114–115}} indicates that a device ([[#Status modifier|SM]]=0) or a control unit ([[#Status modifier|SM]]=1) is busy.
* {{Anchor|Channel end|CE}}'''[[#CSW_Channel_end|Channel end]]'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=115}} indicates that the device has completed the data transfer for a channel command. There may also be an [[#Incorrect length|Incorrect length]] indication if the Count field of the CCW is exhausted, depending on the value of the [[#CCW-SuppressLengthIndication|Suppress-Length-Indication]] bit.
* {{Anchor|Device end|DE}}'''[[#CSW_Device_end|Device end]]'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=115}} indicates that the device has completed an operation and is ready to accept another. DE may be signalled concurrently with [[#Channel en|CE]] or may be delayed.
* {{Anchor|Unit check|UC}}'''[[#CSW_Unit_check|Unit check]]'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=115–116}} indicates that the device or control unit has detected an unusual conditionscondition and that details may be obtained by issuing a Sense command.
* {{Anchor|Unit exception|UE}}'''[[#CSW_Unit_exception|Unit exception]]'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=116}} indicates that the device has detected an unusual condition, e.g., end of file.
===Channel Address Word===
===Channel Command Word===
A ''Channel Command Word'' is a doubleword containing the following:
* an 8-bit channel [[#CCW Command codes|Command Code]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=100}}
* a 24-bit address<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=100–101}}
* a 5-bit flag field<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=99–100,101–105}}
* an unsigned halfword Count field<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=100–101}}
====CCW Command codes====
|-
| style="font-family:monospace" | MMMM 0100
| Sense<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=106–107}}
|-
| style="font-family:monospace" | **** 1000
| Transfer in Channel (TIC)<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=107–108}}
|-
| style="font-family:monospace" | MMMM 1100
| Read Backward<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=105–106}}
|-
| style="font-family:monospace" | MMMM MM01
| Write<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=105}}
|-
| style="font-family:monospace" | MMMM MM10
| Read<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=105}}
|-
| style="font-family:monospace" | MMMM MM11
| Control<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=106–107}}
|}
| valign=top | {{anchor|CCW-CD}}CD
| valign=top | {{anchor|CCW-ChainData}}Chain-Data
| Continue operation using the storage area defined by the next CCW.<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=101–103}}
|-
|-
| valign=top | {{anchor|CCW-CC}}CC
| valign=top | {{anchor|CCW-ChainCommand}}Chain-Command
| Continue with the Command in the next CCW.<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=101,103}}
|-
| align=right valign=top | 34
| valign=top | {{anchor|CCW-SLI}}SLI<ref group=NB>{{efn|Also known as Suppress Incorrect Length Indication (SILI)</ref>}}
| valign=top | {{anchor|CCW-SuppressLengthindication}}Suppress-Length-Indication
| Continue channel program after count mis-match.<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=99–100}}
|-
| align=right valign=top | 35
| valign=top | {{anchor|CCW-SKIP}}SKIP
| valign=top | Skip
| Do not read from or write into storage.| Do not read from or write into storage.<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=103–104}}
|-
| align=right valign=top | 36
| valign=top | {{anchor|CCW-PCI}}PCI
| valign=top | {{anchor|CCW-ProgramControlledInterupt}}Program-Controlled-Interruption
| Request interruption when fetching CCW.<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=104–105}}
|}
|-
| align=right | 0-3
| Key<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=119}}
|-
| align=right | 4-7
|-
| align=right | 8-31
| Command Address<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=119}}
|-
| align=right | 32-47
| Status<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=113–118}}
|-
| align=right valign=top | 32-39
| valign=top |
: Unit Status Conditions<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=113–116}}
: Detected by the device or control unit
|-
| align=right | {{anchor|CSW_Attention}}32
|
: [[#Attention|Attention]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=113}}
|-
| align=right | {{anchor|CSW_Status_modifier}}33
|
: [[#Status modifier|Status modifier]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=113–114}}
|-
| align=right | {{anchor|CSW_Control_unit_end}}34
|
: [[#Control unit end|Control unit end]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=114}}
|-
| align=right | {{anchor|CSW_Busy}}35
|
: [[#Busy|Busy]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=114–115}}
|-
| align=right | {{anchor|CSW_Channel_end}}36
|
: [[#Channel end|Channel end]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=115}}
|-
| align=right | {{anchor|CSW_Device_end}}37
|
: [[#Device end|Device end]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=115}}
|-
| align=right | {{anchor|CSW_Unit_check}}38
|
: [[#Unit check|Unit check]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=115–116}}
|-
| align=right | {{anchor|CSW_Unit_exception}}39
|
: [[#Unit exception|Unit exception]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=116}}
|-
| align=right valign=top | 40-47
| valign=top |
: Channel Status Conditions<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=116–118}}
: Detected by the channel.
|-
| align=right | {{anchor|CSW_Program-controlled_interruption_status}}40
|
: [[#Program-controlled interruption status|Program-controlled interruption]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=116–117}}
|-
| align=right | {{anchor|CSW_Incorrect_length}}41
|
: [[#Incorrect length|Incorrect length]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=117}}
|-
| align=right | {{anchor|CSW_Program_check}}42
|
: [[#Program check|Program check]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=117}}
|-
| align=right | {{anchor|CSW_Protection_check}}43
|
: [[#Protection check|Protection check]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=117–118}}
|-
| align=right | {{anchor|CSW_Channel_data_check}}44
|
: [[#Channel data check|Channel data check]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=118}}
|-
| align=right | {{anchor|CSW_Channel_control_check}}45
|
: [[#Channel control check|Channel control check]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=118}}
|-
| align=right | {{anchor|CSW_Interface_control_check}}46
|
: [[#Interface control check|Interface control check]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=118}}
|-
| align=right | {{anchor|CSW_Chaining_check}}47
|
: [[#Chaining check|Chaining check]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=118}}
|-
| align=right | 48-63
| Count<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=120}}
|}
* The '''Protection Key''' field contains the protect key from the CAW at the time that the I/O operation was initiated for I/O complete or PCI interruptions.<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=119}}
* The '''Command Address''' field contains the address+8 of the last CCW fetched for an I/O complete or PCI interruption. However, there are 9 exceptions<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>.{{rp|pagep=119}}
* The '''Status''' field contains one byte of [[#Channel status|Channel status]] bits, indicating conditions detected by the channel<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>,{{rp|pagespp=116–118}} and one byte of [[#Unit status|Unit status]] bits, indicating conditions detected by the I/O unit<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>.{{rp|pagespp=113–116}} There is no distinction between conditions detected by the control unit and conditions detected by the device.
* The '''Residual Count''' is a half word that gives the number of bytes in the area described by the CCW that have not been transferred to or from the channel<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>.{{rp|pagep=120}} The difference between the count in the CCW and the residual count gives the number of bytes transferred.
===I/O instructions===
* '''System Reset''' sends a reset signal on every I/O channel and clears the processor state; all pending interruptions are cancelled. System Reset is not guaranteed to correct parity errors in general registers, floating point registers or storage. System Reset does not reset the state of shared I/O devices.
* '''{{anchor|Initial_Program_Load}}Initial Program Load''' (IPL)<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=123}} is a process for loading a program when there isn't a loader available in storage, usually because the machine was just powered on or to load an alternative operating system.<ref name=A22-6821-7/>{{rp|page=123}} This process is sometimes known as [[Booting]].
:: As part of the IPL facility the operator has a means of specifying a 12-bit<ref group=NB {{efn|name=ChanNum/>}} device address, typically with three dials as shown in the operator controls drawing. When the operator<ref group=NB>{{efn|Or an equivalent automated facility.</ref>}} selects the ''Load'' function, the system performs a ''System Reset'', sends a Read IPL<ref group=NB>{{efn|Read with all modifier bits zero</ref>}} channel command to the selected device in order to read 24 bytes into locations 0-23 and causes the channel to begin fetching ''CCW''s at ___location 8; the effect is as if the channel had fetched a CCW from ___location 0 with a length of 24, andan address of 0 and the flags containing Command Chaining + Suppress Length Indication. At the completion of the operation, the system stores the I/O address in the halfword at ___location 2 and loads the PSW from ___location 0.
:: Initial program loading is typically done from a tape, a card reader, or a disk drive. Generally, the operating system was loaded from a disk drive; IPL from tape or cards was used only for diagnostics or for installing an operating system on a new computer.
* '''Emergency pull switch'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=124}} (Emergency power off, EPO) sends an EPO signal to every I/O channel, then turns off power to the processor complex. Because EPO bypasses the normal sequencing of power down, damage can result, and the EPO control has a mechanical latch to ensure that a customer engineer inspects the equipment before attempting to power it back on.
* '''Power on'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=124}} powers up all components of the processor complex and performs a system reset.
* '''Power off'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=124}} initiates an orderly power-off sequence. Although the contents of storage are preserved, the associated storage keys may be lost.
* The '''Interrupt''' key<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=124}} causes an [[#External interruption|external interruption]] with bit 25 set in the External Old PSW.
* The '''Wait light'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=124}} indicates that the [[#Program Status Word (PSW)|PSW]] has bit 14 (wait) set; the processor is temporarily halted but resumes operation when an interruption condition occurs.
* The '''Manual light'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=124}} indicates that the CPU is in a stopped state.
* The '''System light'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=124}} indicates that a meter is running, either due to CPU activity or due to I/O channel activity.
* The '''Test light'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=124}} indicates that certain operator controls are active, when certain facilities, e.g., INSTRUCTION STEP, have been used by a Diagnose instruction or when abnormal thermal conditions exist. The details are model dependent.
* The '''Load light'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=124}} is turned on by IPL and external start. It is turned off by loading the PSW from ___location 0 at the completion of the load process.
* The '''Load unit'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=124–125}} controls provide the rightmost 11<ref group=NB>{{efn|There is an inconsistency, in that ''Interruptions from More than Seven Channels''<sup class=reference>[[#PoOps|PoOps]]</sup>{{rpsfn|pagePoOps|p=121.4}} allows for more channels.</ref>}} bits of the device from which to perform an IPL.
* The '''Load Key'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=125}} starts the [[#Initial Program Load|IPL]] sequence.
* The '''Prefix Select Key Switch'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=125}} selects whether [[#Initial Program Load|IPL]] will use the primary prefix or the alternative prefix.
* The '''System-Reset Key'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=125}} initiates a [[#System Reset|System Reset]].
* The '''Stop Key'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=125}} puts the CPU in a stopped state; channel programs continue running and interruption conditions remain pending.
* The '''Rate Switch'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=125}} determines the mode in which the processor fetches instructions. Two modes are defined by the architecture:
** PROCESS
** INSTRUCTION STEP
* The '''Start Key'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=125}} initiates instruction fetching in accordance with the setting of the [[#Rate Switch|Rate Switch]].
* The '''Storage-Select Switch'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=126}} determines the type of resource accessed by the [[#Store Key|Store Key]] and [[#Display Key|Display Key]]. Three selections are defined by the architecture:
** Main storage
** General registers
** Floating-point registers
* The '''Address Switches'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=126}} specify the address or register number for the [[#Store Key|Store Key]], [[#Display Key|Display Key]] and, on some models, the [[#Set IC Key|Set IC Key]]..
* The '''Data Switches'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=126}} specify the data for the [[#Store Key|Store Key]] and, on some models, the [[#Set IC Key|Set IC Key]].
* The '''Store Key'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=126}} stores the value in the [[#Data Switches|Data Switches]] as specified by the [[#|Storage-Select Switch]] and the [[#Address Switches|Address Switches]].
* The '''Display Key'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=126}} displays the value specified by the [[#|Storage-Select Switch]] and the [[#Address Switches|Address Switches]].
* The '''Set IC='''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=126}} sets the instruction address portion of the PSW from the [[#Data Switches|Data Switches]] or the [[#Address Switches|Address Switches]], depending on the model.
* The '''Address-Compare Switches'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=126}} select the mode of comparison and what is compared. Stop on instruction address compare is present on all models, but stop on data address compare is only present on some models.
* The '''Alternate-Prefix Light'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=126}} is on when the prefix trigger is in the alternate state.
==Optional features==
===Direct Control===
The ''Direct Control''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=17.1}} feature provides six external signal lines and an 8-bit data path to/from storage.<ref name=A22-6845/>
===Floating-point arithmetic===
===Multi-system operation===
''Multi-system operation''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=17.1–18}} is a set of features to support multi-processor systems, e.g., [[#Direct Control|Direct Control]], direct address relocation (prefixing).
===Storage protection===
==Notes==
{{notelist}}
{{Reflist|group=NB|35em}}
==References==
| title = IBM System/360 Principles of Operation
| id = A22-6821-7
| ref = {{sfnref|PoOps}}
| date = September 1968
| version = Eighth Edition
| 