Cycles per instruction: Difference between revisions

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{{Short description|Aspect of CPU performance}}

{{Refimprove|date=December 2009}}

In [[computer architecture]], '''cycles per instruction''' (aka '''clock cycles per instruction''', '''clocks per instruction''', or '''CPI''') is one aspect of a [[central processing unit|processor's]]'s performance: the average number of [[clock cycle]]s per [[Instruction (computer science)|instruction]] for a program or program fragment.<ref>{{cite book |title=Computer Organization and Design: The Hardware/Software Interface|firsturl=https://archive.org/details/computerorganiza00henn|url-access=registration|first1=David A.|last1=Patterson|first2=John L.|last2=Hennessy|year=1994|publisher=Morgan Kaufmann |isbn=9781558602816}}</ref> It is the [[multiplicative inverse]] of [[instructions per cycle]].

== Definition ==

The average of Cycles Per Instruction in a given process ({{math|CPI}}) is defined by the following [[Weighted arithmetic mean|weighted average]]:

: <math>

\mathrm{CPI} := \frac{\Sigma_i(\mathrm{IC}_i)(\mathrm{CC}_i)}{\mathrm{IC}} = \frac{\Sigma_i(\mathrm{IC}_i \cdot \mathrm{CC}_i)}{\Sigma_i(\mathrm{IC}_i)}

CPI = \frac{\Sigma_i(IC_i)(CC_i)}{IC}

</math>

Where <math>IC_i\mathrm{IC}_i</math> is the number of instructions for a given instruction type <math>i</math>, <math>CC_i\mathrm{CC}_i</math> is the clock-cycles for that instruction type and <math>\mathrm{IC}=\Sigma_i(IC_i\mathrm{IC}_i)</math> is the total instruction count. The summation sums over all instruction types for a given benchmarking process.

==Explanation==

Let us assume a [[classic RISC pipeline]], with the following 5five stages:

# Instruction fetch cycle (IF).

# Instruction decode/Register fetch cycle (ID).

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# Write-back cycle (WB).

Each stage requires one clock cycle and an instruction passes through the stages sequentially. Without [[instruction pipelining|pipelining]], in a [[multi-cycle processor]], a new instruction is fetched in stage 1 only after the previous instruction finishes at stage 5, therefore the number of clock cycles it takes to execute an instruction is 5five (CPI = 5 > 1). In this case, the processor is said to be ''subscalar''. With pipelining, a new instruction is fetched every clock cycle by exploiting [[instruction-level parallelism]], therefore, since one could theoretically have 5five instructions in the 5five pipeline stages at once (one instruction per stage), a different instruction would complete stage 5 in every clock cycle and on average the number of clock cycles it takes to execute an instruction is 1 (CPI = 1). In this case, the processor is said to be ''scalar''.

With a single-[[Execution unit|execution-unit]] processor, the best CPI attainable is 1. However, with a multiple-execution-unit processor, one may achieve even better CPI values (CPI < 1). In this case, the processor is said to be ''[[superscalar]]''. To get better CPI values without pipelining, the number of execution units must be greater than the number of stages. For example, with 6six executions units, 6six new instructions are fetched in stage 1 only after the 6six previous instructions finish at stage 5, therefore on average the number of clock cycles it takes to execute an instruction is 5/6 (CPI = 5/6 < 1). To get better CPI values with pipelining, there must be at least 2two execution units. For example, with 2two executions units, 2two new instructions are fetched every clock cycle by exploiting instruction-level parallelism, therefore 2two different instructions would complete stage 5 in every clock cycle and on average the number of clock cycles it takes to execute an instruction is 1/2 (CPI = 1/2 < 1).

==Examples==

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===Example 1===

For the multi-cycle [[MIPS architecture|MIPS]], there are 5five types of instructions:

* Load (5 cycles)

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* 50% load instructions

* 15% R-type instructions

* 25% store instructions

* 15% R-type instructions

* 8% branch instructions

* 2% jump instructions

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<math>

\text{CPI} = \frac{5 \times 50 + 4 \times 1525 + 4 \times 2515 + 3 \times 8 + 3 \times 2}{100} = 4.4

</math>

===Example 2===

<ref>Advanced Computer Architecture by Kai Hwang, Chapter 1, Exercise Problem 1.1</ref> A 400-[[MHz]] processor was used to execute a [[benchmark program]] with the following [[instruction mix]] and [[clock cycle]] count:

{| class="wikitable"

|-

! Instruction typeTYPE

! Instruction count

! Clock cycle count

|-

| Integer arithmeticArithmetic

| 45000

| 1

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|}

Determine the effective CPI, [[Instructions per second#Million instructions per second|MIPS]] (Millions of instructions per second) rate, and execution time for this program.

<math>

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</math>

<math>400 Mhz\,\text{MHz} = 400 ,000 ,000 \,\text{Hz}</math>

since: <math>\text{MIPS} \propto 1/\text{CPI}</math> and <math>\text{MIPS} \propto \text{clock Frequencyfrequency}</math>

<math>

\text{Effective processor performance} = \text{MIPS} = \frac{\text{clock frequency}}{\text{CPI}} \times {\frac{1}{\text{1 Million}}} </math><math>= \frac{400,000,000 }{1.55 \times 1000000}= \frac{400}{1.55} = 258 \, \text{MIPS}

</math>

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<math>

\text{Execution time}(T) = \text{CPI} \times \text{Instruction count} \times \text{clock time} = \frac{\text{CPI} \times \text{Instruction Count}}{\text{frequency}} </math><math>= \frac{1.55 \times 100000}{400 \times 1000000} = \frac{1.55}{4000} = 0.0003875 \, \text{sec} = 0.3875 \, \text{ms}

</math>

==See also==

* [[Million instructionsCycle per second]] ([[Hertz|MIPSHz]])

* [[Instructions per cycle]] (IPC)

* [[Instructions per second]] (IPS)

* [[Cycle per second]] ([[Hertz|Hz]])

* [[Megahertz myth]]

* [[Million instructions per second|MIPS]]

* The [[Benchmark (computing)|benchmark]] article provides a useful introduction to computer performance measurement for those readers interested in the topic.

==References==

{{Reflist}}

{{CPU technologies}}

{{DEFAULTSORT:Cycles Per Instruction}}

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[[Category:Clock signal]]

[[Category:Rates]]

[[Category:Computer performance]]