Successive-approximation ADC: Difference between revisions

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{{Short description|Type of analog-to-digital converter}}

{{No footnotes|date=March 2020}}

[[File:SA ADC block diagram.png|thumb|300px320x320px|Successive-approximation ADC block diagram showing digital-to-analog converter (DAC), end of conversion indicator (EOC), successive-approximation register (SAR), sample and hold circuit (S/H), input voltage ({{math|''V''_in}}) and reference voltage ({{math|''V''_ref}})]]

A '''successive-approximation ADC''' (or '''SAR ADC''') is a type of [[analog-to-digital converter]] (ADC) that [[Digitization|digitizes]] each [[Sampling (signal processing)|sample]] from a continuous [[analog waveform]] using a [[binary search]] through all possible [[Quantization (signal processing)|quantization]] levels.

== History ==

The SAR ADC was first used for experimental [[pulse-code modulation]] (PCM) by [[Bell Labs]] in the 1940s. In 1954, [[Bernard Marshall Gordon|Bernard Gordon]] introduced the first commercial [[vacuum tube]] SAR ADC, converting 50,000 11-bit [[samples per second]].<ref>{{Cite web |last=Kester |first=Walt |date=June 2005 |title=Which ADC Architecture Is Right for Your Application? |url=https://www.analog.com/en/resources/analog-dialogue/articles/the-right-adc-architecture.html |url-status=live |archive-url=https://web.archive.org/web/20250109032609/https://www.analog.com/en/resources/analog-dialogue/articles/the-right-adc-architecture.html |archive-date=2025-01-09 |access-date=2025-05-30 |website=[[Analog Dialogue]]}}</ref>

== Algorithm ==

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# An analog [[voltage comparator]] that compares {{math|''V''_in}} to the output of a [[digital-to-analog converter]] (DAC).

# A successive-approximation [[Processor register|register]] that is updated by results of the comparator to provide the DAC with a digital code whose accuracy increases each successive iteration.

# A DAC that supplies the [[comparator]] with an analog voltage relative to the reference voltage {{math|1=''V''_ref}} (which corresponds to the full-scale range of the ADC) and proportional to the digital code of the SAR.

[[File:4-bit Successive Approximation DAC.gif|thumb|right|Animation of a 4-bit successive-approximation ADC with {{math|1=''V''_ref = 5 [[volt|V]]}}|320x320px]]

The successive-approximation register is initialized with 1 in the [[most significant bit]] (MSB) and zeroes in the lower bits. The register's code is fed into the DAC, which provides an analog equivalent of its digital code (initially {{math|1={{sfrac|1|2}}''V''_ref}}) to the comparator for comparison with the sampled input voltage. If this analog voltage exceeds {{math|''V''_in}}, then the comparator causes the SAR to reset this bit; otherwise, the bit is left as 1. Then the next bit is set to 1 and the same test is done, continuing this [[Binary search algorithm|binary search]] until every bit in the SAR has been tested. The resulting code is the digital approximated output of the sampled input voltage.

The algorithm's objective for the {{math|''n''^th}} iteration is to approximately digitize the input voltage to an accuracy of {{frac|1|2^''n''}} relative to the reference voltage. To show this mathematically, the normalized input voltage is represented as {{math|''x''}} in {{math|[−1,&nbsp;1]}} by letting {{math|1=''V''_in = ''xV''_ref}}. The algorithm starts with an initial approximation of {{math|1=''x''₀ = 0}} and during each iteration {{math|''i''}} produces the following approximation:<blockquote>{{math|''i''^th}} approximation: {{math|1=''x''_''i'' = ''x''_''i''−1 − {{sfrac|''ssgn''(''x''_''i''−1 − ''x'')|2^''i''}}}}</blockquote>where the binary [[signum function]] {{math|''ssgn''(}} mathematically represents the comparison of the previous iteration's approximation {{math|1=''x'')_i-1}} iswith athe [[signumnormalized function]]input voltage {{math|''x''}}:<math display="block"> ssgn(x_{i-1} - x) := \begin{cases}

+1 & \text{if } xx_{i-1} \geq 0x, \\

-1 & \text{if } xx_{i-1} < 0x. \end{cases}</math>It follows using mathematical induction that the approximation of the {{math|''n''^th}} iteration theoretically has a bounded accuracy of: {{math|{{!}}''x''_''n'' − ''x''{{!}} ≤ {{sfrac|1|2^''n''}}}}.[[File:ADC animation 20.gif|thumb|alt=Successive approximation animation|Operation of successive-approximation ADC as input voltage falls from 5 to 0&nbsp;V. Iterations on the ''x'' axis. Approximation value on the ''y'' axis.|right]]

=== UseInaccuracies within non-ideal analog circuits ===

When implemented as a real analog circuit, circuit inaccuracies and [[Noise (electronics)|noise]] may cause the binary search algorithm to incorrectly remove values it believes {{math|''V''_in}} cannot be, so a successive-approximation ADC might not output the closest value. It is very important for the DAC to accurately produce all {{math|2^''n''}} analog values for comparison against the unknown {{math|''V''_in}} in order to produce a best match estimate. The maximal error can easily exceed several LSBs, especially as the error between the actual and ideal {{math|2^''n''}} becomes large. Manufacturers may characterize the accuracy using an [[effective number of bits]] (ENOB) smaller than the actual number of output bits.

{{As of|2001}}, the component-matching limitations of the DAC generally limited the linearity to about 12&nbsp;bits in practical designs and mandated some form of trimming or calibration to achieve the necessary linearity for more than 12&nbsp;bits.<ref>{{Cite web |date=2001-10-02 |title=Understanding SAR ADCs: Their Architecture and Comparison with Other ADCs |url=https://www.analog.com/en/resources/technical-articles/successive-approximation-registers-sar-and-flash-adcs.html |url-status=live |archive-url=https://web.archive.org/web/20241118075147/https://www.analog.com/en/resources/technical-articles/successive-approximation-registers-sar-and-flash-adcs.html |archive-date=2024-11-18 |access-date=2025-01-03 |website=[[Analog Devices]]}}</ref> And since [[Johnson–Nyquist noise#Thermal noise on capacitors|kT/C noise]] is inversely proportional to capacitance, low noise demands a large input capacitance (which costs chip area and requires a more powerful drive buffer), which has motivated proposals around noise cancellation.<ref>{{Cite journal |last=Keerthy Kumar |first=Shashank |date=2023 |title=Design of a 13-Bit SAR ADC with kT/C noise cancellation technique |url=http://lup.lub.lu.se/student-papers/record/9142088 |journal=Master's Thesis published in [[Lund University]] Student Papers}}</ref> For comparison, for a {{math|1=''V''_ref}} of 5&nbsp;V, the least significant bit of a 16-bit converter corresponds to 76&nbsp;μV, which is around the 64&nbsp;μ[[Root mean square voltage|Vrms]] noise of a 1&nbsp;[[Picofarad|pF]] (large for on-chip) capacitor at [[room temperature]]. {{As of|2012}}, SAR ADCs are limited to 18&nbsp;bits, while [[delta-sigma]] ADCs (which can be 24&nbsp;bits) are better suited if more than 16&nbsp;bits are needed.<ref>{{Cite web |date=2012-05-07 |title=Understanding Noise, ENOB, and Effective Resolution in Analog-to-Digital Converters |url=https://www.analog.com/en/resources/technical-articles/noise-enob-and-effective-resoluition-in-analog-to-digital-converter-circuits--maxim-integrated.html |url-status=live |archive-url=https://web.archive.org/web/20240422221715/https://www.analog.com/en/resources/technical-articles/noise-enob-and-effective-resoluition-in-analog-to-digital-converter-circuits--maxim-integrated.html |archive-date=2024-04-22 |access-date=2024-12-28 |website=[[Analog Devices]]}}</ref> SAR ADCs are commonly found on [[microcontrollers]] because they are easy to integrate into a [[mixed-signal]] process, but suffer from inaccuracies from the internal reference voltage [[resistor ladder]] and [[Clock signal|clock]] and [[signal noise]] from the rest of the microcontroller, so external ADC chips may provide better accuracy.<ref>{{Cite web |last=Giovino |first=Bill |date=2018-11-21 |title=IoT Microcontrollers Have ADCs, but Know When to Choose and Apply an External ADC |url=https://www.digikey.com/en/articles/iot-microcontrollers-have-adcs-know-when-apply-an-external-adc |url-status=live |archive-url=https://web.archive.org/web/20240624010637/https://www.digikey.com/en/articles/iot-microcontrollers-have-adcs-know-when-apply-an-external-adc |archive-date=2024-06-24 |access-date=2025-01-03 |website=[[DigiKey]]}}</ref>

[[File:ADC animation 20.gif|thumb|alt=Successive approximation animation|Operation of successive-approximation ADC as input voltage falls from 5 to 0&nbsp;V. Iterations on the ''x'' axis, starting with the initial state at notch 1. Voltages on the ''y'' axis.|right]]

===Examples===

'''Example 1:''' The ten steps to converting an analog input to 10 9-bit digital, using successive-approximation, are shown here for all voltages from 5&nbsp;V to 0&nbsp;V in 0.1&nbsp;V iterations. Since the reference voltage is 5&nbsp;V, when the input voltage is also 5&nbsp;V, all bits are set. As the voltage is decreased to 4.9&nbsp;V, only some of the least significant bits are cleared. The MSB will remain set until the input is one half the reference voltage, 2.5&nbsp;V.

The binary weights assigned to each bit, starting with the MSB, are 2.5, 1.25, 0.625, 0.3125, 0.15625, 0.078125, 0.0390625, 0.01953125, 0.009765625, 0.0048828125. All of these add up to 4.9951171875990234375, meaning binary 1111111111111111111, or one LSB less than 5.

When the analog input is being compared to the internal DAC output, it effectively is being compared to each of these binary weights, starting with the 2.5&nbsp;V and either keeping it or clearing it as a result. Then by adding the next weight to the previous result, comparing again, and repeating until all the bits and their weights have been compared to the input, the result, a binary number representing the analog input, is found.

'''Example 2:''' The working of a 4-bit successive-approximation ADC is illustrated below. The MSB is initially set to 1, whereas the remaining digits are set to zero. If the input voltage is lower than the value stored in the register, on the next clock cycle, the register changes its value to that illustrated in the figure by following the green line. If the input voltage is higher, then on the next clock cycle, the register changes its value to that illustrated in the figure by following the red line. The simplified structure of this type of ADC that acts on {{math|1=2^''n''}} volts range can be expressed as an algorithm:

# Initialize register with MSB set to 1 and all other values set to zero.

# In the n-{{Sup|th}} clock cycle, if voltage is higher than digital equivalent voltage of the number in register, the (n+1)-{{Sup|th}} digit from the left is set to 1. If the voltage were lower than digital equivalent voltage, then n-{{Sup|th}} digit from left is set to zero and the next digit is set to 1. To perform a conversion, an N-bit ADC requires N such clock cycles excluding the initial state.

{{Multiple image|

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===Variants===

* ''Counter type ADC'': The D to A converter can be easily turned around to provide the inverse function A to D conversion. The principle is to adjust the DAC's input code until the DAC's output comes within {{math|±{{frac|1|2}}}} LSB to the analog input, which is to be converted to binary digital form.

* ''Servo tracking ADC'': It is an improved version of a counting ADC. The circuit consists of an up-down counter with the comparator controlling the direction of the count. The analog output of the DAC is compared with the analog input. If the input is greater than the DAC output signal, the output of the comparator goes high and the counter is caused to count up. The tracking ADC has the advantage of being simple. The disadvantage, however, is the time needed to stabilize as a new conversion value is directly proportional to the rate at which the analog signal changes.

==Charge-redistribution successive-approximation ADC==

[[File:ChargeScalingDAC.png|right|thumb|300px320x320px|Charge-scalingSwitched capacitor array acting as the DAC for an {{math|''N''}}-bit charge-redistribution SAR ADC, fed into a ground-referenced comparator.]]

One of the most common SAR ADC implementations uses a charge-scaling [[Digital-to-analog converter|DAC]] consisting of an array of individually-switched [[capacitors]] sized in [[powers of two]] and an additional duplicate of the smallest capacitor, for a total of {{math|''N''+1}} capacitors for {{math|''N''}} bits. Thus if the largest capacitance is {{math|''C''}}, then the array's total capacitance is {{math|2''C''}}. The switched capacitor array acts as both the sample-and-hold element and the DAC. Redistributing their [[Electric charge|charge]] will adjust their net voltage, which is fed into the negative input of a comparator (whose positive input is always grounded) to perform the binary search using the following steps:<ref>{{Cite web |last=Kugelstadt |first=Thomas |date=2000 |title=The operation of the SAR-ADC based on charge redistribution |url=https://www.ti.com.cn/cn/lit/an/slyt176/slyt176.pdf |url-status=live |archive-url=https://web.archive.org/web/20241227083825/https://www.ti.com.cn/cn/lit/an/slyt176/slyt176.pdf |archive-date=2024-12-27 |access-date=2024-12-28 |website=[[Texas Instruments]]}}</ref><ref>{{Cite web |date=2020 |title=Operation of a SAR-ADC Based on Charge Redistribution |url=https://www.renesas.com/en/document/apn/r14an0001-operation-sar-adc-based-charge-redistribution-rev100 |url-status=live |archive-url=https://web.archive.org/web/20241015132842/https://www.renesas.com/en/document/apn/r14an0001-operation-sar-adc-based-charge-redistribution-rev100 |archive-date=2024-10-15 |access-date=2024-12-28 |website=[[Renesas Electronics]]}}</ref>

One of the most common implementations of the successive-approximation ADC, the ''charge-redistribution'' successive-approximation ADC, uses a charge-scaling [[Digital-to-analog converter|DAC]]. The charge-scaling DAC simply consists of an array of individually switched binary-weighted capacitors. The amount of charge upon each capacitor in the array is used to perform the aforementioned binary search in conjunction with a comparator internal to the DAC and the successive-approximation register.

[[File:CAPadc.png|thumb|3 bits simulation of a capacitive ADC]]

# The capacitor array is completely discharged to the offset voltage of the comparator, {{math|''V''_OS}}. This step provides automatic offset cancellation (i.e. the offset voltage represents nothing but dead charge, which can't be juggled by the capacitors).

# All of the capacitors within the array are switched to the input signal {{math|''V''_in}}. The capacitors now have a charge equal to their respective capacitance times the input voltage minus the offset voltage upon each of them.

# The capacitors are then switched so that this charge is applied across the comparator input, creating a comparator input voltage equal to {{math|−''V''_in}}.

# The actual conversion process proceeds. First, the MSB capacitor is switched to {{math|''V''_ref}}, which corresponds to the full-scale range of the ADC. Due to the binary-weighting of the array, the MSB capacitor forms a 1:1 charge divider with the rest of the array. Thus, the input voltage to the comparator is now {{math|−''V''_in + {{frac|''V''_ref|2}} }}. Subsequently, if {{math|''V''_in}} is greater than {{frac|''V''_ref|2}}, then the comparator outputs a digital 1 as the MSB, otherwise it outputs a digital 0 as the MSB. Each capacitor is tested in the same manner until the comparator input voltage converges to the offset voltage, or at least as close as possible given the resolution of the DAC.

[[File:CAPadc.png|thumb|3 bit capacitive ADC, using {{math|1=''V''_ref = 5V}}. The bottom left transient simulation uses {{math|''V''_in ≅ 3.5V}} or about {{math|.7}} of {{math|''V''_ref}}, resulting in an answer of {{math|{{frac|5|8}}}} (101 in binary), representing {{math|3.125V}} or {{math|0.625}} of {{math|''V''_ref}}. "PESE" is the voltage on the array, and its remaining final voltage is the conversion's residual error.|320x320px]]

=== Use with non-ideal analog circuits ===

# Discharge: The capacitors are discharged. (Note, discharging to comparator's offset voltage will automatically provide offset cancellation.)

When implemented as an analog circuit – where the value of each successive bit is not perfectly {{math|2^''N''}} (e.g. 1.1, 2.12, 4.05, 8.01, etc.) – a successive-approximation approach might not output the ideal value because the binary search algorithm incorrectly removes what it believes to be half of the values the unknown input cannot be. Depending on the difference between actual and ideal performance, the maximal error can easily exceed several LSBs, especially as the error between the actual and ideal {{math|2^''N''}} becomes large for one or more bits. Since the actual input is unknown, it is therefore very important that accuracy of the analog circuit used to implement a SAR ADC be very close to the ideal {{math|2^''N''}} values; otherwise, it cannot guarantee a best match search.

# AllSampling: of theThe capacitors within the array are switched to the input signal {{math|''V''_in}}. TheAfter a brief sampling period, the capacitors nowwill havehold a charge equal to their respective capacitance times the{{math|''V''_in}} input voltage(and minus the offset voltage upon each of them), so the array holds a total charge of {{math|2''C''·''V''_in}}.

# Hold: The capacitors are then switched soto thatground. thisThis charge is applied acrossprovides the comparator's negative input, creatingwith a comparator input voltage equal toof {{math|−''V''_in}}.

# Conversion: the actual conversion process proceeds with the following steps in each iteration, starting with the largest capacitor as the test capacitor for the MSB, and then testing each next smaller capacitor in order for each bit of lower significance:

## Redistribution: The current test capacitor is switched to {{math|''V''_ref}}. The test capacitor forms a charge divider with the remainder of the array whose ratio depends on the capacitor's relative size. In the first iteration, the ratio is {{math|1:1}}, so the comparator's negative input becomes {{math|−''V''_in + {{frac|''V''_ref|2}}}}. On the {{math|''i''^th}} iteration, the ratio will be {{math|1:2^''i''−1}}, so the {{math|''i''^th}} iteration of this redistribution step effectively adds {{math|{{frac|''V''_ref|2^''i''}}}} to the voltage.

## Comparison: The comparator's output determines the bit's value for to the current test capacitor. In the first iteration, if {{math|''V''_in}} is greater than {{frac|''V''_ref|2}}, then the comparator will output a digital 1 and otherwise output a digital 0.

## Update Switch: A digital 0 result will leave the current test capacitor connected to {{math|''V''_ref}} for subsequent iterations, while a digital 1 result will switch the capacitor back to ground. Thus, each {{math|''i''^th}} iteration may or may not add {{math|{{frac|''V''_ref|2^''i''}}}} to the comparator's negative input voltage. For instance, the voltage at the end of the first iteration will be {{math|−''V''_in + MSB·{{frac|''V''_ref|2}}}}.

# End Of Conversion: After all capacitors are tested in the same manner, the comparator's negative input voltage will have converged as close as possible (given the resolution of the DAC) to the comparator's offset voltage.

== See also ==

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{{DEFAULTSORT:Successive Approximation Adc}}

[[Category:Electronic circuits]]

[[Category:Digital signal processing]]

[[Category:Analog circuits]]