Content deleted Content added
Em3rgent0rdr (talk | contribs) →Examples: pretty sure Example 1 animation is just 9-bit, not 10-bit, conversion. Going from x-axis label 1 to x-axis notch 2 is determining the MSB. See talk. |
m convert special characters found by Wikipedia:Typo Team/moss (via WP:JWB) |
||
| (12 intermediate revisions by 5 users not shown) | |||
Line 3:
[[File:SA ADC block diagram.png|thumb|320x320px|Successive-approximation ADC block diagram showing digital-to-analog converter (DAC), end of conversion indicator (EOC), successive-approximation register (SAR), sample and hold circuit (S/H), input voltage ({{math|''V''<sub>in</sub>}}) and reference voltage ({{math|''V''<sub>ref</sub>}})]]
A '''successive-approximation ADC''' (or '''SAR ADC''') is a type of [[analog-to-digital converter]] (ADC) that [[Digitization|digitizes]] each [[Sampling (signal processing)|sample]] from a continuous [[analog waveform]] using a [[binary search]] through all possible [[Quantization (signal processing)|quantization]] levels.
== History ==
The SAR ADC was first used for experimental [[pulse-code modulation]] (PCM) by [[Bell Labs]] in the 1940s. In 1954, [[Bernard Marshall Gordon|Bernard Gordon]] introduced the first commercial [[vacuum tube]] SAR ADC, converting 50,000 11-bit [[samples per second]].<ref>{{Cite web |last=Kester |first=Walt |date=June 2005 |title=Which ADC Architecture Is Right for Your Application? |url=https://www.analog.com/en/resources/analog-dialogue/articles/the-right-adc-architecture.html |url-status=live |archive-url=https://web.archive.org/web/20250109032609/https://www.analog.com/en/resources/analog-dialogue/articles/the-right-adc-architecture.html |archive-date=2025-01-09 |access-date=2025-05-30 |website=[[Analog Dialogue]]}}</ref>
== Algorithm ==
Line 12 ⟶ 15:
# A DAC that supplies the [[comparator]] with an analog voltage relative to the reference voltage {{math|1=''V''<sub>ref</sub>}} (which corresponds to the full-scale range of the ADC) and proportional to the digital code of the SAR.
[[File:4-bit Successive Approximation DAC.gif|thumb|right|Animation of a 4-bit successive-approximation ADC with {{math|1=''V''<sub>ref</sub> = 5 [[volt|V]]}}|320x320px]]
The successive-approximation register is initialized with 1 in the [[most significant bit]] (MSB) and zeroes in the lower bits. The register's code is fed into the DAC, which provides an analog equivalent of its digital code (initially {{math|1={{sfrac|1|2}}''V''<sub>ref</sub>}}) to the comparator for comparison with the sampled input voltage. If this analog voltage exceeds {{math|''V''<sub>in</sub>}}, then the comparator causes the SAR to reset this bit; otherwise, the bit is left as 1. Then the next bit is set to 1 and the same test is done, continuing this [[
The algorithm's objective for the {{math|''n''<sup>th</sup>}} iteration is to approximately digitize the input voltage to an accuracy of {{frac|1|2<sup>''n''</sup>}} relative to the reference voltage. To show this mathematically, the normalized input voltage is represented as {{math|''x''}} in {{math|[−1, 1]}} by letting {{math|1=''V''<sub>in</sub> = ''xV''<sub>ref</sub>}}. The algorithm starts with an initial approximation of {{math|1=''x''<sub>0</sub> = 0}} and during each iteration {{math|''i''}} produces the following approximation:<blockquote>{{math|''i''<sup>th</sup>}} approximation: {{math|1=''x''<sub>''i''</sub> = ''x''<sub>''i''−1</sub> − {{sfrac|''sgn''(''x''<sub>''i''−1</sub> − ''x'')|2<sup>''i''</sup>}}}}</blockquote>where the binary [[signum function]] {{math|''sgn''}} mathematically represents the comparison of the previous iteration's approximation {{math|1=''x''<sub>i-1</sub>}} with the normalized input voltage {{math|''x''}}:<math display="block"> sgn(x_{i-1} - x) = \begin{cases}
Line 22 ⟶ 25:
When implemented as a real analog circuit, circuit inaccuracies and [[Noise (electronics)|noise]] may cause the binary search algorithm to incorrectly remove values it believes {{math|''V''<sub>in</sub>}} cannot be, so a successive-approximation ADC might not output the closest value. It is very important for the DAC to accurately produce all {{math|2<sup>''n''</sup>}} analog values for comparison against the unknown {{math|''V''<sub>in</sub>}} in order to produce a best match estimate. The maximal error can easily exceed several LSBs, especially as the error between the actual and ideal {{math|2<sup>''n''</sup>}} becomes large. Manufacturers may characterize the accuracy using an [[effective number of bits]] (ENOB) smaller than the actual number of output bits.
{{As of|2001}}, the component-matching limitations of the DAC generally limited the linearity to about 12 bits in practical designs and mandated some form of trimming or calibration to achieve the necessary linearity for more than 12 bits.<ref>{{Cite web |date=2001-10-02 |title=Understanding SAR ADCs: Their Architecture and Comparison with Other ADCs |url=https://www.analog.com/en/resources/technical-articles/successive-approximation-registers-sar-and-flash-adcs.html |url-status=live |archive-url=https://web.archive.org/web/20241118075147/https://www.analog.com/en/resources/technical-articles/successive-approximation-registers-sar-and-flash-adcs.html |archive-date=2024-11-18 |access-date=2025-01-03 |website=[[Analog Devices]]}}</ref> And since [[Johnson–Nyquist noise#Thermal noise on capacitors|kT/C noise]] is inversely proportional to capacitance, low noise demands a large input capacitance (which costs chip area and requires a more powerful drive buffer), which has motivated proposals around noise cancellation.<ref>{{Cite journal |last=Keerthy Kumar |first=Shashank |date=2023 |title=Design of a 13-Bit SAR ADC with kT/C noise cancellation technique |url=http://lup.lub.lu.se/student-papers/record/9142088 |journal=Master's Thesis published in [[Lund University]] Student Papers}}</ref> For comparison, for a {{math|1=''V''<sub>ref</sub>}} of 5 V, the least significant bit of a 16-bit converter corresponds to 76 μV, which is around the 64 μ[[Root mean square voltage|Vrms]] noise of a 1 [[Picofarad|pF]] (large for on-chip) capacitor at [[room temperature]]. {{As of|2012}}, SAR ADCs are limited to 18 bits, while [[
[[File:ADC animation 20.gif|thumb|alt=Successive approximation animation|Operation of successive-approximation ADC as input voltage falls from 5 to 0 V. Iterations on the ''x'' axis
===Examples===
'''Example 1:''' The steps to converting an analog input to 9-bit digital, using successive-approximation, are shown here for all voltages from 5 V to 0 V in 0.1 V iterations. Since the reference voltage is 5 V, when the input voltage is also 5 V, all bits are set. As the voltage is decreased to 4.9 V, only some of the least significant bits are cleared. The MSB will remain set until the input is one half the reference voltage, 2.5 V.
The binary weights assigned to each bit, starting with the MSB, are 2.5, 1.25, 0.625, 0.3125, 0.15625, 0.078125, 0.0390625, 0.01953125, 0.009765625
When the analog input is being compared to the internal DAC output, it effectively is being compared to each of these binary weights, starting with the 2.5 V and either keeping it or clearing it as a result. Then by adding the next weight to the previous result, comparing again, and repeating until all the bits and their weights have been compared to the input, the result, a binary number representing the analog input, is found.
'''Example 2:''' The working of a 4-bit successive-approximation ADC is illustrated below. The MSB is initially set to 1, whereas the remaining digits are set to zero. If the input voltage is lower than the value stored in the register, on the next clock cycle, the register changes its value to that illustrated in the figure by following the green line. If the input voltage is higher, then on the next clock cycle, the register changes its value to that illustrated in the figure by following the red line. The simplified structure of this type of ADC that acts on {{math|1=2<sup>''n''</sup>}} volts range can be expressed as an algorithm:
# Initialize register with MSB set to 1 and all other values set to zero.
Line 64 ⟶ 67:
===Variants===
* ''Counter type ADC'': The D to A converter can be easily turned around to provide the inverse function A to D conversion. The principle is to adjust the DAC's input code until the DAC's output comes within {{math|±{{frac|1|2}}}} LSB to the analog input, which is to be converted to binary digital form.
* ''Servo tracking ADC'': It is an improved version of a counting ADC. The circuit consists of an up-down counter with the comparator controlling the direction of the count. The analog output of the DAC is compared with the analog input. If the input is greater than the DAC output signal, the output of the comparator goes high and the counter is caused to count up. The tracking ADC has the advantage of being simple. The disadvantage, however, is the time needed to stabilize as a new conversion value is directly proportional to the rate at which the analog signal changes.
==Charge-redistribution successive-approximation ADC==
[[File:ChargeScalingDAC.png|right|thumb|320x320px|Switched capacitor array acting as the DAC for an {{math|''N''}}-bit charge-redistribution SAR ADC, fed into a ground-referenced comparator.]]
One of the most common SAR ADC implementations uses a charge-scaling [[Digital-to-analog converter|DAC]] consisting of an array of individually-switched [[capacitors]] sized in [[powers of two]] and an additional duplicate of the smallest capacitor, for a total of {{math|''N''+1}} capacitors for {{math|''N''}} bits. Thus if the largest capacitance is {{math|''C''}}, then the array's total capacitance is {{math|2''C''}}. The switched capacitor array acts as both the sample-and-hold element and the DAC. Redistributing their [[Electric charge|charge]] will adjust their net voltage, which is
[[File:CAPadc.png|thumb|3 bit capacitive ADC, using {{math|1=''V''<sub>ref</sub> = 5V}}. The bottom left transient simulation uses {{math|''V''<sub>in</sub> ≅ 3.5V}} or about {{math|.7}} of {{math|''V''<sub>ref</sub>}}, resulting in an answer of {{math|{{frac|5|8}}}} (101 in binary), representing {{math|3.125V}} or {{math|0.625}} of {{math|''V''<sub>ref</sub>}}. "PESE" is the voltage on the array, and its remaining final voltage is the conversion's residual error.|320x320px]]
Line 97 ⟶ 100:
{{DEFAULTSORT:Successive Approximation Adc}}
[[Category:Digital signal processing]]
[[Category:Analog circuits]]
| |||