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When implemented as a real analog circuit, circuit inaccuracies and [[Noise (electronics)|noise]] may cause the binary search algorithm to incorrectly remove values it believes {{math|''V''<sub>in</sub>}} cannot be, so a successive-approximation ADC might not output the closest value. It is very important for the DAC to accurately produce all {{math|2<sup>''n''</sup>}} analog values for comparison against the unknown {{math|''V''<sub>in</sub>}} in order to produce a best match estimate. The maximal error can easily exceed several LSBs, especially as the error between the actual and ideal {{math|2<sup>''n''</sup>}} becomes large. Manufacturers may characterize the accuracy using an [[effective number of bits]] (ENOB) smaller than the actual number of output bits.
{{As of|2001}}, the component-matching limitations of the DAC generally limited the linearity to about 12 bits in practical designs and mandated some form of trimming or calibration to achieve the necessary linearity for more than 12 bits.<ref>{{Cite web |date=2001-10-02 |title=Understanding SAR ADCs: Their Architecture and Comparison with Other ADCs |url=https://www.analog.com/en/resources/technical-articles/successive-approximation-registers-sar-and-flash-adcs.html |url-status=live |archive-url=https://web.archive.org/web/20241118075147/https://www.analog.com/en/resources/technical-articles/successive-approximation-registers-sar-and-flash-adcs.html |archive-date=2024-11-18 |access-date=2025-01-03 |website=[[Analog Devices]]}}</ref> And since [[Johnson–Nyquist noise#Thermal noise on capacitors|kT/C noise]] is inversely proportional to capacitance, low noise demands a large input capacitance (which costs chip area and requires a more powerful drive buffer), which has motivated proposals around noise cancellation.<ref>{{Cite journal |last=Keerthy Kumar |first=Shashank |date=2023 |title=Design of a 13-Bit SAR ADC with kT/C noise cancellation technique |url=http://lup.lub.lu.se/student-papers/record/9142088 |journal=Master's Thesis published in [[Lund University]] Student Papers}}</ref> For comparison, for a {{math|1=''V''<sub>ref</sub>}} of 5 V, the least significant bit of a 16-bit converter corresponds to 76
[[File:ADC animation 20.gif|thumb|alt=Successive approximation animation|Operation of successive-approximation ADC as input voltage falls from 5 to 0 V. Iterations on the ''x'' axis, starting with the initial state at notch 1. Voltages on the ''y'' axis.|right]]
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