Random test generator: Difference between revisions

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{{Use mdy dates|date=January 2019}}

{{Use American English|date=January 2019}}

{{UnreferencedMore sources needed|date=January 2019}}

'''Random test generators''' (often abbreviated RTG or ISG<ref name=":0">{{Citation |title=Introduction to FORCE-RISCV |date=2023-02-21 |url=https://github.com/openhwgroup/force-riscv |publisher=OpenHW Group |access-date=2023-02-25}}</ref> for Instruction Stream Generator or Instruction Sequence Generator<ref name=":0" />) are a type of [[computer software]] that is used in [[functional verification]] of [[microprocessor]]s. Their primary use lies in providing input stimulus to a [[device under test]].

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==Dynamic Generators==

Dynamic generators incorporate significant knowledge about the architecture being tested. They enhance the ability of less-skilled users to generate complex tests that can hit hard-to-reach corner cases without stumbling on subtle programming pitfalls. This added knowledge, flexibility and ease-of-use is reflected in a more complex generator, and consequently the cost of creating and maintaining the generator are greater than for table-based or static generators.

==References==

{{Reflist}}

==External links==

* [http://www.haifa.ibm.com/dept/svt/papers/simulation/meth_date99.pdf IBM Genesys Pro] {{Webarchive|url=https://web.archive.org/web/20060316083416/http://www.haifa.ibm.com/dept/svt/papers/simulation/meth_date99.pdf |date=March 16, 2006 }}

* [http://www.obsidiansoft.com Obsidian Software RAVEN]

* [http://forge.ispras.ru/projects/microtesk MicroTESK], an [[open-source]] ISG developed by the [[Russian Academy of Sciences]]