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{{Use dmy dates|date=August 2018}}
'''Intel 5-level paging''', referred to simply as ''5-level paging'' in [[Intel]] documents, is a processor extension for the [[x86-64]] line of processors.<ref name="intel-white-paper">{{Cite web|url=https://www.intel.com/content/www/us/en/content-details/671442/5-level-paging-and-5-level-ept-white-paper.html|title=5-Level Paging and 5-Level EPT|publisher=Intel Corporation|date=May 2017}}</ref>{{Rp|11}} It extends the size of [[virtual address]]es from 48 bits to 57 bits by adding an additional level to x86-64's [[Page table#Multilevel page tables|multilevel page tables]], increasing the addressable [[virtual memory]] from 256 [[tebibyte|TiB]] to 128 [[pebibyte|PiB]]. The extension was first implemented in the [[Ice Lake (microprocessor)|Ice Lake]] processors.<ref name="anandtech-13699">{{Cite web|url=https://www.anandtech.com/show/13699/intel-architecture-day-2018-core-future-hybrid-x86/2|archive-url=https://web.archive.org/web/20190502215444/https://www.anandtech.com/show/13699/intel-architecture-day-2018-core-future-hybrid-x86/2|url-status=dead|archive-date=2 May 2019|title=Sunny Cove Microarchitecture: A Peek At the Back End|work=Intel's Architecture Day 2018: The Future of Core, Intel GPUs, 10nm, and Hybrid x86|last=Cutress|first=Ian|access-date=2019-10-15}}</ref>
== Technology ==
[[File:X86 Paging 64bit.svg|thumb|right|555px|4-level paging of the 64-bit mode]]
In the 4-level paging scheme (previously known as [[IA-32e]] paging), the 64-bit virtual memory address is divided into five parts. The lowest 12 bits contain the offset within the 4 KiB memory page, and the following 36 bits are evenly divided between the four 9 bit descriptors, each linking to a 64-bit [[X86-64#Page table structure|page table entry]] in a 512-entry page table for each of the four paging levels. This makes it possible to use bits 0 through 47 in the virtual address, for a total of 256 TiB.<ref name="x86-software-developers-manual" />{{Rp|page=4{{hyp}}2}}
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