Intel Core (microarchitecture): Difference between revisions

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The '''Intel Core microarchitecture''' (provisionally referred to as '''Next Generation Micro-architecture''',<ref>{{cite web |last1=Bessonov |first1=Oleg |title=New Wine into Old Skins. Conroe: Grandson of Pentium III, Nephew of NetBurst? |url=http://ixbtlabs.com/articles2/cpu/p6-nexgen.html |website=ixbtlabs.com |date=9 September 2005}} Note that all mentions of "Next-Generation Micro-architecture" in Intel's slides have asterisks that warn that "micro-architecture name [[To be determined|TBD]]".</ref> and developed as '''Merom''')<ref name="hinton">{{cite web |last1=Hinton |first1=Glenn |title=Key Nehalem Choices |url=https://web.stanford.edu/class/ee380/Abstracts/100217-slides.pdf |date=17 February 2010}}</ref> is a multi-core [[central processing unit|processor]] [[microarchitecture]] launched by [[Intel]] in mid-2006. It is a major evolution over the [[Yonah (microprocessor)|Yonah]], the previous iteration of the [[P6 (microarchitecture)|P6 microarchitecture series]] which started in 1995 with [[Pentium Pro]]. It also replaced the [[NetBurst]] microarchitecture, which suffered from high power consumption and heat intensity due to an inefficient [[Pipeline (computing)|pipeline]] designed for high [[clock rate]]. In early 2004, the new version of NetBurst (Prescott) needed very high power to reach the clocks it needed for competitive performance, making it unsuitable for the shift to [[Multi-core processor|dual/multi-core]] CPUs. On May 7, 2004, Intel confirmed the cancellation of the next NetBurst, [[Tejas and Jayhawk]].<ref>{{cite web |title=Intel cancels Tejas, moves to dual-core designs |url=https://www.eetimes.com/intel-cancels-tejas-moves-to-dual-core-designs/ |website=[[EE Times]] |date=7 May 2004}}</ref> Intel had been developing Merom, the 64-bit evolution of the [[Pentium M]], since 2001,<ref name="hinton"/> and decided to expand it to all market segments, replacing NetBurst in desktop computers and servers. It inherited from Pentium M the choice of a short and efficient pipeline, delivering superior performance despite not reaching the high clocks of NetBurst.{{Efn|NetBurst had reached 3.8 GHz in 2004. Core initially reached 3 GHz, and after moving to 45nm in [[Penryn (microarchitecture)|Penryn]] would reach 3.5 GHz. [[Westmere (microarchitecture)|Westmere]], the ultimate evolution of P6, reached 3.6 GHz base and 3.86 GHz boost frequency. (Excluding the 4.4 GHz special-order Xeons.)}}

The first processors that used this architecture were code-named '[[Merom (microprocessor)|Merom]]', '[[Conroe (microprocessor)|Conroe]]', and '[[Woodcrest (microprocessor)|Woodcrest]]'; Merom is for mobile computing, Conroe is for desktop systems, and Woodcrest is for servers and workstations. While architecturally identical, the three processor lines differ in the socket used, bus speed, and power consumption. The first Core-based desktop and mobile processors were branded ''[[Intel Core 2|Core 2]]'', later expanding to the lower-end ''[[Pentium Dual-Core]]'', ''[[Pentium]]'' and ''[[Celeron]]'' brands; while server and workstation Core-based processors were branded ''[[Xeon]]''.

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==Technology==

[[Image:Intel Core2 arch.svg|right|thumb|upright=2|Intel Core microarchitecture]]

While the Core microarchitecture is a major architectural revision, it is based in part on the [[Pentium M]] processor family designed by Intel Israel.<ref>{{cite web |url=http://seattletimes.nwsource.com/html/businesstechnology/2003658346_intelisrael09.html |title=How Israel saved Intel |last=King |first=Ian |publisher=The Seattle Times |date=April 9, 2007 |access-date=April 15, 2012}}</ref> The [[Pipeline (computing)|pipeline]] of Core/[[Penryn (microarchitecture)|Penryn]] is 14 stages long<ref>{{cite web |title=Driving energy-efficient performance, innovation with Intel Core microarchitecture |url=https://www.intel.com/pressroom/kits/events/idfspr_2006/BackgrounderIDF.pdf |publisher=Intel |date=7 March 2006}}</ref> – less than half of [[Pentium 4#Prescott|Prescott]]'s. Penryn's successor [[Nehalem (microarchitecture)|Nehalem]] has a two cycles higher branch misprediction penalty than Core/Penryn.<ref>{{cite web |last1=De Gelas |first1=Johan |title=The Bulldozer Aftermath: Delving Even Deeper |url=https://www.anandtech.com/show/5057/the-bulldozer-aftermath-delving-even-deeper/2 |archive-url=https://web.archive.org/web/20120601190408/http://www.anandtech.com/show/5057/the-bulldozer-aftermath-delving-even-deeper/2 |url-status=dead |archive-date=June 1, 2012 |website=[[AnandTech]]}}</ref><ref>{{cite web |last1=Thomadakis |first1=Michael Euaggelos |title=The Architecture of the Nehalem Processor and Nehalem-EP SMP Platforms |url=https://www.researchgate.net/publication/235960679}}</ref> Core can ideally sustain up to 4 [[instructions per cycle]] (IPC) execution rate, compared to the 3 IPC capability of [[P6 (microarchitecture)|P6]], [[Pentium M (microarchitecture)|Pentium M]] and [[NetBurst]] microarchitectures. The new architecture is a dual core design with a shared [[L2 cache]] engineered for maximum [[performance per watt]] and improved scalability.

One new technology included in the design is [[Macro-Ops Fusion]], which combines two [[x86]] instructions into a single [[micro-operation]]. For example, a common code sequence like a compare followed by a conditional jump would become a single micro-op. However, this technology does not work in 64-bit mode.

Core can speculatively execute [[Memory disambiguation#RAW dependence violations|loads ahead of preceding stores]] with unknown addresses.<ref>{{cite web |last1=De Gelas |first1=Johan |title=Intel Core versus AMD's K8 architecture |url=https://www.anandtech.com/show/1998/5 |archive-url=https://web.archive.org/web/20101107020630/http://www.anandtech.com/show/1998/5 |url-status=dead |archive-date=November 7, 2010 |website=[[AnandTech]]}}</ref>

Other new technologies include 1 cycle throughput (2 cycles previously) of all 128-bit SSE instructions and a new power saving design. All components will run at minimum speed, raising speed dynamically as needed (similar to AMD's [[Cool'n'Quiet]] power-saving technology, and Intel's own [[SpeedStep]] technology from earlier mobile processors). This allows the chip to produce less heat, and minimize power use.

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For most Woodcrest CPUs, the [[front-side bus]] (FSB) runs at 1333 [[MT/s]]; however, this is scaled down to 1066&nbsp;MT/s for lower end 1.60 and 1.86&nbsp;GHz variants.<ref>{{cite web |url=http://processorfinder.intel.com/details.aspx?sSpec=SL9RZ |title=Intel Xeon Processor 5110 |access-date=April 15, 2012 |publisher=Intel}}</ref><ref>{{cite web |url=http://processorfinder.intel.com/details.aspx?sSpec=SL9Ry |title=Intel Xeon Processor 5120 |publisher=Intel |access-date=April 15, 2012}}</ref> The Merom mobile variant was initially targeted to run at an FSB of 667&nbsp;MT/s while the second wave of Meroms, supporting 800&nbsp;MT/s FSB, were released as part of the Santa Rosa platform with a different socket in May 2007. The desktop-oriented Conroe began with models having an FSB of 800&nbsp;MT/s or 1066&nbsp;MT/s with a 1333&nbsp;MT/s line officially launched on July 22, 2007.

The power use of these processors is very low: average energy use is to be in the 1–2 watt range in ultra -low voltage variants, with [[thermal design power]]s (TDPs) of 65 watts for Conroe and most Woodcrests, 80 watts for the 3.0&nbsp;GHz Woodcrest, and 40 or 35 watts for the low-voltage Woodcrest. In comparison, a 2.2&nbsp;GHz AMD [[Opteron]] 875HE processor consumes 55 watts, while the energy efficient [[Socket AM2]] line fits in the 35 watt [[thermal envelope]] (specified a different way so not directly comparable). Merom, the mobile variant, is listed at 35 watts TDP for standard versions and 5 watts TDP for ultra -low voltage (ULV) versions.{{citation needed|date=October 2011}}

Previously, Intel announced that it would now focus on power efficiency, rather than raw performance. However, at [[Intel Developer Forum]] (IDF) in spring 2006, Intel advertised both. Some of the promised numbers were:

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In Intel's [[Intel Tick-Tock|Tick-Tock]] cycle, the 2007/2008 "Tick" was the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23. In Core 2 processors, it is used with the code names Penryn (Socket P), Wolfdale (LGA 775) and Yorkfield (MCM, LGA 775), some of which are also sold as Celeron, Pentium and Xeon processors. In the Xeon brand, the [[Xeon#5200-series "Wolfdale-DP"|Wolfdale-DP]] and [[Xeon#5400-series "Harpertown"|Harpertown]] code names are used for LGA 771 based MCMs with two or four active Wolfdale cores.

Architecturally, 45&nbsp;nm Core 2 processors feature SSE4.1 and new divide/shuffle engine.<ref>{{Cite web|url=http://www.anandtech.com/show/2362|archive-url=https://web.archive.org/web/20100505135238/http://www.anandtech.com/show/2362|url-status=dead|archive-date=May 5, 2010|title = Intel Core 2 Extreme QX9650 - Penryn Ticks Ahead}}</ref>

The chips come in two sizes, with 6 MB and 3 MB L2 cache. The smaller version is commonly called Penryn-3M and Wolfdale-3M and Yorkfield-6M, respectively. The single-core version of Penryn, listed as Penryn-L here, is not a separate model like Merom-L but a version of the Penryn-3M model with only one active core.

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*[http://www.intel.com/products/roadmap/ Intel processor roadmap]

*[https://web.archive.org/web/20070415163814/http://www.pcper.com/article.php?aid=217 A Detailed Look at Intel's New Core Architecture]

*[https://web.archive.org/web/20060310044430/http://anandtech.com/tradeshows/showdoc.aspx?i=2711&p=2 Intel names the Core Microarchitecture]

*[https://web.archive.org/web/20060717124332/http://www.xbitlabs.com/articles/editorial/display/idf-s2006_5.html Pictures of processors using the Core Microarchitecture, among others (also first mention of Clovertown-MP)]

*[https://web.archive.org/web/20060322051611/http://www.tgdaily.com/2006/03/07/idf_keynotes_welcome_to_intel_3-point-0/ IDF keynotes, advertising the performance of the new processors]

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*[http://www.realworldtech.com/page.cfm?ArticleID=RWT030906143144 RealWorld Tech's overview of the Core microarchitecture]

*[https://arstechnica.com/articles/paedia/cpu/core.ars Detailed overview of the Core microarchitecture at Ars Technica]

*[https://archive.today/20130117023531/http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2748 Intel Core versus AMD's K8 architecture at Anandtech]

*[https://web.archive.org/web/20110810020619/http://www.dailytech.com/article.aspx?newsid=2015 Release dates of upcoming Intel Core processors using the Intel Core Microarchitecture]

*[http://www.hexus.net/content/item.php?item=6184 Benchmarks Comparing the Computational Power of Core Architecture against Older Intel NetBurst and AMD Athlon64 Central Processing Units]