Intel Core (microarchitecture): Difference between revisions

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{{short description|Intel processor microarchitecture}}

{{About|the Intel microarchitecture|Intel processors branded as ''Intel Core''|Intel Core}}

{{Use mdy dates|date=October 2018}}

{{About|the Intel microarchitecture|Intel processors branded as ''Intel Core''|Intel Core}}

{{Infobox CPU

| name = Intel Core

| image =

| image_size = 150px

| produced-start =

| produced-end =

| created = {{start date and age|June 26, 2006}}&nbsp;(Xeon)<br/>{{start date and age|July 27, 2006}}&nbsp;(Core&nbsp;2)

<!-- | model = Celeron Series

| model1 = Pentium Series

Line 17 ⟶ 16:

| model6 = Core 2 Extreme Series

| model7 = Xeon Series -->

| model = P6 family ([[Celeron]], [[Pentium]], Pentium Dual-Core, Core 2 range, Xeon)

| numcores = 1–4 (2-6 Xeon)

| transistors = 105M to 582M ([[65 nanometer|65 nm]])<br/>228M to 1900M ([[45 nm]])

<!-- (A1, M0)

| transistors1 = 167M [[65 nanometer|65 nm]] (G0)

| transistors2 = 291M [[65 nanometer|65 nm]] (B2, E1, G0, L2)

| transistors3 = 582M [[65 nanometer|65 nm]] (B3, G0) -->

| slowest = 1.06933

| fastest = 3.335

| slow-unit = GHzMHz

| fast-unit = GHz

| size-from = [[65 nanometer|65 nm]]

| size-to = [[45 nanometer|45 nm]]

| l1cache = 64 KB per core

| l2cache = 1 MB0.5 to 86 MB unifiedper two cores

| l3cache = 8 MB to 16 MB shared (Xeon&nbsp;7400)

| fsb-slowest = 533

| fsb-fastest = 1600

| fsb-slow-unit = [[Transfer (computing)|MT/s]]

| fsb-fast-unit = MT/s

| arch1arch = [[Intelx86-16]], Core[[IA-32]], [[x86-64]]

| microarch = Core

| instructions = [[x86]], [[x86-64]]

| extensions = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]] (45nm Core 2 only), [[VT-x]] (some)

| sock1 = [[Socket M]] (µPGAμPGA 478)

| sock2 = [[Socket P]] (µPGAμPGA 478)

| sock3 = [[Socket T]] ([[LGA 775]])

| sock4 = [[Micro-FCBGA|FCBGASocket J]] (µBGA[[LGA 479771]])

| sock5 = [[Micro-FCBGA|FCBGASocket 604]] (µBGA 965)

| sock6 = [[Micro-FCBGA|FCBGA]] (μBGA 479)

| predecessor = [[NetBurst (microarchitecture)|NetBurst]]<br />[[Enhanced Pentium M (microarchitecture)|Enhanced Pentium M]]

| sock7 = [[Micro-FCBGA|FCBGA]] (μBGA 965)

| successor = [[Penryn (microarchitecture)|Penryn (tick)]]<br>[[Nehalem (microarchitecture)|Nehalem (tock)]]

| predecessor = [[NetBurst (microarchitecture)|NetBurst]]<br />[[Enhanced Pentium M (microarchitecture)|Enhanced Pentium M]] ([[P6 (microarchitecture)|P6]])

| successor = [[Penryn (microarchitecture)|Penryn (tick)]]<br/>(a version of Core)<br/>[[Nehalem (microarchitecture)|Nehalem (tock)]]

| support status = Unsupported

}}

The '''Intel Core microarchitecture''' (previouslyprovisionally knownreferred to as the'''Next Generation Micro-architecture''',<ref>{{cite web |last1=Bessonov |first1=Oleg |title=New Wine into Old Skins. Conroe: Grandson of Pentium III, Nephew of NetBurst? |url=http://ixbtlabs.com/articles2/cpu/p6-nexgen.html |website=ixbtlabs.com |date=9 September 2005}} Note that all mentions of "Next-Generation Micro-Architecturearchitecture" in Intel's slides have asterisks that warn that "micro-architecture name [[To be determined|TBD]]".</ref> and developed as '''Merom''')<ref name="hinton">{{cite web |last1=Hinton |first1=Glenn |title=Key Nehalem Choices |url=https://web.stanford.edu/class/ee380/Abstracts/100217-slides.pdf |date=17 February 2010}}</ref> is a multi-core [[central processing unit|processor]] [[microarchitecture]] unveiledlaunched by [[Intel]] in Q1 mid-2006. It is baseda major onevolution over the [[Yonah (microprocessor)|Yonah]], processorthe design and can be considered anprevious iteration of the [[P6 (microarchitecture)|P6 microarchitecture series]] introducedwhich started in 1995 with [[Pentium Pro]]. HighIt poweralso consumptionreplaced andthe heat[[NetBurst]] intensitymicroarchitecture, thewhich resultingsuffered inabilityfrom tohigh effectivelypower increase [[clock speed]],consumption and otherheat shortcomingsintensity suchdue asto an inefficient [[Pipeline (computing)|pipeline]] weredesigned thefor primaryhigh reasons[[clock whyrate]]. IntelIn abandonedearly the2004, [[NetBurstPrescott (microarchitecture)|NetBurstneeded microarchitecture]]very andhigh switchedpower to areach completelythe differentclocks architecturalit design,needed deliveringfor highcompetitive efficiencyperformance, throughmaking ait smallunsuitable pipelinefor ratherthe thanshift highto clock[[Multi-core speedsprocessor|dual/multi-core]] CPUs. TheOn CoreMay microarchitecture7, initially2004, didIntel not reachconfirmed the clock speedscancellation of the next NetBurst, microarchitecture[[Tejas and Jayhawk]].<ref>{{cite web |title=Intel cancels Tejas, evenmoves afterto movingdual-core designs |url=https://www.eetimes.com/intel-cancels-tejas-moves-to-dual-core-designs/ |website=[[45EE nanometer|45&nbsp;nmTimes]] |date=7 May 2004}}</ref> Intel had been developing Merom, the 64-bit evolution of the [[lithographyPentium M]]., since However2001,<ref aftername="hinton"/> manyand generationsdecided ofto successorexpand microarchitecturesit whichto usedall Coremarket assegments, theirreplacing basisNetBurst (suchin asdesktop [[Nehalemcomputers (microarchitecture)|Nehalem]],and [[Sandyservers. Bridge]]It inherited from Pentium M the choice of a short and more)efficient pipeline, Inteldelivering managedsuperior toperformance eventuallydespite surpassnot reaching the clockhigh speedsclocks of NetburstNetBurst.{{Efn|NetBurst withhad thereached Devil's3.8 CanyonGHz (Improvedin version2004. ofCore initially reached 3 GHz, and after moving to 45nm in [[HaswellPenryn (microarchitecture)|Haswell)Penryn]] microarchitecturewould reachingreach a3.5 baseGHz. frequency[[Westmere (microarchitecture)|Westmere]], the ultimate evolution of 4P6, reached 3.6 GHz base and a3.86 maximumGHz testedboost frequency. of(Excluding the 4.4 GHz usingspecial-order 22&nbsp;nm lithographyXeons. )}}

The first processors that used this architecture were code-named '[[Merom (microprocessor)|Merom]]', '[[Conroe (microprocessor)|Conroe]]', and '[[Woodcrest (microprocessor)|Woodcrest]]'; Merom is for mobile computing, Conroe is for desktop systems, and Woodcrest is for servers and workstations. While architecturally identical, the three processor lines differ in the socket used, bus speed, and power consumption. The initial mainstreamfirst Core-based desktop and mobile processors were branded ''[[PentiumIntel Dual-Core 2|Core 2]]'', later expanding orto the lower-end ''[[Pentium Dual-Core]]'' and low end branded, ''[[CeleronPentium]]''; server and workstation Core-based processors were branded ''[[XeonCeleron]]'', brands; while Intel's first 64-bit desktopserver and mobileworkstation Core-based processors were branded ''[[Intel Core#64-bit Core microarchitecture based|Core 2Xeon]]''.

==Features==

The Core microarchitecture returned to lower [[clock rate]]s and improved the usageuse of both available clock cycles and power when compared with the preceding [[NetBurst]] (microarchitecture)|NetBurst microarchitecture]] of the [[Pentium 4]]/ and [[Pentium D|D]]-branded CPUs.<ref>{{cite web|title=Penryn Arrives: Core 2 Extreme QX9650 Review |url=http://www.extremetech.com/article2/0,1697,2208241,00.asp |publisher=ExtremeTech |access-date=October 30, 2006 |url-status=dead |archive-url=https://web.archive.org/web/20071031004242/http://www.extremetech.com/article2/0%2C1697%2C2208241%2C00.asp |archive-date=October 31, 2007 }}</ref> The Core microarchitecture provides more efficient decoding stages, execution units, [[CPU cache|cache]]s, and [[Bus (computing)|buses]], reducing the [[Electric energy consumption|power consumption]] of Core 2-branded CPUs while increasing their processing capacity. Intel's CPUs have varied widely in power consumption according to clock rate, architecture, and semiconductor process, shown in the [[CPU power dissipation]] tables.

Like the last NetBurst CPUs, Core based processors feature multiple cores and hardware virtualization support (marketed as [[Intel VT-x]]), as well asand [[Intel 64]] and [[SSSE3]]. However, Core-based processors do not have the [[Hyperhyper-Threading|Hyper-Threading Technologythreading]] foundtechnology as in Pentium 4 processors. This is because the Core microarchitecture is a descendantbased ofon the [[P6 (microarchitecture)|P6 microarchitecture]] used by Pentium Pro, Pentium II, Pentium III, and Pentium M.

The L1 cache size was enlarged inof the Core microarchitecture, fromat 3264&nbsp;KB onL1 Pentium II&nbsp;cache/&nbsp;IIIcore (1632&nbsp;KB L1 Data + 1632&nbsp;KB L1 Instruction) tois as large as in Pentium M, up from 6432&nbsp;KB L1on cachePentium II&nbsp;/core&nbsp;III (3216&nbsp;KB L1 Data + 3216&nbsp;KB L1 Instruction) on Pentium M and Core/Core 2. The consumer version also lacks an L3 Cachecache foundas in the Gallatin core of the Pentium 4 Extreme Edition, though it is exclusively present in high-end versions of Core-based Xeons. Both an L3 cache and Hyperhyper-threading were reintroduced again to consumer line in the [[Nehalem microarchitecture]].

==Roadmap==

{{mainMain|Intel Tick-Tock}}

{{IntelProcessorRoadmap}}

Line 68 ⟶ 70:

==Technology==

[[Image:Intel Core2 arch.svg|right|thumb|upright=2|Intel Core microarchitecture]]

While the Core microarchitecture is a major architectural revision, it is based in part on the [[Pentium M]] processor family designed by Intel Israel.<ref>{{ cite web | url = http://seattletimes.nwsource.com/html/businesstechnology/2003658346_intelisrael09.html | title = How Israel saved Intel | last = King | first = Ian | publisher = The Seattle Times | date = April 9, 2007 | access-date = April 15, 2012 }}</ref> The [[PenrynPipeline (microprocessorcomputing)|Penrynpipeline]] of Core/[[pipelinePenryn (computingmicroarchitecture)|pipelinePenryn]] is 12–1414 stages long<ref name="bittech08">{{cite web |title=Intel Core i7Driving energy-efficient Nehalemperformance, Architectureinnovation Dive:with 5Intel -Core Architecturemicroarchitecture Enhancements|url=httphttps://www.bit-techintel.netcom/hardwarepressroom/cpuskits/2008events/11idfspr_2006/03/intel-core-i7-nehalem-architecture-dive/5|first=RichardBackgrounderIDF.pdf |last publisher=Intel Swinburne|date=November7 3, 2008|access-date=August 21,March 20112006}}</ref> —– less than half of [[Pentium 4#Prescott|Prescott]]'s, a signature feature of wide order execution cores. Penryn's successor, [[Nehalem (microarchitecture)|Nehalem]] borrowedhas morea heavilytwo fromcycles thehigher Pentiumbranch 4misprediction andpenalty hasthan 20-24Core/Penryn.<ref>{{cite pipelineweb stages|last1=De Gelas |first1=Johan |title=The Bulldozer Aftermath: Delving Even Deeper |url=https://www.anandtech.com/show/5057/the-bulldozer-aftermath-delving-even-deeper/2 |archive-url=https://web.archive.org/web/20120601190408/http://www.anandtech.com/show/5057/the-bulldozer-aftermath-delving-even-deeper/2 |url-status=dead |archive-date=June 1, 2012 |website=[[AnandTech]]}}</ref><ref>{{cite nameweb |last1="bittech08"Thomadakis |first1=Michael Euaggelos |title=The Architecture of the Nehalem Processor and Nehalem-EP SMP Platforms |url=https://www.researchgate.net/publication/235960679}}</ref> Core's can ideally sustain up to 4 [[executioninstructions unitper cycle]] is(IPC) 4execution issues widerate, compared to the 3-issue coresIPC capability of [[P6 (microarchitecture)|P6]], [[Pentium M (microarchitecture)|Pentium M]], and 2-issue cores of [[NetBurst (microarchitecture)|NetBurst]] microarchitectures. The new architecture is a dual core design with linked [[L1 cache]] anda shared [[L2 cache]] engineered for maximum [[performance per watt]] and improved scalability.

One new technology included in the design is [[Macro-Ops Fusion]], which combines two [[x86]] instructions into a single [[micro-operation]]. For example, a common code sequence like a compare followed by a conditional jump would become a single micro-op. UnfortunatelyHowever, this technology does not work in 64-bit mode.

Core can speculatively execute [[Memory disambiguation#RAW dependence violations|loads ahead of preceding stores]] with unknown addresses.<ref>{{cite web |last1=De Gelas |first1=Johan |title=Intel Core versus AMD's K8 architecture |url=https://www.anandtech.com/show/1998/5 |archive-url=https://web.archive.org/web/20101107020630/http://www.anandtech.com/show/1998/5 |url-status=dead |archive-date=November 7, 2010 |website=[[AnandTech]]}}</ref>

Other new technologies include 1 cycle throughput (2 cycles previously) of all 128-bit SSE instructions and a new power saving design. All components will run at minimum speed, ramping up speed dynamically as needed (similar to AMD's [[Cool'n'Quiet]] power-saving technology, as well as Intel's own [[SpeedStep]] technology from earlier mobile processors). This allows the chip to produce less heat, and consume as little power as possible.

Other new technologies include 1 cycle throughput (2 cycles previously) of all 128-bit SSE instructions and a new power saving design. All components will run at minimum speed, ramping upraising speed dynamically as needed (similar to AMD's [[Cool'n'Quiet]] power-saving technology, as well asand Intel's own [[SpeedStep]] technology from earlier mobile processors). This allows the chip to produce less heat, and consume as littleminimize power as possibleuse.

For most Woodcrest CPUs, the [[Front side bus|front side bus (FSB)]] runs at 1333 [[MT/s]]; however, this is scaled down to 1066&nbsp;MT/s for lower end 1.60 and 1.86&nbsp;GHz variants.<ref>{{ cite web | url = http://processorfinder.intel.com/details.aspx?sSpec=SL9RZ | title = Intel Xeon Processor 5110 | access-date = April 15, 2012 | publisher=Intel }}</ref><ref>{{ cite web | url = http://processorfinder.intel.com/details.aspx?sSpec=SL9Ry | title = Intel Xeon Processor 5120 | publisher = Intel | access-date = April 15, 2012}}</ref> The Merom mobile variant was initially targeted to run at an FSB of 667&nbsp;MT/s while the second wave of Meroms, supporting 800&nbsp;MT/s FSB, were released as part of the Santa Rosa platform with a different socket in May 2007. The desktop-oriented Conroe began with models having an FSB of 800&nbsp;MT/s or 1066&nbsp;MT/s with a 1333&nbsp;MT/s line officially launched on July 22, 2007.

For most Woodcrest CPUs, the [[Front side bus|front -side bus]] (FSB)]] runs at 1333 [[MT/s]]; however, this is scaled down to 1066&nbsp;MT/s for lower end 1.60 and 1.86&nbsp;GHz variants.<ref>{{ cite web | url = http://processorfinder.intel.com/details.aspx?sSpec=SL9RZ | title = Intel Xeon Processor 5110 | access-date = April 15, 2012 | publisher=Intel }}</ref><ref>{{ cite web | url = http://processorfinder.intel.com/details.aspx?sSpec=SL9Ry | title = Intel Xeon Processor 5120 | publisher = Intel | access-date = April 15, 2012}}</ref> The Merom mobile variant was initially targeted to run at an FSB of 667&nbsp;MT/s while the second wave of Meroms, supporting 800&nbsp;MT/s FSB, were released as part of the Santa Rosa platform with a different socket in May 2007. The desktop-oriented Conroe began with models having an FSB of 800&nbsp;MT/s or 1066&nbsp;MT/s with a 1333&nbsp;MT/s line officially launched on July 22, 2007.

The power consumption of these new processors is extremely low—average use energy consumption is to be in the 1–2 watt range in ultra low voltage variants, with [[thermal design power]]s (TDPs) of 65 watts for Conroe and most Woodcrests, 80 watts for the 3.0&nbsp;GHz Woodcrest, and 40 watts for the low-voltage Woodcrest. In comparison, an AMD [[Opteron]] 875HE processor consumes 55 watts, while the energy efficient [[Socket AM2]] line fits in the 35 watt [[thermal envelope]] (specified a different way so not directly comparable). Merom, the mobile variant, is listed at 35 watts TDP for standard versions and 5 watts TDP for Ultra Low Voltage (ULV) versions.{{citation needed|date=October 2011}}

The power consumptionuse of these new processors is extremelyvery low—averagelow: useaverage energy consumptionuse is to be in the 1–2 watt range in ultra -low voltage variants, with [[thermal design power]]s (TDPs) of 65 watts for Conroe and most Woodcrests, 80 watts for the 3.0&nbsp;GHz Woodcrest, and 40 or 35 watts for the low-voltage Woodcrest. In comparison, ana 2.2&nbsp;GHz AMD [[Opteron]] 875HE processor consumes 55 watts, while the energy efficient [[Socket AM2]] line fits in the 35 watt [[thermal envelope]] (specified a different way so not directly comparable). Merom, the mobile variant, is listed at 35 watts TDP for standard versions and 5 watts TDP for Ultraultra-low Low Voltagevoltage (ULV) versions.{{citation needed|date=October 2011}}

Previously, Intel announced that it would now focus on power efficiency, rather than raw performance. However, at [[Intel Developer Forum|IDF]] in the spring of 2006, Intel advertised both. Some of the promised numbers were:

* 20% more performance for Merom at the same power level (compared to [[Core Duo]])

Previously, Intel announced that it would now focus on power efficiency, rather than raw performance. However, at [[Intel Developer Forum|IDF]] (IDF) in the spring of 2006, Intel advertised both. Some of the promised numbers were:

* 40% more performance for Conroe at 40% less power (compared to [[Pentium D]])

* 8020% more performance for WoodcrestMerom at 35%the lesssame power (level; compared to the original [[Xeon#Dual-Core Xeon|dual-core XeonDuo]])

* 2040% more performance for MeromConroe at the40% sameless power; level (compared to [[CorePentium DuoD]])

* 4080% more performance for ConroeWoodcrest at 4035% less power; (compared to the original [[PentiumXeon#Dual-Core Xeon|dual-core DXeon]])

==Processor cores==

The processors of the Core microarchitecture can be categorized by number of cores, cache size, and socket; each combination of these has a unique code name and product code that is used across a number ofseveral brands. For instance, code name "Allendale" with product code 80557 has two cores, 2 MB L2 cache and uses the desktop socket 775, but has been marketed as Celeron, Pentium, Core 2, and Xeon, each with different sets of features enabled. Most of the mobile and desktop processors come in two variants that differ in the size of the L2 cache, but the specific amount of L2 cache in a product can also be reduced by disabling parts at production time. Tigerton dual-cores and all quad-core processors except - are multi-chip modules combining two dies. For the 65&nbsp;nm processors, the same product code can be shared by processors with different dies, but the specific information about which one is used can be derived from the stepping.

Wolfdale-DP and all quad-core processors except Dunnington QC are multi-chip modules combining two dies. For the 65&nbsp;nm processors, the same product code can be shared by processors with different dies, but the specific information about which one is used can be derived from the stepping.

{| class="wikitable" style="font-size: 100%; text-align: center"

|-

! !! fab !! coresCores !! colspan="2" |Mobile !! colspan=2|Desktop, UP Server !! CL Server !! DP Server !! MP Server

|- style="text-align:center;"

! style="text-align:left;"|Single-Core [[65 nm]]

| [[65rowspan="2" nm]]|| 1

| [[Merom (microprocessor)#Merom-L|Merom-L]]<br />80537 || || [[Conroe (microprocessor)#Conroe-L|Conroe-L]]<br />80557 || || || ||

|- style="text-align:center;"

! style="text-align:left;"|Single-Core [[45 nm]]

|

| [[45 nm]]|| 1||

| [[Penryn (microprocessor)#Penryn-L|Penryn-L]]<br />80585 || || || || [[Wolfdale (microprocessor)#Wolfdale-CL|Wolfdale-CL]]<br />80588 ||

|- style="text-align:center;"

! style="text-align:left;"|Dual-Core 65&nbsp;nm

| 65&nbsp;nm|rowspan="2" | 2

| [[Merom (microprocessor)#Merom-2M|Merom-2M]]<br />80537 || [[Merom (microprocessor)#Merom|Merom]]<br />80537 || [[Conroe (microprocessor)#Allendale|Allendale]]<br />80557 || [[Conroe (microprocessor)#Conroe|Conroe]]<br />80557 || [[Conroe (microprocessor)#Conroe-CL|Conroe-CL]]<br />80556 || [[Woodcrest (microprocessor)|Woodcrest]]<br />80556|| [[Xeon#7300-series "Tigerton-DC"|Tigerton-DC]]<br />80564

|- style="text-align:center;"

! style="text-align:left;"|Dual-Core 45&nbsp;nm

| [[Penryn (microprocessor)#Penryn-3M|Penryn-3M]]<br />80577 || [[Penryn (microprocessor)#Penryn|Penryn]]<br />80576|| [[Wolfdale (microprocessor)#Wolfdale-3M|Wolfdale-3M]]<br />80571 || [[Wolfdale (microprocessor)#Wolfdale|Wolfdale]]<br />80570 || [[Wolfdale (microprocessor)#Wolfdale-CL|Wolfdale-CL]]<br />80588 || [[Wolfdale-DP (microprocessor)|Wolfdale-DP]]<br />80573 ||

| 45&nbsp;nm|| 2

| [[Penryn (microprocessor)#Penryn-3M|Penryn-3M]]<br />80577 || [[Penryn (microprocessor)#Penryn|Penryn]]<br />80576|| [[Wolfdale (microprocessor)#Wolfdale-3M|Wolfdale-3M]]<br />80571 || [[Wolfdale (microprocessor)#Wolfdale|Wolfdale]]<br />80570 || [[Wolfdale (microprocessor)#Wolfdale-CL|Wolfdale-CL]]<br />80588 || [[Wolfdale-DP (microprocessor)|Wolfdale-DP]]<br />80573 ||

|- style="text-align:center;"

! style="text-align:left;"|Quad-Core 65&nbsp;nm

| 65&nbsp;nm|rowspan="2" | 4

| || || || [[Kentsfield (microprocessor)|Kentsfield]]<br />80562 || || [[Clovertown (microprocessor)|Clovertown]]<br />80563|| [[Xeon#7300-series "Tigerton (microprocessor)"|Tigerton QC]]<br />80565

|- style="text-align:center;"

! style="text-align:left;"|Quad-Core 45&nbsp;nm

| || [[Penryn (microprocessor)#Penryn-QC|Penryn-QC]]<br />80581 || [[Yorkfield (microprocessor)#Yorkfield-6M|Yorkfield-6M]]<br />80580 || [[Yorkfield (microprocessor)#Yorkfield|Yorkfield]]<br />80569|| [[Yorkfield (microprocessor)#Yorkfield CL|Yorkfield-CL]]<br /> 80584 || [[Harpertown (microprocessor)|Harpertown]]<br />80574 || [[Xeon#7400-series "Dunnington QC"|Dunnington QC]]<br />80583

| 45&nbsp;nm|| 4

| || [[Penryn (microprocessor)#Penryn-QC|Penryn-QC]]<br />80581 || [[Yorkfield (microprocessor)#Yorkfield-6M|Yorkfield-6M]]<br />80580 || [[Yorkfield (microprocessor)#Yorkfield|Yorkfield]]<br />80569|| [[Yorkfield (microprocessor)#Yorkfield CL|Yorkfield-CL]]<br /> 80584 || [[Harpertown (microprocessor)|Harpertown]]<br />80574 || [[Xeon#7400-series "Dunnington QC"|Dunnington QC]]<br />80583

|- style="text-align:center;"

! style="text-align:left;"|Six-Core 45&nbsp;nm

| 6

| 45&nbsp;nm|| 6

| || || || || || || [[Dunnington (microprocessor)|Dunnington]]<br />80582

|}

===Conroe/Merom (65 nm)===

{{Main|Conroe (microprocessor)}}

The original Core 2 processors are based aroundon the same dies that can be identified as [[CPUID]] Family 6 Model 15. Depending on their configuration and packaging, their code names are Conroe ([[LGA 775]], 4 MB L2 cache), Allendale (LGA 775, 2 MB L2 cache), Merom ([[Socket M]], 4 MB L2 cache) and Kentsfield ([[Multimulti-chip module]], LGA 775, 2x4MB L2 cache). Merom and Allendale processors with limited features can be foundare in [[Pentium Dual Core]] and [[Celeron]] processors, while Conroe, Allendale and Kentsfield also are sold as [[Xeon]] processors.

while Conroe, Allendale and Kentsfield also are sold as [[Xeon]] processors.

Additional code names for processors based on this model are [[Xeon#5100-series "Woodcrest"|Woodcrest]] (LGA 771, 4 MB L2 cache), [[Xeon#5300-series "Clovertown"|Clovertown]] (MCM, LGA 771, 2×4MB L2 cache) and [[Xeon#7300-series "Tigerton"|Tigerton]] (MCM, [[Socket 604]], 2×4MB L2 cache), all of which are marketed only under the Xeon brand.

Line 130:

{| class="wikitable" style="font-size: 100%; text-align: center"

! Processor !! Brand name !! Model (list) !! Cores !! L2 Cache !! Socket || TDP

|-

| colspan="7" |'''Mobile processors'''

|-

| [[Merom (microprocessor)|Merom]]-2M

| rowspan=3|Mobile Core 2 Duo

| [[List of Intel Core 2 microprocessors#"Merom-2M" (ultra-low-voltage, 65 nm)|U7xxx]] || rowspan=3|2 || 2 MiBMB || rowspan=2|BGA479 || 10 W

|-

| Merom

| [[List of Intel Core 2 microprocessors#"Merom" (low-voltage, 65 nm)|L7xxx]] || 4 MiBMB || 17 W

|-

| Merom<br/>Merom-2M

| [[List of Intel Core 2 microprocessors#"Merom", "Merom-2M" (standard-voltage, 65 nm)|T5xxx<br/>T7xxx]] || 2–4 MiBMB || [[Socket M]]<br/>[[Socket P]]<br/>BGA479 || 35 W

|-

| Merom XE

| Mobile Core 2 Extreme

| [[List of Intel Core 2 microprocessors#"Merom XE" (standard-voltage, 65 nm)|X7xxx]] || 2 || 4 MiBMB || Socket P || 44 W

|-

| Merom

| rowspan=2|[[Celeron M]]

| [[List of Intel Celeron microprocessors#"Merom", "Merom-L" (standard-voltage, 65 nm)|5x0]] || rowspan=2|1 || rowspan=2|1 MiBMB || Socket M<br/>Socket P || 30 W

|-

| Merom-2M

| [[List of Intel Celeron microprocessors#"Merom-2M" (standard-voltage, 65 nm)|5x5]] || rowspan="3" | Socket P || 31 W

|-

| Merom-2M

| Celeron Dual-Core

| [[List of Intel Celeron microprocessors#"Merom-2M" (standard-voltage, 65 nm) 2|T1xxx]] || 2 || 512–1024 KiB || Socket PKB || 35 W

|-

| Merom-2M

| [[Pentium Dual-Core]]

| [[List of Intel Pentium Dual-Core microprocessors#"Merom-M", "Merom-2M" (65 nm)|T2xxx<br/>T3xxx]] || 2 || 1 MiB || Socket PMB || 35 W

|-

| colspan="7" |'''Desktop processors'''

|-

| [[Conroe (microprocessor)#Allendale|Allendale]] || rowspan=2|[[Xeon]] || [[List of Intel Xeon microprocessors#"Allendale" (65 nm)|3xxx]] || rowspan=2|2 || 2 MB || rowspan=2|[[LGA 775]] || rowspan=2|65 W

Line 164 ⟶ 168:

| [[Conroe (microprocessor)|Conroe]] || [[List of Intel Xeon microprocessors#"Conroe" (65 nm)|3xxx]] || 2–4 MB

|-

| rowspan=2|Conroe and<br/>Allendale

| rowspan=3|[[Intel Core#Core 2 Duo|Core 2 Duo]]

| [[List of Intel Core 2 microprocessors#"Allendale" (65 nm)|E4xxx]] || rowspan=3|2 || 2 MB || rowspan=2 | LGA 775 || rowspan=3|65 W

Line 175 ⟶ 179:

| Conroe-XE

| [[Intel Core#Core 2 Extreme|Core 2 Extreme]]

| [[List of Intel Core 2 microprocessors#"Conroe XE" (65 nm)|X6xxx]] || 2 || 4 MB || rowspan="6" | LGA 775 || 75 W

|-

| Allendale

| [[Pentium Dual-Core]]

| [[List of Intel Pentium Dual-Core microprocessors#"Allendale" (65 nm)|E2xxx]] || 2 || 1 MB || LGA 775 || 65 W

|-

| Allendale

| [[Celeron]]

| [[List of Intel Celeron microprocessors#"Allendale" (65 nm)|E1xxx]] || 2 || 512 KB || LGA 775 || 65 W

|-

| [[Kentsfield (microprocessor)|Kentsfield]]

| [[Xeon]] || [[List of Intel Xeon microprocessors#"Kentsfield" (65 nm)|32xx]] || 4 || 2×4 MiB || [[LGA 775]]MB || 95–105 W

|-

| Kentsfield

| [[Intel Core#Core 2 Quad|Core 2 Quad]] || [[List of Intel Core 2 microprocessors#"Kentsfield" (65 nm)|Q6xxx]] || 4 || 2×4 MiB || LGA 775MB || 95–105 W

|-

| Kentsfield XE

| [[Intel Core#Core 2 Extreme|Core 2 Extreme]] || [[List of Intel Core 2 microprocessors#"Kentsfield XE" (65 nm)|QX6xxx]] || 4 || 2×4 MiB || LGA 775MB || 130 W

|-

| [[Xeon#Woodcrest|Woodcrest]] || rowspan=8|[[Xeon]] || [[List of Intel Xeon microprocessors#"Woodcrest" (65&nbsp;nm)|51xx]] || 2 || 4 MB || LGA 771 || 65–80 W

Line 202 ⟶ 206:

| X53xx || 120–150 W

|-

| [[Xeon#Tigerton|Tigerton-DC]] || [[List of Intel Xeon microprocessors#"Tigerton" (65&nbsp;nm)|E72xx]] || 2 || rowspan=2|2×4 MB || rowspan=4|[[Socket 604]] || 80 W

|-

| rowspan=3|[[Xeon#Tigerton|Tigerton QC]] || L73xx || rowspan=3| 4 || 50 W

|-

| E73xx || 2×2–2×4 MB || 80 W

Line 220 ⟶ 224:

| Merom-L

| Mobile [[Core 2 Solo]]

| [[List of Intel Core 2 microprocessors#"Merom-L" (ultra-low-voltage, 65 nm)|U2xxx]] || 1 || 2 MiBMB || BGA479 || 5.5 W

|-

| Merom-L

| rowspan=2|[[Celeron M]]

| [[List of Intel Celeron microprocessors#"Merom", "Merom-L" (standard-voltage, 65 nm)|5x0]] || rowspan=2|1 || 512 KiBKB || Socket M<br/>Socket P || 27 W

|-

| Merom-L

| [[List of Intel Celeron microprocessors#"Merom-L" (ultra-low-voltage, 65 nm)|5x3]] || 512–1024 KiBKB || BGA479 || 5.5–10 W

|-

| Conroe-L

| rowspan=2|[[Celeron M]]

| [[List of Intel Celeron microprocessors#"Conroe-L" (65 nm)|4x0]] || rowspan=2|1 || rowspan=2|512 KiBKB || LGA 775 || 35 W

|-

| Conroe-CL

Line 239 ⟶ 243:

===Penryn/Wolfdale (45 nm)===

{{Main|Penryn (microarchitecture)}}

[[Image:Intel_CPU_Core_2_Duo_E8400_Wolfdale_top.jpg|thumb|right|Wolfdale-type Core 2 Duo E8400 top view]]

In Intel's [[Intel Tick-Tock|Tick-Tock]] cycle, the 2007/2008 "Tick" was the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23. In Core 2 processors, it is used with the code names Penryn (Socket P), Wolfdale (LGA 775) and Yorkfield (MCM, LGA 775), some of which are also sold as Celeron, Pentium and Xeon processors. In the Xeon brand, the [[Xeon#5200-series "Wolfdale DP"|Wolfdale-DP]] and [[Xeon#5400-series "Harpertown"|Harpertown]] code names are used for LGA 771 based MCMs with two or four active Wolfdale cores.

[[Image:Intel_CPU_Core_2_Duo_E8400_Wolfdale_perspective.jpg|thumb|right|Wolfdale-type Core 2 Duo E8400 perspective view]]

In Intel's [[Intel Tick-Tock|Tick-Tock]] cycle, the 2007/2008 "Tick" was the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23. In Core 2 processors, it is used with the code names Penryn (Socket P), Wolfdale (LGA 775) and Yorkfield (MCM, LGA 775), some of which are also sold as Celeron, Pentium and Xeon processors. In the Xeon brand, the [[Xeon#5200-series "Wolfdale -DP"|Wolfdale-DP]] and [[Xeon#5400-series "Harpertown"|Harpertown]] code names are used for LGA 771 based MCMs with two or four active Wolfdale cores.

Architecturally, 45nm45&nbsp;nm Core 2 processors feature SSE4.1 and new divide/shuffle engine.<ref>{{Cite web|url=http://www.anandtech.com/show/2362|archive-url=https://web.archive.org/web/20100505135238/http://www.anandtech.com/show/2362|url-status=dead|archive-date=May 5, 2010|title = Intel Core 2 Extreme QX9650 - Penryn Ticks Ahead}}</ref>

The chips come in two sizes, with 6 MB and 3 MB L2 cache. The smaller version is commonly called Penryn-3M and Wolfdale-3M as well asand Yorkfield-6M, respectively. The single-core version of Penryn, listed as Penryn-L here, is not a separate model like Merom-L but a version of the Penryn-3M model with only one active core.

{| class="wikitable" style="font-size: 100%; text-align: center"

! Processor !! Brand name !! Model (list) !! Cores !! L2 Cache !! Socket || TDP

|-

| colspan="7" |'''Mobile processors'''

|-

| [[Penryn (microprocessor)#Penryn-L|Penryn-L]]

| [[Core 2 Solo]]

| [[List of Intel Core 2 microprocessors#"Penryn-L" (ultra-low-voltage, 45 nm, Small Form Factor)|SU3xxx]] || 1 || 3 MiBMB || BGA956 || 5.5 W

|-

| rowspan=2 | [[Penryn (microprocessor)#Penryn-3M|Penryn-3M]]

Line 259 ⟶ 267:

|-

| rowspan=2 | [[Penryn (microprocessor)|Penryn]]

| [[List of Intel Core 2 microprocessors#"Penryn" (low-voltage, 45 nm, Small Form Factor)|SL9xxx]] || rowspan=2|6 MiBMB || 17 W

|-

| [[List of Intel Core 2 microprocessors#"Penryn" (medium-voltage, 45 nm, Small Form Factor)|SP9xxx]] || 25/28 W

|-

| rowspan=2 | Penryn-3M

| [[List of Intel Core 2 microprocessors#"Penryn" (medium-voltage, 45 nm)|P7xxx]] || rowspan=2|3 MiBMB || rowspan=6|[[Socket P]]<br/>FCBGA6 || rowspan=3|25 W

|-

| [[List of Intel Core 2 microprocessors#"Penryn" (medium-voltage, 45 nm)|P8xxx]]

|-

| Penryn

| [[List of Intel Core 2 microprocessors#"Penryn" (medium-voltage, 45 nm)|P9xxx]] || 6 MiBMB

|-

| rowspan=2 | Penryn-3M

| [[List of Intel Core 2 microprocessors#"Penryn" (standard-voltage, 45 nm)|T6xxx]] || 2 MiBMB || rowspan=3|35 W

|-

| [[List of Intel Core 2 microprocessors#"Penryn" (standard-voltage, 45 nm)|T8xxx]] || 3 MiBMB

|-

| rowspan=2 | Penryn

| [[List of Intel Core 2 microprocessors#"Penryn" (standard-voltage, 45 nm)|T9xxx]] || 6 MiBMB

|-

| [[List of Intel Core 2 microprocessors#"Penryn" (Apple iMac specific, 45 nm)|E8x35]] || 6 MiBMB || Socket P || 35-55 W

|-

| Penryn-QC

| Core 2 Quad

| [[List of Intel Core 2 microprocessors#"Penryn QC" (standard-voltage, 45 nm)|Q9xxx]] || 4 || 2x3-2x6 MiBMB || Socket P || 45 W

|-

| Penryn XE

| rowspan=2|Core 2 Extreme

| [[List of Intel Core 2 microprocessors#"Penryn XE" (standard-voltage, 45 nm)|X9xxx]] || 2 || 6 MiBMB || rowspan=2| Socket P || 44 W

|-

| Penryn-QC

| [[List of Intel Core 2 microprocessors#"Penryn QC XE" (standard-voltage, 45 nm)|QX9xxxQX9300]] || 4 || 2x6 MiBMB || 45 W

|-

| rowspan=2 | Penryn-3M

| rowspan=4 | [[Celeron]]

| [[List of Intel Celeron microprocessors#"Penryn-3M" (standard-voltage, 45 nm) 2|T3xxx]] || rowspan=2 | 2 || rowspan=2|1 MiBMB || Socket P || 35 W

|-

| [[List of Intel Celeron microprocessors#"Penryn-3M" (ultra-low-voltage, 45 nm) 2|SU2xxx]] || µFCμFC-BGA 956 ||10 W

|-

| rowspan=2 | Penryn-L

| [[List of Intel Celeron microprocessors#"Penryn-3M" (standard-voltage, 45 nm)|9x0]] || rowspan=2 | 1 || rowspan=2|1 MiBMB || Socket P || 35 W

|-

| [[List of Intel Celeron microprocessors#"Penryn-3M" (ultra-low-voltage, 45 nm)|7x3]] || µFCμFC-BGA 956|| 10 W

|-

| rowspan=2 | Penryn-3M

| rowspan=3 | [[Pentium Dual-Core|Pentium]]

| [[List of Intel Pentium microprocessors#"Penryn-3M" (standard voltage, 45 nm)|T4xxx]]|| rowspan=2 | 2 || 1 MiBMB || Socket P || 35 W

|-

| [[List of Intel Pentium microprocessors#"Penryn-3M" (ultra-low voltage, 45 nm)|SU4xxx]] || rowspan=2|2 MiBMB || rowspan=2|µFCμFC-BGA 956|| 10 W

|-

| Penryn-L

| [[List of Intel Pentium microprocessors#"Penryn-L" (ultra-low voltage, 45 nm)|SU2xxx]] || 1 || 5.5 W

|-

| colspan="7" |'''Desktop processors'''

| rowspan=6|[[Wolfdale (microprocessor)#Wolfdale-3M|Wolfdale-3M]]

|-

| rowspan=6"5" |[[Wolfdale (microprocessor)#Wolfdale-3M|Wolfdale-3M]]

| [[Celeron]]

| [[List of Intel Celeron microprocessors#"Wolfdale-3M" (45 nm)|E3xxx]] || rowspan=7|2 || rowspan=2|1 MB || rowspan=7|LGA 775 || rowspan=6|65 W

Line 330 ⟶ 339:

| [[List of Intel Core 2 microprocessors#"Wolfdale" (45 nm)|E8xxx]] || rowspan=4|6 MB

|-

| rowspan=3"5" |[[Xeon]]

| [[List of Intel Xeon microprocessors#"Wolfdale" (45 nm)|31x0]] || 45-65 W

|-

Line 339 ⟶ 348:

|-

| [[Yorkfield (microprocessor)|Yorkfield]]

| rowspan=2|[[Xeon]]

| [[List of Intel Xeon microprocessors#"Yorkfield" (45 nm)|X33x0]] || rowspan=7|4 || rowspan=2|2×3–2×6 MB || [[LGA 775]] || 65–95 W

|-

Line 358 ⟶ 366:

| [[List of Intel Core 2 microprocessors#"Yorkfield XE" (45 nm)|QX9xxx]] || rowspan=2|2×6 MB || 130–136 W

|-

| [[List of Intel Core 2 microprocessors#"Yorkfield XE" (45 nm)|QX9xx5]] || rowspan="4" | LGA 771 || 150 W

|-

| rowspan=3|[[Xeon#Wolfdale-DP|Wolfdale-DP]]

Line 365 ⟶ 373:

| rowspan=3|2

| rowspan=3|6 MB

| rowspan=3|LGA 771

| 65 W

|-

Line 372 ⟶ 379:

|-

| X52xx

| rowspan="2" | 80 W

|-

| rowspan=3|[[Xeon#Harpertown|Harpertown]]

Line 379 ⟶ 386:

| rowspan=3|2×6 MB

| rowspan=3|LGA 771

| 80 W

|-

| L54xx

Line 392 ⟶ 398:

{| class="wikitable" style="font-size: 100%; text-align: center"

! Processor !! Brand name !! Model (list) !! Cores !! L3 Cachecache !! Socket || TDP

|-

| rowspan=3|[[Xeon#Dunnington|Dunnington]]

Line 415 ⟶ 421:

==Steppings==

The Core microarchitecture uses a number ofseveral [[Steppingstepping level|steppings]]s (steppings), which unlike previousprior microarchitectures not only, represent incremental improvements, but alsoand different sets of features like cache size and low power modes. Most of these steppings are used across brands, typically by disabling some of the features and limiting clock frequencies on low-end chips.

Steppings with a reduced cache size use a separate naming scheme, which means that the releases are no longer in alphabetic order. AdditionalAdded steppings have been used in internal and engineering samples, but are not listedunlisted in the tables.

Many of the high-end Core 2 and Xeon processors use [[Multi-chip module]]s of two or three chips in order to get larger cache sizes or more than two cores.

===Steppings using 65&nbsp; nm process{{Anchor|Steppings using 65nm process}}===

{| class="wikitable" style="font-size: 100%; text-align: center"

|-

Line 442 ⟶ 448:

|-

! B2

| Jul 2006 || 143&nbsp;mm²² || 06F6 || 4&nbsp;MiBMB || 2.93&nbsp;GHz

| [[List of Intel Celeron microprocessors#"Merom", "Merom-L" (standard-voltage, 65 nm)|M5xx]] || || [[List of Intel Core 2 microprocessors#"Merom" (standard-voltage, 65 nm)|T5000 T7000]] [[List of Intel Core 2 microprocessors#"Merom" (low-voltage, 65 nm)|L7000]]

| || || [[List of Intel Core 2 microprocessors#"Conroe" (65 nm)|E6000 X6000]]

| [[List of Intel Xeon microprocessors#"Conroe" (65 nm)|3000]]

Line 449 ⟶ 455:

|-

! B3

| Nov 2006 || 143&nbsp;mm²² || 06F7 || 4&nbsp;MiBMB || 3.00&nbsp;GHz

| || ||

| || || ||

Line 457 ⟶ 463:

|-

! L2

| Jan 2007 || 111&nbsp;mm²² || 06F2 || 2&nbsp;MiBMB || 2.13&nbsp;GHz

| || || [[List of Intel Core 2 microprocessors#"Merom" (standard-voltage, 65 nm)|T5000]] [[List of Intel Core 2 microprocessors#"Merom-2M" (ultra-low-voltage, 65 nm)|U7000]]

| || [[List of Intel Pentium Dual-Core microprocessors#"Allendale" (65 nm)|E2000]]

Line 466 ⟶ 472:

|-

! E1

| May 2007 || 143&nbsp;mm²² || 06FA || 4&nbsp;MiBMB || 2.80&nbsp;GHz

| [[List of Intel Celeron microprocessors#"Merom", "Merom-L" (standard-voltage, 65 nm)|M5xx]] ||

| [[List of Intel Core 2 microprocessors#"Merom" (standard-voltage, 65 nm)|T7000]] [[List of Intel Core 2 microprocessors#"Merom" (low-voltage, 65 nm)|L7000]] [[List of Intel Core 2 microprocessors#"Merom XE" (standard-voltage, 65 nm)|X7000]]

| || || ||

Line 474 ⟶ 480:

|-

! G0

| Apr 2007 || 143&nbsp;mm²² || 06FB || 4&nbsp;MiBMB || 3.00&nbsp;GHz

| [[List of Intel Celeron microprocessors#"Merom", "Merom-L" (standard-voltage, 65 nm)|M5xx]] || || [[List of Intel Core 2 microprocessors#"Merom" (standard-voltage, 65 nm)|T7000]] [[List of Intel Core 2 microprocessors#"Merom" (low-voltage, 65 nm)|L7000]] [[List of Intel Core 2 microprocessors#"Merom XE" (standard-voltage, 65 nm)|X7000]]

| || [[List of Intel Pentium Dual-Core microprocessors#"Conroe" (65 nm)|E2000]] || [[List of Intel Core 2 microprocessors#"Allendale" (65 nm)|E4000]] [[List of Intel Core 2 microprocessors#"Conroe" (65 nm)|E6000]] || [[List of Intel Xeon microprocessors#"Conroe" (65 nm)|3000]]

| [[List of Intel Core 2 microprocessors#"Kentsfield" (65 nm)|Q6000 QX6000]]

Line 482 ⟶ 488:

|-

! G2

| Mar 2009<ref>{{cite web|url=https://qdms.intel.com/dm/i.aspx/AFFA9254-C0C8-4D98-97B7-1F89751F9933/PCN108529-03.pdf|title=Intel Core 2 Duo Mobile Processors T7400 & L7400 and Intel Celeron M Processor 530 (Merom - Napa Refresh), PCN 108529-03, Product Design, B-2 to G-2 Stepping Conversion, Reason for Revision: Change G-0 to G-2 Stepping and Correct Post Conversion MM#|publisher=Intel|date=March 30, 2009}}</ref> || 143&nbsp;mm² || 06FB || 4&nbsp;MB || 2.16&nbsp;GHz

| Mar 2009 || 143&nbsp;mm² || 06FB || 4&nbsp;MiB || 2.16&nbsp;GHz

| [[List of Intel Celeron microprocessors#"Merom", "Merom-L" (standard-voltage, 65 nm)|M5xx]] ||

| [[List of Intel Core 2 microprocessors#"Merom-2M" (standard-voltage, 65 nm)|T5000]] [[List of Intel Core 2 microprocessors#"Merom" (standard-voltage, 65 nm)|T7000]] [[List of Intel Core 2 microprocessors#"Merom" (low-voltage, 65 nm)|L7000]]

| || || ||

Line 490 ⟶ 496:

|-

! M0

| Jul 2007 || 111&nbsp;mm²² || 06FD || 2&nbsp;MiBMB || 2.40&nbsp;GHz

| [[List of Intel Celeron microprocessors#"Merom-2M" (standard-voltage, 65 nm)|5xx]] [[List of Intel Celeron microprocessors#Celeron T1000|T1000]]

| [[List of Intel Pentium Dual-Core microprocessors#"Merom-M", "Merom-2M" (65 nm)|T2000 T3000]]

| [[List of Intel Core 2 microprocessors#"Merom" (standard-voltage, 65 nm)|T5000 T7000]] [[List of Intel Core 2 microprocessors#"Merom-2M" (ultra-low-voltage, 65 nm)|U7000]]

| [[List of Intel Celeron microprocessors#"Allendale" (standard-voltage, 65 nm)|E1000]]

| [[List of Intel Pentium Dual-Core microprocessors#"Allendale" (65 nm)|E2000]]

| [[List of Intel Core 2 microprocessors#"Allendale" (65 nm)|E4000]] ||

Line 501 ⟶ 507:

|-

! A1

| Jun 2007 || 81&nbsp;mm²{{Efn|77 mm² according to Intel,<ref>[https://ark.intel.com/content/www/us/en/ark/products/29736/intel-celeron-processor-440-512k-cache-2-00-ghz-800-mhz-fsb.html Intel® Celeron® Processor 440] ''ark.intel.com''</ref> 80&nbsp;mm² according to Hiroshige Goto<ref>[https://pc.watch.impress.co.jp/docs/2008/0402/kaigai01_07.pdf Intel CPU Die-Size and Microarchitecture]</ref>}} || 10661 || 1&nbsp;MB || 2.20&nbsp;GHz

| Jun 2007 || 81&nbsp;mm² || 10661 || 1&nbsp;MiB || 2.20&nbsp;GHz

| [[List of Intel Celeron microprocessors#"Merom", "Merom-L" (standard-voltage, 65 nm)|M5xx]] || || [[List of Intel Core 2 microprocessors#"Merom-L" (ultra-low-voltage, 65 nm)|U2000]]

| [[List of Intel Celeron microprocessors#"Conroe-L" (65 nm)|220 4x0]] || || ||

| ||

Line 510 ⟶ 516:

Early ES/QS steppings are: B0 (CPUID 6F4h), B1 (6F5h) and E0 (6F9h).

Steppings B2/B3, E1, and G0 of model 15 (cpuid 06fx) processors are evolutionary steps of the standard Merom/Conroe die with 4&nbsp;MiBMB L2 cache, with the short-lived E1 stepping only being used in mobile processors. Stepping L2 and M0 are the "''[[Conroe (microprocessor)#Allendale|Allendale]]"'' chips with just 2&nbsp;MiBMB L2 cache, reducing production cost and power consumption for low-end processors.

The G0 and M0 steppings improve idle power consumption in C1E state and add the C2E state in desktop processors. In mobile processors, all of which support C1 through C4 idle states, steppings E1, G0, and M0 add support for the Mobile Intel 965 Express ([[Centrino#Santa Rosa platform (2007)|Santa Rosa]]) platform with [[Socket P]], while the earlier B2 and L2 steppings only appear for the [[Socket M]] based Mobile Intel 945 Express ([[Centrino#Napa platform (2006)|Napa refresh]]) platform.

The model 22 stepping A1 (cpuid 10661h) marks a significant design change, with just a single core and 1&nbsp;MiBMB L2 cache further reducing the power consumption and manufacturing cost for the low-end. Like the earlier steppings, A1 is not used with the Mobile Intel 965 Express platform.

Steppings G0, M0 and A1 mostly replaced all older steppings in 2008. In 2009, a new stepping G2 was introduced to replace the original stepping B2.<ref>{{cite web|url=http://www.radisys.com/files/support_downloads/PCN%203100003_L7400%20stepping%20change%208%2012%2009.pdf|format=PDF|access-date=June 17, 2012|title=Product Change Notice|url-status=dead|archive-url=https://web.archive.org/web/20101222141937/http://radisys.com/files/support_downloads/PCN%203100003_L7400%20stepping%20change%208%2012%2009.pdf|archive-date=December 22, 2010}}</ref>

===Steppings using 45&nbsp;nm process{{Anchor|Steppings using 45nm process}}===

Line 533 ⟶ 539:

! L2 cache

! Max. clock

! [[Celeron]] || [[Pentium]] || [[Intel Core#64-bit Core microarchitecture based2|Core&nbsp;2]]

! [[Celeron]] || [[Pentium]] || [[Intel Core#64-bit Core microarchitecture based2|Core&nbsp;2]] || [[Xeon]]

! [[Intel Core#64-bit Core microarchitecture based2|Core&nbsp;2]] || [[Xeon]]

! [[Xeon]]

|-

! C0

| Nov 2007 || 107&nbsp;mm²² || 10676 || 6&nbsp;MiBMB || 3.00&nbsp;GHz

| || || [[List of Intel Core 2 microprocessors#"Penryn" (Apple iMac specific, 45 nm)|E8000]] [[List of Intel Core 2 microprocessors#"Penryn-3M" (medium-voltage, 45 nm)|P7000]] [[List of Intel Core 2 microprocessors#"Penryn-3M" (standard-voltage, 45 nm)|T8000]] [[List of Intel Core 2 microprocessors#"Penryn" (standard-voltage, 45 nm)|T9000]] [[List of Intel Core 2 microprocessors#"Penryn" (medium-voltage, 45 nm)|P9000]] [[List of Intel Core 2 microprocessors#"Penryn" (medium-voltage, 45 nm, Small Form Factor)|SP9000]] [[List of Intel Core 2 microprocessors#"Penryn" (low-voltage, 45 nm, Small Form Factor)|SL9000]] [[List of Intel Core 2 microprocessors#"Penryn XE" (standard-voltage, 45 nm)|X9000]]

| || || [[List of Intel Core 2 microprocessors#"Wolfdale" (45 nm)|E8000]] || [[List of Intel Xeon microprocessors#"Wolfdale" (45 nm)|3100]]

Line 546 ⟶ 552:

|-

! M0

| Mar 2008 || 82&nbsp;mm² ² || 10676 || 3&nbsp;MiBMB || 2.40&nbsp;GHz

| [[List of Intel Celeron microprocessors#"Penryn-3M" (ultra-low-voltage, 45 nm)|7xx]] ||

| [[List of Intel Core 2 microprocessors#"Penryn-3M" (ultra-low-voltage, 45 nm, Small Form Factor)|SU3000]] [[List of Intel Core 2 microprocessors#"Penryn-3M" (medium-voltage, 45 nm)|P7000 P8000]] [[List of Intel Core 2 microprocessors#"Penryn-3M" (standard-voltage, 45 nm)|T8000]] [[List of Intel Core 2 microprocessors#"Penryn-3M" (ultra-low-voltage, 45 nm, Small Form Factor)|SU9000]]

Line 555 ⟶ 561:

|-

! C1

| Mar 2008 || 107&nbsp;mm²² || 10677 || 6&nbsp;MiBMB || 3.20&nbsp;GHz

| || ||

| || ||

Line 563 ⟶ 569:

|-

! M1

| Mar 2008 || 82&nbsp;mm² ² || 10677 || 3&nbsp;MiBMB || 2.50&nbsp;GHz

| || ||

| || ||

Line 571 ⟶ 577:

|-

! E0

| Aug 2008 || 107&nbsp;mm²² || 1067A || 6&nbsp;MiBMB || 3.33&nbsp;GHz

| || || [[List of Intel Core 2 microprocessors#"Penryn" (standard-voltage, 45 nm)|T9000]] [[List of Intel Core 2 microprocessors#"Penryn" (medium-voltage, 45 nm)|P9000]] [[List of Intel Core 2 microprocessors#"Penryn" (medium-voltage, 45 nm, Small Form Factor)|SP9000]] [[List of Intel Core 2 microprocessors#"Penryn" (low-voltage, 45 nm, Small Form Factor)|SL9000]] [[List of Intel Core 2 microprocessors#"Penryn QC" (standard-voltage, 45 nm)|Q9000]] [[List of Intel Core 2 microprocessors#"Penryn QC XE" (standard-voltage, 45 nm)|QX9000]]

| || || [[List of Intel Core 2 microprocessors#"Wolfdale" (45 nm)|E8000]]

Line 580 ⟶ 586:

|-

! R0

| Aug 2008 || 82&nbsp;mm² ² || 1067A || 3&nbsp;MiBMB || 2.93&nbsp;GHz

| [[List of Intel Celeron microprocessors#"Penryn-3M" (ultra-low-voltage, 45 nm)|7xx]] [[List of Intel Celeron microprocessors#"Penryn-3M" (standard-voltage, 45 nm)|900]] [[List of Intel Celeron microprocessors#Celeron SU2000|SU2000]] [[List of Intel Celeron microprocessors#Celeron T3000|T3000]] || [[List of Intel Pentium microprocessors#"Penryn-3M" (standard voltage, 45 nm)|T4000]] [[List of Intel Pentium microprocessors#"Penryn-L" (ultra-low voltage, 45 nm)|SU2000]] [[List of Intel Pentium microprocessors#"Penryn-3M" (ultra-low voltage, 45 nm)|SU4000]] || [[List of Intel Core 2 microprocessors#"Penryn-3M" (ultra-low-voltage, 45 nm, Small Form Factor)|SU3000]] [[List of Intel Core 2 microprocessors#"Penryn-3M" (standard-voltage, 45 nm)|T6000]] [[List of Intel Core 2 microprocessors#"Penryn-3M" (ultra-low-voltage, 45 nm, Small Form Factor)|SU7000]] [[List of Intel Core 2 microprocessors#"Penryn-3M" (medium-voltage, 45 nm)|P8000]] [[List of Intel Core 2 microprocessors#"Penryn-3M" (ultra-low-voltage, 45 nm, Small Form Factor)|SU9000]]

| [[List of Intel Celeron microprocessors#"Wolfdale-3M" (45 nm)|E3000]] || [[List of Intel Pentium Dual-Core microprocessors#"Wolfdale-3M" (45 nm)|E5000]] [[List of Intel Pentium microprocessors#"Wolfdale-3M" (45 nm) 2|E6000]]

| [[List of Intel Core 2 microprocessors#"Wolfdale-3M" (45 nm)|E7000]] ||

Line 589 ⟶ 595:

|-

! A1

| Sep 2008 || 503&nbsp;mm² ² || 106D1 || 3&nbsp;MiBMB || 2.67&nbsp;GHz

| || ||

| || ||

Line 596 ⟶ 602:

|}

In the model 23 (cpuid 01067xh), Intel started marketing stepping with full (6&nbsp;MiBMB) and reduced (3&nbsp;MiBMB) L2 cache at the same time, and giving them identical cpuid values. All steppings have the new [[SSE4|SSE4.1]] instructions. Stepping C1/M1 was a bug fix version of C0/M0 specifically for quad core processors and only used in those. Stepping E0/R0 adds two new instructions (XSAVE/XRSTOR) and replaces all earlier steppings.

In mobile processors, stepping C0/M0 is only used in the Intel Mobile 965 Express ([[Centrino#Santa Rosa platform (2007)|Santa Rosa refresh]]) platform, whereas stepping E0/R0 supports the later Intel Mobile 4 Express ([[Centrino#Montevina platform (2008)|Montevina]]) platform.

Model 30 stepping A1 (cpuid 106d1h) adds an L3 cache as well asand six instead of the usual two cores, which leads to an unusually large die size of 503&nbsp;mm²².<ref>{{cite web |title=ARK entry for Intel Xeon Processor X7460 |url=http://ark.intel.com/Product.aspx?id=36947&processor=X7460&spec-codes=SLG9P |publisher=Intel |access-date=July 14, 2009}}</ref> As of February 2008, it has only found its way into the very high-end Xeon 7400 series ([[Dunnington (microprocessor)|Dunnington]]).

==System requirements==

Line 608 ⟶ 614:

Supporting [[chipset]]s are:

* [[Intel Corporation|Intel]]: 865G/PE/P, 945G/GZ/GC/P/PL, 965G/P, 975X, P/G/Q965, Q963, 946GZ/PL, P3x, G3x, Q3x, X38, X48, P4x, 5400 Express ''(See also: [[List of Intel chipsets]]'')

* [[NVIDIANvidia]]: [[nForce4|nForce4]] Ultra/SLI X16]] for Intel, [[nForce 500|nForce 570/590 SLI]] for Intel, [[nForce 600|nForce 650i Ultra/650i SLI/680i LT SLI/680i SLI]] and [[nForce 700|nForce 750i SLI/780i SLI/790i SLI/790i Ultra SLI]].

* [[VIA Technologies|VIA]]: P4M800, P4M800PRO, P4M890, P4M900, PT880 Pro/Ultra, PT890. ''(See also: [[List of VIA chipsets]]'')

* [[Silicon Integrated Systems|SiS]]: 662, 671, 671fx, 672, 672fx

* [[ATI Technologies|ATI]]: [[Xpress 200|Radeon Xpress 200]] and CrossFire Xpress 3200 for Intel

:

The Yorkfield XE model QX9770 (45&nbsp;nm with 1600 MT/s FSB) has limited chipset compatibility - with only X38, P35 (Withwith [[Overclockingoverclocking]]) and some high-performance X48 and P45 motherboards being compatible. BIOS updates were gradually being released to provide support for the Penryn technology, and the QX9775 is only compatible with the Intel D5400XS motherboard. The Wolfdale-3M model E7200 also has limited compatibility (at least the Xpress 200 chipset is incompatible){{Citation needed|date=September 2009}}).

Although a motherboard may have the required chipset to support Conroe, some motherboards based on the above-mentioned chipsets do not support Conroe. This is because all Conroe-based processors require a new power delivery feature set specified in [http://download.intel.com/design/processor/applnots/31321402.pdf Voltage Regulator-Down (VRD) 11.0]. This requirement is a result of Conroe's significantly lower power consumption, compared to the Pentium 4/D CPUs it replaced. A motherboard that has both a supporting chipset and VRD 11 supports Conroe processors, but even then some boards will need an updated [[BIOS]] to recognize Conroe's FID (Frequency ID) and VID (Voltage ID).

===Synchronous memory modules===

Unlike the previousprior [[Pentium 4]] and [[Pentium D]] design, the Core 2 technology sees a greater benefit from memory running [[Synchronization (computer science)|synchronously]] with the [[Front Sidefront-side Busbus]] (FSB). This means that for the Conroe CPUs with FSB of 1066&nbsp;MT/s, the ideal memory performance for DDR2 is [[DDR2 SDRAM#Specification standards|PC2-8500]]. In a few configurations, using [[DDR2 SDRAM#Specification standards|PC2-5300]] instead of PC2-4200 can actually decrease performance. Only when going to [[DDR2 SDRAM#Specification standards|PC2-6400]] is there a significant performance increase. While DDR2 memory models with tighter timing specifications do improve performance, the difference in real world games and applications is often negligible.<ref>{{cite web |title=Intel Core 2: Is high speed memory worth its price? |url=http://www.madshrimps.be/gotoartik.php?articID=472 |publisher=Madshrimps | author=piotke | date = August 1, 2006 |access-date=August 1, 2006}}</ref>

Optimally, the memory bandwidth afforded should match the bandwidth of the FSB, that is to say that a CPU with a 533&nbsp;MT/s rated bus speed should be paired with RAM matching the same rated speed, for example DDR2 533, or PC2-4200. A common myth{{Citation needed|date=February 2011}} is that installing interleaved RAM will offer double the bandwidth. However, at most the increase in bandwidth by installing interleaved RAM is roughly 5–10%. The [https://web.archive.org/web/20060116070359/http://www.extremetech.com/article2/0,1697,1155324,00.asp AGTL+ PSB] used by all [[NetBurst (microarchitecture)|NetBurst]] processors as well asand current and medium-term (pre-[[Intel QuickPath Interconnect|QuickPath]]) Core 2 processors provide a 64-bit data path. Current chipsets provide for a couple of either DDR2 or DDR3 channels.

{| class="wikitable" style="font-size: 100%; text-align: center"

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|-

! style="text-align:left;" rowspan="2"| Processor model

! style="text-align:left;" rowspan="2"| Front -side bus

! style="text-align:left;" colspan="3"| Matched memory and maximum bandwidth<br /><small>single channel /, dual channel</small>

|-

! [[DDR SDRAM#Chips and modules|DDR]]

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| <small>'''Mobile:'''</small> T5200, T5300, U2''n''00, U7''n''00

|align=center| 533 [[Megatransfer|MT/s]]

| style="vertical-align:top; text-align:center;" rowspan="2"| PC-3200 (DDR-400)<br /><small>3.2 GB/s</small>

| style="vertical-align:top; text-align:center;" rowspan="2"| PC2-4200 (DDR2-533)<br /><small>4.264 GB/s</small><br />PC2-8500 (DDR2-1066)<br /><small>8.532 GB/s</small>

| style="vertical-align:top; text-align:center;" rowspan="2"| PC3-8500 (DDR3-1066)<br /><small>8.530 GB/s</small>

|-

| <small>'''Desktop:'''</small> E6''n''00, E6''n''20, X6''n''00, E7''n''00, Q6''n''00 and QX6''n''00<br /><small>'''Mobile:'''</small> T9400, T9550, T9600, P7350, P7450, P8400, P8600, P8700, P9500, P9600, SP9300, SP9400, X9100

|align=center| 1066 MT/s

|-

| <small>'''Mobile:'''</small> T5''n''00, T5''n''50, T7''n''00 ([[Socket M]]), L7200, L7400

|align=center| 667 MT/s

| style="vertical-align:top; text-align:center;" rowspan="2"| PC-3200 (DDR-400)<br /><small>3.2 GB/s</small>

| style="vertical-align:top; text-align:center;" rowspan="2"| PC2-5300 (DDR2-667)<br /><small>5.336 GB/s</small>

| style="vertical-align:top; text-align:center;" rowspan="2"| PC3-10600 (DDR3-1333)<br /><small>10.670 GB/s</small>

|-

| <small>'''Desktop:'''</small> E6''n''40, E6''n''50, E8''nn''0, Q9''nn''0, QX6''n''50, QX9650

|align=center| 1333 MT/s

|-

| <small>'''Mobile:'''</small> T5''n''70, T6400, T7''n''00 ([[Socket P]]), L7300, L7500, X7''n''00, T8n00, T9300, T9500, X9000<br /><small>'''Desktop:'''</small> E4''n''00, Pentium E2''nn''0, Pentium E5''nn''0, Celeron 4''n''0, E3''n''00

|align=center| 800 MT/s

| style="vertical-align:top; text-align:center;" rowspan="2"| PC-3200 (DDR-400)<br /><small>3.2 GB/s</small><br />PC-3200 (DDR-400)<br /><small>3.2 GB/s</small>

| style="vertical-align:top; text-align:center;" rowspan="2"| PC2-6400 (DDR2-800)<br /><small>6.400 GB/s</small><br />PC2-8500 (DDR2-1066)<br /><small>8.532 GB/s</small>

| style="vertical-align:top; text-align:center;" rowspan="2"| PC3-6400 (DDR3-800)<br /><small>6.400 GB/s</small><br />PC3-12800 (DDR3-1600)<br /><small>12.800 GB/s</small>

|-

|<small>'''Desktop:'''</small> QX9770, QX9775

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|}

On jobs requiring large amounts of memory access, the quad-core Core 2 processors can benefit significantly<ref>{{cite web | title=Benchmarks of four Prime95 processes on a quad-core |url=http://www.mersenneforum.org/showpost.php?p=106531&postcount=25 |publisher=Mersenne Forum | author=Jacob | date=May 19, 2007 |access-date=May 22, 2007}}</ref> from using [[DDR2 SDRAM#Specification standards|PC2-8500]] memory, which runs at exactly the same speed as the CPU's FSB; this is not an officially supported configuration, but a number ofseveral motherboards support it.

The Core 2 processor does not require the use of DDR2. While the Intel 975X and P965 chipsets require this memory, some motherboards and chipsets support both Core 2 processors and [[DDR SDRAM|DDR]] memory. When using DDR memory, performance may be reduced because of the lower available memory bandwidth.

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==Chip errata==

<!-- Someone should verify this more rigorously. -->

The Core 2 [[memory management unit]] (MMU) in X6800, E6000 and E4000 processors does not operate to previousprior specifications [[implementation|implemented]] in previousprior generations of [[x86]] hardware. This may cause problems, many of them serious security and stability issues, with existingextant [[operating system]] software. Intel's documentation states that their programming manuals will be updated "in the coming months" with information on recommended methods of managing the [[translation lookaside buffer]] (TLB) for Core 2 to avoid issues, and admits that, "in rare instances, improper TLB invalidation may result in unpredictable system behavior, such as hangs or incorrect data."<ref>{{cite web | title = Dual-Core Intel Xeon Processor 7200 Series and Quad-Core Intel Xeon Processor 7300 Series | url = http://download.intel.com/design/processor/datashts/31327807.pdf | page = 46 | format = PDF | access-date = January 23, 2010}}</ref>

Among the issues stated:

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* Allowed memory corruptions outside of the range of permitted writing for a process by running common instruction sequences.

Intel [[erratum|errata]] Ax39, Ax43, Ax65, Ax79, Ax90, Ax99 are said to be particularly serious.<ref>{{cite web | url = http://download.intel.com/design/mobile/SPECUPDT/31407918.pdf | pages = 18–21 | format = PDF | title = Intel Core 2 Duo Processor for Intel Centrino Duo Processor Technology Specification Update }}</ref> 39, 43, 79, which can cause unpredictable behavior or system hang, have been fixed in recent [[stepping (versionStepping numbers)level|steppings]].

Among those who have stated the errata to be particularly serious are [[OpenBSD]]'s [[Theo de Raadt]]<ref>[http{{Cite web|url=https://marc.info/?l=openbsd-misc&m=118296441702631|title='Intel Core 2' - MARC|website=marc.info]}}</ref> and [[DragonFly BSD]]'s [[Matt Dillon (computer scientist)|Matthew Dillon]].<ref>{{ cite web | url = http://undeadly.org/cgi?action=article&sid=20070630105416&mode=expanded&count=14 | title = Matthew Dillon on Intel Core Bugs | publisher = OpenBSD journal | date = June 30, 2007 | access-date = April 15, 2012}}</ref> Taking a contrasting view was [[Linus Torvalds]], calling the TLB issue "totally insignificant", adding, "The biggest problem is that Intel should just have documented the TLB behavior better."<ref>{{ cite web | url = http://www.realworldtech.com/forums/index.cfm?action=detail&id=80552&threadid=80534&roomid=2 | publisher = Real World Technologies | last = Torvalds | first = Linus | title = Core 2 Errata -- problematic or overblown? | access-date = April 15, 2012 | date = June 27, 2007}}</ref>

Microsoft has issued update KB936357 to address the errata by [[microcode]] update,<ref>{{ cite web | url = http://support.microsoft.com/kb/936357 | title = A microcode reliability update is available that improves the reliability of systems that use Intel processors | date = October 8, 2011 | access-date = April 15, 2012 | publisher = Microsoft}}</ref> with no performance penalty. BIOS updates are also available to fix the issue.

==See also==

* [[x86 architecture]]

* [[List of Intel CPU microarchitectures]]

==References==

{{notelist}}

{{reflist|30em}}

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*[http://www.intel.com/products/roadmap/ Intel processor roadmap]

*[https://web.archive.org/web/20070415163814/http://www.pcper.com/article.php?aid=217 A Detailed Look at Intel's New Core Architecture]

*[https://web.archive.org/web/20060310044430/http://anandtech.com/tradeshows/showdoc.aspx?i=2711&p=2 Intel names the Core Microarchitecture]

*[https://web.archive.org/web/20060717124332/http://www.xbitlabs.com/articles/editorial/display/idf-s2006_5.html Pictures of processors using the Core Microarchitecture, among others (also first mention of Clovertown-MP)]

*[https://web.archive.org/web/20060322051611/http://www.tgdaily.com/2006/03/07/idf_keynotes_welcome_to_intel_3-point-0/ IDF keynotes, advertising the performance of the new processors]

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*[http://www.realworldtech.com/page.cfm?ArticleID=RWT030906143144 RealWorld Tech's overview of the Core microarchitecture]

*[https://arstechnica.com/articles/paedia/cpu/core.ars Detailed overview of the Core microarchitecture at Ars Technica]

*[https://archive.today/20130117023531/http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2748 Intel Core versus AMD's K8 architecture at Anandtech]

*[https://web.archive.org/web/20110810020619/http://www.dailytech.com/article.aspx?newsid=2015 Release dates of upcoming Intel Core processors using the Intel Core Microarchitecture]

*[http://www.hexus.net/content/item.php?item=6184 Benchmarks Comparing the Computational Power of Core Architecture against Older Intel NetburstNetBurst and AMD Athlon64 Central Processing Units]

{{Intel processors|core}}

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[[Category:Intel x86 microprocessors|Core microarchitecture]]

[[Category:Intel microarchitectures|Core]]

[[Category:X86 microarchitectures|Core]]

[[Category:Computer-related introductions in 2006]]