MIPS architecture processors: Difference between revisions

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[[File:MIPS Architecture (Pipelined).svg|thumb|right|300px|[[Instruction pipelining|Pipelined]] MIPS, showing the five stages: instruction fetch, instruction decode, execute, memory access and write back.]]

The first MIPS microprocessor, the ''[[R2000 (microprocessor)|R2000]]'', was announced in 1985. It added multiple-cycle multiply and divide instructions in a somewhat independent on-chip unit. New instructions were added to retrieve the results from this unit back to the [[processor register]] file; these result-retrieving instructions were [[interlock|interlocked]].

The R2000 could be booted either [[Endianness|''big-endian'' or ''little-endian'']]. It had thirty-one 32-bit general purpose registers, but no [[status register]] (''condition code register'' (CCR), the designers considered it a potential bottleneck), a feature it shares with the [[AMD 29000]], the [[DEC Alpha]], and [[RISC-V]]. Unlike other registers, the [[program counter]] is not directly accessible.

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[[Quantum Effect Devices]] (QED), a separate company started by former MIPS employees, designed the ''[[R4600]]'' ''Orion'', the ''[[R4700]]'' ''Orion'', the ''[[R4650]]'' and the ''[[R5000]]''. Where the R4000 had pushed clock frequency and sacrificed cache capacity, the QED designs emphasized large caches which could be accessed in just two cycles and efficient use of silicon area. The R4600 and R4700 were used in low-cost versions of the [[SGI Indy]] workstation as well as the first MIPS-based Cisco routers, such as the 36x0 and 7x00-series routers. The [[R4650]] was used in the original [[WebTV]] [[set-top box]]es (now Microsoft TV). The [[R5000]] FPU had more flexible single precision floating-point scheduling than the R4000, and as a result, R5000-based SGI Indys had much better graphics performance than similarly clocked [[R4400]] Indys with the same graphics hardware. SGI gave the old graphics board a new name when it was combined with [[R5000]], to emphasize the improvement. QED later designed the ''RM7000'' and ''[[RM9000]]'' family of devices for [[embedded system]] markets like [[computer network]]ing and laser printers. QED was acquired by the semiconductor manufacturer [[PMC-Sierra]] in August 2000, the latter company continuing to invest in the MIPS architecture. The ''[[RM7000]]'' included an integrated 256 KB L2 cache and a controller for optional L3 cache. The ''RM9xx0'' were a family of [[System-on-a-chip|SOC]] devices which included [[Northbridge (computing)|northbridge]] peripherals such as [[memory controller]], [[Peripheral Component Interconnect|PCI]] controller, [[Gigabit Ethernet]] controller and fast I/O such as a [[HyperTransport]] port.

The ''[[R8000]]'' (1994) was the first [[superscalar]] MIPS design, able to execute two integer or floating point and two memory instructions per cycle. The design was spread over six chips: an integer unit (with 16 KB instruction and 16 KB data caches), a floating-point unit, three fullfully-custom secondary cache tag RAMs (two for secondary cache accesses, one for bus snooping), and a cache controller ASIC. The design had two fully pipelined double precision multiply-add units, which could stream data from the 4 MB off-chip secondary cache. The R8000 powered SGI's [[SGI Challenge|POWER Challenge]] servers in the mid-1990s and later became available in the POWER Indigo2 workstation. Although its FPU performance fit scientific users quite well, its limited integer performance and high cost dampened appeal for most users. The R8000 was sold for only a year and remains fairly rare.

In 1995, the ''[[R10000]]'' was released. This processor was a single-chip design, ran at a higher clock frequency than the R8000, and had larger 32 KB primary instruction and data caches. It was also superscalar, but its major innovation was [[out-of-order execution]]. Even with one memory pipeline and simpler FPU, the vastly improved integer performance, lower price, and higher density made the R10000 preferable for most customers.

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=== Licensable architecture ===

In the early 1990s, MIPS began to [[license]] their designs to third-party vendors. This proved fairly successful due to the simplicity of the core, which allowed it to have many uses that would have formerly used much less able [[complex instruction set computer]] (CISC) designs of similar [[gate count]] and price; the two are strongly related: the price of a CPU is generally related to the number of gates and the number of external pins. [[Sun Microsystems]] attempted to enjoy similar success by licensing their [[SPARC]] core but was not nearly as successful. By the late 1990s, MIPS was a powerhouse in the [[embedded processor]] field. According to MIPS Technologies Inc., there was an exponential growth, with 48-million MIPS-based CPU shipments and 49% of total RISC CPU market share in 1997.<ref name="MIPS Brochure">{{cite web |url=http://www.warthman.com/images/MIPS%20Brochure%20Optimized.pdf |title=MIPS Brochure |publisher=MIPS Technologies Inc. |access-date=March 2, 2013 |archive-date=June 4, 2016 |archive-url=https://web.archive.org/web/20160604022750/http://www.warthman.com/images/MIPS%20Brochure%20Optimized.pdf |url-status=dead }}</ref> MIPS was so successful that SGI spun off MIPS Technologies in 1998. In 2000s fully half of MIPS's income came from licensing their designs, while much of the rest came from contract design work on cores for third parties.

In 1999, MIPS Technologies replaced the previous versions of the MIPS architecture with two architectures, the 32-bit ''MIPS32'' (based on MIPS II with some added features from MIPS III, MIPS IV, and MIPS V) and the 64-bit ''MIPS64'' (based on MIPS V) for licensing. Nippon Electric Corporation ([[NEC]]), [[Toshiba]], and [[SiByte]] (later acquired by [[Broadcom]]) each obtained licenses for the MIPS64 as soon as it was announced. [[Philips]], [[LSI Corporation|LSI Logic]] and [[Integrated Device Technology]] (IDT) have since joined them. Today, the MIPS cores are one of the most-used "heavyweight"{{Clarify|date=June 2009}} cores in the market for computer-like devices: [[handheld PC]]s, set-top boxes, etc.

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=== Embedded markets ===

[[File:Game Boy Advance SP (counterfeit) - board - Ingenic JZ4730JZ4725B-0845.JPGjpg|thumb|168px168x168px|The [[Ingenic]] JZ4730JZ4725 is an example for a MIPS-based [[System on Chip|SoC]].]]

Through the 1990s, the MIPS architecture was widely adopted by the embedded market, including for use in [[computer network]]ing, [[telecommunication]]s, [[video arcade game]]s, [[video game console]]s, [[computer printer]]s, digital [[set-top box]]es, [[digital television]]s, [[DSL modem|DSL]] and [[cable modem]]s, and [[personal digital assistant]]s.

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=== MIPS-based supercomputers ===

One interesting, less common use of the MIPS architecture is in massive processor count supercomputers. [[Silicon Graphics]] (SGI) refocused its business from desktop graphics workstations to the [[high-performance computing]] market in the early 1990s. The success of the company's first foray into server systems, the [[SGI Challenge|Challenge]] series based on the R4400 and [[R8000]], and later [[R10000]], motivated SGI to form a vastly more powerful system. The introduction of the integrated R10000 allowed SGI to produce a system, the [[Origin 2000]], eventually scalable to 1024 CPUs using its [[NUMAlink]] cc-NUMA interconnect. The Origin 2000 begat the [[Origin 3000]] series which topped out with the same 1,024 maximum CPU count but using the R14000 and R16000 chips up to 700&nbsp;MHz. Its MIPS-based supercomputers were withdrawn in 2005 when SGI made the strategic decision to move to Intel's Itanium [[IA-64]] architecture.

A high-performance computing startup named [[SiCortex]] introduced a massively parallel MIPS-based supercomputer in 2007. The machines are based on the MIPS64 architecture and a high performance interconnect using a [[Kautz graph]] topology. The system is very power efficient and computationally powerful.{{citation needed|date=May 2013}} The most innovative aspect of the system was its multicore processing node which integrates six MIPS64 cores, a [[crossbar switch]] [[memory controller]], interconnect [[direct memory access]] (DMA) engine, [[Gigabit Ethernet]] and [[PCI Express]] controllers all on a single chip which consumes only 10 watts of power, yet has a peak floating point performance of 6 giga[[FLOPS]]. The most powerful configuration, the SC5832, is a single cabinet supercomputer consisting of 972 such node chips for a total of 5832 MIPS64 processor cores and 8.2 teraFLOPS of peak performance.

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=== MIPS Aptiv ===

Announced in 2012,<ref>{{Cite web |url=http://www.anandtech.com/show/5826/mips-technologies-updates-processor-ip-lineup-with-aptiv-series |archive-url=https://web.archive.org/web/20120512063917/http://www.anandtech.com/show/5826/mips-technologies-updates-processor-ip-lineup-with-aptiv-series |url-status=dead |archive-date=May 12, 2012 |title=MIPS Technologies Updates Processor IP Lineup with Aptiv Series |last=S. |first=Ganesh T. |date=10 May 2012 |website=Anandtech |access-date=2016-06-22}}</ref> the MIPS Aptiv family includes three 32-bit CPU products based on the MIPS32 Release 3 architecture.

==== microAptiv ====

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=== MIPS Warrior ===

Announced in June 2013,<ref>{{Cite web |url=https://imgtec.com/blog/mips-processors/mips-series5-warrior-cpu-cores-the-next-revolution-in-cpu-ip/ |title=Introducing the MIPS Series5 'Warrior' CPU cores: the next revolution in processor IP from Imagination |date=2013-06-26 |website=Imagination Technologies |language=en-GB |access-date=2016-06-22 }}{{Dead link|date=July 2025 |bot=InternetArchiveBot |fix-attempted=yes }}</ref> the MIPS Warrior family includes multiple 32-bit and 64-bit CPU products based on the MIPS Release 5 and 6 architectures.

==== Warrior M-class ====

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* MIPS P5600 multiprocessor core (MIPS32 Release 5):<ref>{{Cite web |url=https://imgtec.com/mips/warrior/p-class-p5600-multiprocessor-core/ |title=P-Class P5600 Multiprocessor Core |website=Imagination Technologies |language=en-GB |access-date=2016-06-22}}</ref> hardware virtualization with hardware table walk, 128-bit SIMD, 40-bit eXtended Physical Addressing (XPA)

* MIPS P6600 multiprocessor core (MIPS64 Release 6): hardware virtualization with hardware table walk, 128-bit SIMD

== Trivia ==

The MIPS rabbit character from ''[[Super Mario 64]]'' was named after the MIPS microprocessor.

==See also==