Multi-channel memory architecture: Difference between revisions

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In the fields of [[digital electronics]] and [[computer hardware]], '''multi-channel memory architecture''' is a technology that increases the data transfer rate between the [[DRAM]] memory and the [[memory controller]] by adding more channels of communication between them. Theoretically, this multiplies the data rate by exactly the number of channels present. Dual-channel memory employs two channels. The technique goes back as far as the 1960s having been used in [[IBM System/360 Model 91]] and in [[CDC 6600]].<ref name="JacobNg2007">{{cite book| first1=Bruce | last1 = Jacob | first2 = Spencer | last2 = Ng | first3=David | last3 = Wang|title= Memory systems: cache, DRAM, disk|year = 2007 | publisher = Morgan Kaufmann|isbn=978-0-12-379751-3|page= 318}}</ref>

Modern high-end desktop and workstation processors such as the [[Advanced Micro Devices|AMD]] [[Ryzen Threadripper]] series and the [[Intel]] [[List of Intel Core i9 processors|Core i9 Extreme Edition]] lineup support quad-channel memory. Server processors from the AMD [[Epyc]] series and the Intel [[Xeon]] platforms give support to memory bandwidth starting from quad-channel module layout to up to octa12-channel layout.<ref>{{Citecite web |lastlast1=jpringleShilov |datefirst1=SeptemberAnton 12, 2017|title=BenchmarkingAMD Epyc,Confirms Ryzen,Twelve andDDR5 Xeon:Memory TyrannyChannels ofFor Zen 4 EPYC CPUs Memory|url=https://www.myromstomshardware.orgcom/forumnews/viewtopic.php?pamd-confirms-12-ddr5-memory-channels-on-genoa |website=18295Tom's Hardware |access-date=April9 23,December 2021 |websitepublisher=[[RegionalFuture OceanUS ModelingInc System]]|access-date=22 April 2024}}</ref> In March 2010, AMD released [[Socket G34]] and Magny-Cours Opteron 6100 series<ref name = Opteron6100>{{cite web | publisher = AMD | title = Opteron 6000 Series Platform Quick Reference Guide | url = http://sites.amd.com/us/documents/48101a_opteron%20_6000_qrg_rd2.pdf | access-date = 2012-10-15 | archive-url = https://web.archive.org/web/20120512170219/http://sites.amd.com/us/Documents/48101A_Opteron%20_6000_QRG_RD2.pdf | archive-date = 2012-05-12 | url-status = dead }}</ref> processors with support for quad-channel memory. In 2006, Intel released chipsets that support quad-channel memory for its [[LGA771]] platform<ref>{{Citation | url = http://ark.intel.com/products/27746/Intel-5000P-Memory-Controller | publisher = Intel | title = 5000P memory controller}}.</ref> and later in 2011 for its [[LGA2011]] platform.<ref>{{Citation | url = http://www.techpowerup.com/138087/Intel-LGA2011-Socket-X68-Express-Chipset-Pictured.html | title = Intel LGA2011 socket x68 express chipset pictured | date = 10 January 2011 | publisher = Tech power up}}.</ref> Microcomputer chipsets with even more channels were designed; for example, the chipset in the [[AlphaStation]] 600 (1995) supports eight-channel memory, but the [[backplane]] of the machine limited operation to four channels.<ref>{{Citation | journal = HP | url = http://www.hpl.hp.com/hpjournal/dtj/vol7num1/vol7num1art7.txt | title = The Design and Verification of the AlphaStation 600 5-series Workstation | volume = 7 | number = 1 | author1 = John H. Zurawski | author2 = John E. Murray | author3 = Paul J. Lemmon | access-date = 2011-10-19 | archive-date = 2021-02-25 | archive-url = https://web.archive.org/web/20210225050210/https://www.hpl.hp.com/hpjournal/dtj/vol7num1/vol7num1art7.txt | url-status = dead }}.</ref> <!-- TO-DO: Cite a machine where they actually used 8 channels. -->

== Dual-channel architecture ==

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Dual-channel architecture is a technology implemented on motherboards by the motherboard manufacturer and does not apply to memory modules. Theoretically any matched pair of memory modules may be used in either single- or dual-channel operation, provided the motherboard supports this architecture.

With the introduction of [[DDR5]], each DDR5 DIMM has two independent sub-channels.

=== Performance ===

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When operating in triple-channel mode, [[memory latency]] is reduced due to interleaving, meaning that each module is accessed sequentially for smaller bits of data rather than completely filling up one module before accessing the next one. Data is spread amongst the modules in an alternating pattern, potentially tripling available memory bandwidth for the same amount of data, as opposed to storing it all on one module.

The architecture can only be used when all three, or a multiple of three, memory modules are identical in capacity and speed, and are placed in three-channel slots. When two memory modules are installed, the architecture will operate in dual-channel architecture mode.<ref name="support.intel.com">{{Citation|title=Desktop Boards – Triple Memory Modules|url=http://support.intel.com/support/motherboards/desktop/sb/CS-011965.htm#triple|publisher=Intel|access-date=2011-10-01|archive-date=2009-03-08|archive-url=https://web.archive.org/web/20090308093852/http://support.intel.com/support/motherboards/desktop/sb/CS-011965.htm#triple|url-status=dead}}, [https://www.intel.com/content/www/us/en/support/articles/000005657/boards-and-kits.html Single- and Multichannel Memory Modes]</ref>

=== Supporting processors ===

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== Octa-channel architecture ==

[[File:HP Z6 (极客湾Geekerwan) 029.png|thumb|alt=The image shows 4 RAM slots on the left and 4 on the right. The image center shows the socket and the AMD Ryzen Threadripper Pro 7995WX|Octa-channel setup with an AMD Ryzen Threadripper Pro 7995WX]]

Supported by [[Cavium#ThunderX2_SoCs|Cavium ThunderX2]] server processors, AMD's server processors from their [[Epyc]] platform, and the [[Threadripper|Threadripper PRO]] lineup of professional-class workstation processors.<ref>{{cite news|last1=Cutress|first1=Ian|title=AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2|url=http://www.anandtech.com/show/11183/amd-prepares-32-core-naples-cpus-for-1p-and-2p-servers-coming-in-q2|archive-url=https://web.archive.org/web/20170307171613/http://www.anandtech.com/show/11183/amd-prepares-32-core-naples-cpus-for-1p-and-2p-servers-coming-in-q2|url-status=dead|archive-date=March 7, 2017|access-date=7 March 2017|publisher=Anandtech|date=7 March 2017}}</ref><ref>{{cite news|last1=Kennedy|first1=Patrick|title=Cavium ThunderX2 and OCP Platform Details|url=https://www.servethehome.com/cavium-thunderx2-ocp-platform-details/|access-date=14 November 2017|publisher=Serve the Home|date=9 November 2017}}</ref><ref>{{Cite web|last=Cutress|first=Ian|date=July 14, 2021|title=AMD Threadripper Pro Review: An Upgrade Over Regular Threadripper?|url=https://www.anandtech.com/show/16805/amd-threadripper-pro-review-an-upgrade-over-regular-threadripper|archive-url=https://web.archive.org/web/20210714131815/https://www.anandtech.com/show/16805/amd-threadripper-pro-review-an-upgrade-over-regular-threadripper|url-status=dead|archive-date=July 14, 2021|access-date=August 18, 2021|website=[[AnandTech]]}}</ref>

== Dodeca-channel architecture ==

Supported by [[Cavium#ThunderX2_SoCs|Cavium ThunderX2]] server processors, AMD's server processors from their [[Epyc]] platform, and the [[Threadripper|Threadripper PRO]] lineup of professional-class workstation processors.<ref>{{cite news|last1=Cutress|first1=Ian|title=AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2|url=http://www.anandtech.com/show/11183/amd-prepares-32-core-naples-cpus-for-1p-and-2p-servers-coming-in-q2|access-date=7 March 2017|publisher=Anandtech|date=7 March 2017}}</ref><ref>{{cite news|last1=Kennedy|first1=Patrick|title=Cavium ThunderX2 and OCP Platform Details|url=https://www.servethehome.com/cavium-thunderx2-ocp-platform-details/|access-date=14 November 2017|publisher=Serve the Home|date=9 November 2017}}</ref><ref>{{Cite web|last=Cutress|first=Ian|date=July 14, 2021|title=AMD Threadripper Pro Review: An Upgrade Over Regular Threadripper?|url=https://www.anandtech.com/show/16805/amd-threadripper-pro-review-an-upgrade-over-regular-threadripper|access-date=August 18, 2021|website=[[AnandTech]]}}</ref>

[[File:AMD Epyc 9754 in Dual-CPU-Socket-Serversystem (极客湾Geekerwan) 07.png|thumb|Server system containing two AMD Epyc CPUs with one dodeca-channel per CPU (768 GiB RAM in total)]]

Dodeca-channel or 12-channel memory architecture is introduced with AMD's server processors from their [[Epyc#Fourth generation Epyc (Genoa, Bergamo and Siena)|Epyc 9004]] platform released in 2022, using [[DDR5]] memory.<ref>{{Cite web |last=Goetting |first=Chris |date=2022-11-10 |title=AMD 4th Gen EPYC 9004 Series Launched: Genoa Tested In A Data Center Benchmark Gauntlet |url=https://hothardware.com/reviews/amd-genoa-data-center-cpu-launch |access-date=2023-12-07 |website=HotHardware |language=en-us}}</ref>

== See also ==

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[[de:Dual Channel]]

[[de:Triple Channel]]

[[es:Arquitectura de memoria multicanal]]

[[es:Doble canal]]

[[it:Dual channel]]

[[ja:デュアルチャネル]]