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{{short description|Form of digital logic family in integrated circuits}}
[[File:Nmos depletion and.svg|right|thumb|A depletion-load and two enhancement-mode NMOS transistor making up [[NAND gate]].]]
In [[integrated circuit]]s, '''depletion-load NMOS''' is a form of digital [[logic family]] that uses only a single power supply voltage, unlike earlier [[NMOS logic|NMOS]] (n-type [[metal-oxide semiconductor]]) logic families that needed
[[Depletion and enhancement modes|Depletion-mode]] n-type [[MOSFET]]s as load transistors allow single voltage operation and achieve greater speed than possible with
The inclusion of depletion-mode NMOS transistors in the [[Semiconductor device fabrication|manufacturing process]] demanded additional manufacturing steps compared to the simpler enhancement-load circuits; this is because depletion-load devices are formed by increasing the amount of [[dopant]] in the load transistors channel region, in order to adjust their [[threshold voltage]]. This is normally performed using [[ion implantation]].
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{{See also|NMOS logic#History}}
In 1965, [[Chih-Tang Sah]], Otto Leistiko and [[Andrew Grove|A.S. Grove]] at [[Fairchild Semiconductor]] fabricated several NMOS devices with channel lengths between [[10 μm process|8{{nbsp}}μm]] and 65{{nbsp}}μm.<ref>{{cite journal |last1=Sah |first1=Chih-Tang |author1-link=Chih-Tang Sah |last2=Leistiko |first2=Otto |last3=Grove |first3=A. S. |title=Electron and hole mobilities in inversion layers on thermally oxidized silicon surfaces |journal=[[IEEE Transactions on Electron Devices]] |date=May 1965 |volume=12 |issue=5 |pages=248–254 |doi=10.1109/T-ED.1965.15489 |bibcode=1965ITED...12..248L |url=https://pdfslide.net/documents/electron-and-hole-mobilities-in-inversion-layers-on-thermally-oxidized-silicon-57e531d33262d.html|url-access=subscription }}</ref> Dale L. Critchlow and [[Robert H. Dennard]] at [[IBM]] also fabricated NMOS devices in the 1960s. The first IBM NMOS product was a [[memory chip]] with 1{{nbsp}}[[kibibit|kb]] data and 50{{ndash}}100 [[nanosecond|ns]] [[access time]], which entered large-scale manufacturing in the early 1970s. This led to MOS [[semiconductor memory]] replacing earlier [[bipolar junction transistor|bipolar]] and [[ferrite-core memory]] technologies in the 1970s.<ref>{{cite journal |last1=Critchlow |first1=D. L. |title=Recollections on MOSFET Scaling |journal=IEEE Solid-State Circuits Society Newsletter |date=2007 |volume=12 |issue=1 |pages=19–22 |doi=10.1109/N-SSC.2007.4785536 |doi-access=free }}</ref>
===Silicon gate===
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There are a couple of drawbacks associated with PMOS: The [[electron hole]]s that are the charge (current) carriers in PMOS transistors have lower mobility than the [[electron]]s that are the charge carriers in NMOS transistors (a ratio of approximately 2.5), furthermore PMOS circuits do not interface easily with low voltage positive logic such as [[Diode–transistor logic|DTL-logic]] and [[Transistor–transistor logic|TTL-logic]] (the 7400-series). However, PMOS transistors are relatively easy to make and were therefore developed first — ionic contamination of the gate oxide from [[Etching (microfabrication)|etching chemical]]s and other sources can very easily prevent (the [[electron]] based) NMOS transistors from switching off, while the effect in (the [[electron-hole]] based) PMOS transistors is much less severe. Fabrication of NMOS transistors therefore has to be many times cleaner than bipolar processing in order to produce working devices.
Early work on NMOS integrated circuit (IC) technology was presented in a brief [[IBM]] paper at [[ISSCC]] in 1969. [[Hewlett-Packard]] then started to develop NMOS IC technology to get the promising speed and easy interfacing for its calculator business.<ref>These calculators (like the [[Datapoint 2200]] and others) were in many ways small [[desktop computer]]s, but preceded the [[
The production-ready NMOS process enabled HP to develop the industry’s first 4-kbit IC [[Read-only memory|ROM]]. [[Motorola]] eventually served as a second source for these products and so became one of the first commercial semiconductor vendors to master the NMOS process, thanks to Hewlett-Packard. A while later, the startup company [[Intel]] announced a 1-kbit pMOS DRAM, called ''1102'', developed as a custom product for [[Honeywell]] (an attempt to replace magnetic [[core memory]] in their [[mainframe computer]]s). HP’s calculator engineers, who wanted a similar but more robust product for the [[HP 9800 series|9800 series]] calculators, contributed IC fabrication experience from their 4-kbit ROM project to help improve Intel DRAM’s reliability, operating-voltage, and temperature range. These efforts contributed to the heavily enhanced [[Intel 1103]] 1-kbit pMOS DRAM, which was the world’s first commercially available [[Dynamic random-access memory|DRAM]] IC. It was formally introduced in October 1970, and became Intel’s first really successful product.<ref>{{cite web|url=http://www.hp9825.com/html/prologues.html |title=Prologues |publisher=Hp9825.com |date= |accessdate=2022-03-15}}</ref>
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===Intel HMOS===
{{redirect|HMOS|operating system|HarmonyOS}}
Intel's own depletion-load NMOS process was known as '''HMOS''', for ''High density, short channel MOS''. The first version was introduced in late 1976 and first used for their [[static RAM]] products,<ref>{{cite journal |first1=A.M. |last1=Volk |first2=P.A. |last2=Stoll |first3=P. |last3=Metrovich |title=Recollections of Early Chip Development at Intel |journal=Intel Technology Journal |volume=5 |issue=Q1 |pages= |date=2001 |url=https://www.intel.com/content/dam/www/public/us/en/documents/research/2001-vol05-iss-1-intel-technology-journal.pdf}}</ref> it was soon being used for faster and/or less power hungry versions of the 8085, 8086, and other chips.
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