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Atmel AVR instruction set: Difference between revisions

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{{Short description|Microcontroller machine language}}
{{multiple issues|
{{lead too short|date=June 2014}}
{{manual|date=June 2014}}
}}
{{main article|Atmel AVR}}
 
Line 8 ⟶ 5:
 
== Processor registers ==
{| class="infobox" style="font-size:88%;width:38em;"
|-
|+ Atmel AVR registers
|-
|
{| style="font-size:88%;"
|-
| style="width:10px; text-align:center;"| <sup>2</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>2</sup><sub>0</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>9</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>8</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>6</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>0</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>9</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>8</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>6</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>0</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|-
|colspan="21" | '''General purpose registers''' <br />
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R1
| style="text-align:center;" colspan="8"| R0
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R3
| style="text-align:center;" colspan="8"| R2
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R5
| style="text-align:center;" colspan="8"| R4
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R7
| style="text-align:center;" colspan="8"| R6
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R9
| style="text-align:center;" colspan="8"| R8
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R11
| style="text-align:center;" colspan="8"| R10
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R13
| style="text-align:center;" colspan="8"| R12
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R15
| style="text-align:center;" colspan="8"| R14
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R17
| style="text-align:center;" colspan="8"| R16
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R19
| style="text-align:center;" colspan="8"| R18
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R21
| style="text-align:center;" colspan="8"| R20
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R23
| style="text-align:center;" colspan="8"| R22
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R25
| style="text-align:center;" colspan="8"| R24
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R27
| style="text-align:center;" colspan="8"| R26
| style="background:white; color:black;"| '''X''' (pointer)
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R29
| style="text-align:center;" colspan="8"| R28
| style="background:white; color:black;"| '''Y''' (pointer)
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R31
| style="text-align:center;" colspan="8"| R30
| style="background:white; color:black;"| '''Z''' (pointer)
|-
|colspan="21" | '''Stack pointer''' <br />
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| SPH
| style="text-align:center;" colspan="8"| SPL
| style="background:white; color:black;"| [[Call stack|'''S'''tack '''P'''ointer]]
|-
|colspan="21" | '''Program counter''' <br />
|- style="background:silver;color:black"
| style="text-align:center;" colspan="22"| PC
| style="background:white; color:black;"| [[Program counter|'''P'''rogram '''C'''ounter]]
|-
|colspan="21" | '''Extended memory''' <br />
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="14"| &nbsp;
| style="text-align:center;" colspan="8"| RAMPD
| style="background:white; color:black;"| Extended direct
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="14"| &nbsp;
| style="text-align:center;" colspan="8"| RAMPX
| style="background:white; color:black;"| Extended X
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="14"| &nbsp;
| style="text-align:center;" colspan="8"| RAMPY
| style="background:white; color:black;"| Extended Y
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="14"| &nbsp;
| style="text-align:center;" colspan="8"| RAMPZ
| style="background:white; color:black;"| Extended Z
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="14"| &nbsp;
| style="text-align:center;" colspan="8"| EIND
| style="background:white; color:black;"| Extended indirect
|-
|colspan="21" | '''Status register'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="14"| &nbsp;
| style="text-align:center;"| [[Interrupt flag|I]]
| style="text-align:center;"| T
| style="text-align:center;"| [[Half-carry flag|H]]
| style="text-align:center;"| [[Sign flag|S]]
| style="text-align:center;"| [[Overflow flag|V]]
| style="text-align:center;"| [[Sign flag|N]]
| style="text-align:center;"| [[Zero flag|Z]]
| style="text-align:center;"| [[Carry flag|C]]
| style="background:white; color:black" | SREG
|}
|}
There are 32 general-purpose 8-bit registers, R0–R31. All arithmetic and logic operations operate on those registers; only load and store instructions access RAM.
 
Line 21 ⟶ 166:
* RAMPX, RAMPY, RAMPZ, RAMPD and EIND: 8-bit segment registers that are prepended to 16-bit addresses in order to form 24-bit addresses; only available in parts with large address spaces.
 
===Status bitsregister===
The status register bits are:
#<li value=0> C [[Carry flag]]. This is a borrow flag on subtracts.</li>
#<li value=0> C [[Carry flag]]. This is a borrow flag on subtracts. The <code>INC</code> and <code>DEC</code> instructions do ''not'' modify the carry flag, so they may be used to loop over multi-byte arithmetic operations.<ref name="isa_manual">{{cite web |url=http://ww1.microchip.com/downloads/en/devicedoc/atmel-0856-avr-instruction-set-manual.pdf |title=AVR Instruction Set Manual |date=November 2016 |publisher=Atmel |id=Atmel-0856L}}</ref></li>
# Z [[Zero flag]]. Set to 1 when an arithmetic result is zero, and cleared when it is non-zero.
# N [[Negative flag]]. Set to a copy of the most significant bit of an arithmetic result.
# V [[Overflow flag]]. Set in case of two's complement overflow.
# S Sign flag. Unique to AVR, this is always N⊕VN[[Exclusive or|⊕]]V, and shows the true sign of a comparison.
# H [[Half-carry flag]]. This is an internal carry from additions and is used to support [[Binary-coded decimal|BCD]] arithmetic.
# T Bit copy. Special bit load and bit store instructions use this bit.
# I [[Interrupt flag]]. Set when interrupts are enabled.
 
There are two special cases which exist to facilitate multi-byte arithmetic:
* The <code>INC</code> and <code>DEC</code> instructions do ''not'' modify the carry flag, so they may be used to loop over [[arbitrary-precision arithmetic]] operands.<ref name="isa_manual">{{cite web |url=https://ww1.microchip.com/downloads/en/DeviceDoc/AVR-InstructionSet-Manual-DS40002198.pdf |title=AVR Instruction Set Manual |date=November 2016 |publisher=Atmel |id=Atmel-0856L}}</ref>{{Rp|84,101}}
* The <code>CPC</code>, <code>SBC</code> and <code>SBCI</code> (compare/subtract with carry) instructions do ''not'' set the Z flag when the result is zero, but only clear it if the result is non-zero.{{r|isa_manual|p=79,147,149}} For ''fixed'' precision multi-byte comparisons, implemented with an [[Loop unrolling|unrolled]] <code>CP; CPC; CPC; CPC</code> sequence, this produces a zero flag which is set only if the ''entire'' difference is zero.
 
== Addressing ==
Line 42 ⟶ 191:
* The general purpose registers, the status register and some I/O registers are bit-addressable, with bit 0 being the least significant and bit 7 the most significant.
 
The first 64 I/O registers are accessible through both the I/O and the data address space. They have therefore two different addresses. These are usually written as "{{mono|0x00}} ({{mono|0x20}})" through "{{mono|0x3F}} ({{mono|0x5F}})", where the first item is the I/O address and the second, in parentheses, the data address.
 
The special-purpose CPU registers, with the exception of PC, can be accessed as I/O registers. Some registers (RAMPX, RAMPY) may not be present on machines with less than 64 [[KiB]] of addressable memory.
Line 49 ⟶ 198:
! Register !! I/O address !! Data address
|-
| SREG || {{mono|0x3F}} || {{mono|0x5F}}
|-
| SP || {{mono|0x3E}}:{{mono|0x3D}} || {{mono|0x5E}}:{{mono|0x5D}}
|-
| EIND || {{mono|0x3C}} || {{mono|0x5C}}
|-
| RAMPZ || {{mono|0x3B}} || {{mono|0x5B}}
|-
| RAMPY || {{mono|0x3A}} || {{mono|0x5A}}
|-
| RAMPX || {{mono|0x39}} || {{mono|0x59}}
|-
| RAMPD || {{mono|0x38}} || {{mono|0x58}}
|}
 
Line 69 ⟶ 218:
! Data address !! I/O address !! Contents
|-
| {{mono|0x0000}} – {{mono|0x001F}} || || Registers R0 – R31
|-
| {{mono|0x0020}} – {{mono|0x003F}} || {{mono|0x00}} – {{mono|0x1F}} || I/O registers (bit-addressable)
|-
| {{mono|0x0040}} – {{mono|0x005F}} || {{mono|0x20}} – {{mono|0x3F}} || I/O registers (not bit-addressable)
|-
| {{mono|0x0060}} – {{mono|0x00FF}} || || Extended I/O registers (memory-mapped I/O only)
|-
| {{mono|0x0100}} – {{mono|RAMEND}} || || Internal SRAM
|}
 
where RAMEND is the last RAM address. In parts lacking extended I/O the RAM would start at {{mono|0x0060}}.
 
== Instruction timing ==
Line 107 ⟶ 256:
* D16 is a 16-bit data address covering 64&nbsp;[[KiB]]; in parts with more than 64&nbsp;KiB data space, the contents of the RAMPD segment register is prepended
* P22 is a 22-bit program address covering 2<sup>22</sup> 16-bit words (i.e. 8&nbsp;[[MiB]])
* S7 and S12 are 7-bit (resp.and 12-bit) ''signed'' displacements, in units of words, relative to the program address stored in the program counter
 
{| class="wikitable"
|+ AVR instruction set
|-
Line 116 ⟶ 265:
! Transfer
! Jump
|-
! Branch
|valign=top rowspan=5|{{#tag:syntaxhighlight|
ADD Rd, Rr
ADC Rd, Rr
ADIW Rp+1:Rp, K6
 
SUB Rd, Rr
SUBI Rdh, K8
SBC Rd, Rr
SBCI Rdh, K8
SBIW Rp+1:Rp, K6
 
INC Rd
DEC Rd
 
AND Rd, Rr
ANDI Rdh, K8
OR Rd, Rr
ORI Rdh, K8
<!--
<S> CLR Rd </S> (EOR)
<S> SER Rdh </S> (LDI)
<S> SBR Rdh, K8 </S> (ORI)
<S> CBR Rdh, K8 </S> (ANDI)
<S> TST Rd </S> (AND)
!-->
COM Rd
NEG Rd
CP Rd, Rr
CPC Rd, Rr
CPI Rdh, K8
SWAP Rd
<!--
<S> LSL Rd </S> (ADD)
<S> ROL Rd </S> (ADC)
!-->
LSR Rd
ROR Rd
ASR Rd
 
MUL Rd, Rr
MULS Rdh, Rrh
MULSU Rdq, Rrq
FMUL Rdq, Rrq
FMULS Rdq, Rrq
FMULSU Rdq, Rrq
|lang="nasm"|style=font-size:95%}}
|valign=top rowspan=5|{{#tag:syntaxhighlight|
BSET s
BCLR s
SBI IO5, b
CBI IO5, b
BST Rd, b
BLD Rd, b
 
NOP
BREAK
SLEEP
WDR|lang="nasm"|style=font-size:95%}}
|valign=top rowspan=5|{{#tag:syntaxhighlight|
MOV Rd, Rr
MOVW Rd+1:Rd, Rr+1:Rr
 
IN Rd, IO6
OUT IO6, Rr
 
PUSH Rr
POP Rr
 
LDI Rdh, K8
LDS Rd, D16
 
LD Rd, X
LDD Rd, YZ+K6
LD Rd, -XYZ
LD Rd, XYZ+
 
STS D16, Rr
 
ST X, Rr
STD YZ+K6, Rr
ST -XYZ, Rr
ST XYZ+, Rr
 
LPM
LPM Rd, Z
LPM Rd, Z+
ELPM
ELPM Rd, Z
ELPM Rd, Z+
 
SPM|lang="nasm"|style=font-size:95%}}
|valign=top|{{#tag:syntaxhighlight|
RJMP S12
IJMP
EIJMP
JMP P22|lang="nasm"|style=font-size:95%}}
|-
! Call
|-
|valign=top|{{sxhl|2=nasm#tag:syntaxhighlight|
RCALL S12
ADD Rd, Rr
ICALL
ADC Rd, Rr
EICALL
ADIW Rp+1:Rp, K6
CALL P22
 
SUB Rd, Rr
RET
SUBI Rdh, K8
RETI|lang="nasm"|style=font-size:95%}}
SBC Rd, Rr
|-
SBCI Rdh, K8
! Branch
SBIW Rp+1:Rp, K6
|-
|valign=top|{{#tag:syntaxhighlight|
INC Rd
CPSE Rd, Rr
DEC Rd
 
SBRC Rr, b
AND Rd, Rr
SBRS Rr, b
ANDI Rdh, K8
 
OR Rd, Rr
SBIC IO5, b
ORI Rdh, K8
SBIS IO5, b
}} <!--
 
<S> CLR Rd </S> (EOR)
BRBC s, S7
<S> SER Rdh </S> (LDI)
BRBS s, S7|lang="nasm"|style=font-size:95%}}
<S> SBR Rdh, K8 </S> (ORI)
<S> CBR Rdh, K8 </S> (ANDI)
<S> TST Rd </S> (AND)
!-->
{{sxhl|2=nasm|
COM Rd
NEG Rd
CP Rd, Rr
CPC Rd, Rr
CPI Rdh, K8
SWAP Rd
}} <!--
<S> LSL Rd </S> (ADD) !-->
LSR Rd <!--
<S> ROL Rd </S> (ADC) !-->
ROR Rd
ASR Rd
{{sxhl|2=nasm|
MUL Rd, Rr
MULS Rdh, Rrh
MULSU Rdq, Rrq
FMUL Rdq, Rrq
FMULS Rdq, Rrq
FMULSU Rdq, Rrq
}}
|valign=top|{{sxhl|2=nasm|
BSET s
BCLR s
SBI IO5, b
CBI IO5, b
BST Rd, b
BLD Rd, b
NOP
BREAK
SLEEP
WDR
}}
|valign=top|{{sxhl|2=nasm|
MOV Rd, Rr
MOVW Rd+1:Rd, Rr+1:Rr
IN Rd, IO6
OUT IO6, Rr
PUSH Rr
POP Rr
LDI Rdh, K8
LDS Rd, D16
LD Rd, X
LDD Rd, YZ+K6
LD Rd, -XYZ
LD Rd, XYZ+
STS D16, Rr
ST X, Rr
STD YZ+K6, Rr
ST -XYZ, Rr
ST XYZ+, Rr
LPM
LPM Rd, Z
LPM Rd, Z+
ELPM
ELPM Rd, Z
ELPM Rd, Z+
SPM
}}
|valign=top|{{sxhl|2=nasm|
RJMP S12
IJMP
EIJMP
JMP P22
}}
|valign=top|{{sxhl|2=nasm|
CPSE Rd, Rr
SBRC Rr, b
SBRS Rr, b
SBIC IO5, b
SBIS IO5, b
BRBC s, S7
BRBS s, S7
}}
|valign=top|{{sxhl|2=nasm|
RCALL S12
ICALL
EICALL
CALL P22
RET
RETI
}}
|}
 
Line 260 ⟶ 408:
#* It is not necessary to explicitly disable interrupts before adjusting the stack pointer registers (SPL and SPH); any write to SPL automatically disables interrupts for 4 clock cycles to give time for SPH to be updated.<!--Technically, until the next I/O write (presumably SPH) or 4 cycles, whichever comes first-->
#* Other multi-byte registers are provided with shadow registers to enable [[Atomic operation|atomic]] read and write. When the lowest-order byte is read, the higher-order bytes are copied to the shadow registers, so reading them later produces a [[snapshot (computer storage)|snapshot]] of the register at the time of the first read. Writes to low-order bytes are buffered until the highest-order byte is written, upon which the entire multi-byte register is updated atomically.
# Later XMEGA cores (specifically, the B, C, and AU models such as the ATxmega16A4U , but ''not'' the earlier A, D and E models such as the ATxmega16D4) add four atomic [[read-modify-write]] instructions: exchange (<code>XCH</code>), load-and-set, load-and-clear, and load-and-toggle.<!--This is from the avr-mcus.def file in the GCC sources, and doesn't match the data sheets, but Atmel redesigned those in 2016 and introduced a lot of errors; many have changelogs mentioning "deleted DES instruction" suggesting they cut & pasted the instruction list and didn't delete unsupported instructions properly. --> These help coordinate with [[direct memory access]] peripherals, notably a [[USB]] controller.
 
Less capable than the "classic" CPU cores are two subsets: the "AVR1" core, and the "AVR tiny". Confusingly, "ATtiny" branded processors have a variety of cores, including AVR1 (ATtiny11, ATtiny28), classic (ATtiny22, ATtiny26), classic+ (ATtiny24) and AVRtiny (ATtiny20, ATtiny40).
Line 290 ⟶ 438:
Architectures other than AVR1 are named according to avr-libc conventions.<ref name="avr-libc-gnu-archname">{{cite web|title=Using the GNU tools|url=https://www.nongnu.org/avr-libc/user-manual/using_tools.html|website=AVR Libc Manual|accessdate=6 May 2018}}</ref>
 
{| class="wikitable plainlist"
! Family
! Members
Line 297 ⟶ 445:
! Transfers
! Bit-Wise
|- style="vertical-align:top;"
|- {{ts|vtp}}
! scope=row | Minimal AVR1 Core
| {{ublist|AT90S1200|ATtiny11|ATtiny12|ATtiny15|ATtiny28}}
| {{ublist|item_style=font-family:monospace;|ADD (LSL)|ADC (ROL)|SUB |SUBI|SBC|SBCI|AND (TST)|ANDI (CBR)|OR|ORI (SBR)|EOR (CLR)|COM|NEG|SBR|CBR|INC|DEC|TST|CLR|SER}}
| {{ublist|item_style=font-family:monospace;|RJMP|RCALL|RET|RETI|CPSE|CP|CPC|CPI|SBRC|SBRS|SBIC|SBIS|BRBS (BRCS,&ZeroWidthSpace;BRLO,&ZeroWidthSpace;BREQ,&ZeroWidthSpace;BRMI,&ZeroWidthSpace;BRVS,&ZeroWidthSpace;BRLT,&ZeroWidthSpace;BRHS,&ZeroWidthSpace;BRTS,&ZeroWidthSpace;BRIE)|BRBC|BREQ|BRNE|BRCS| (BRCC|,&ZeroWidthSpace;BRSH|BRLO|BRMI|,&ZeroWidthSpace;BRNE,&ZeroWidthSpace;BRPL|,&ZeroWidthSpace;BRVC,&ZeroWidthSpace;BRGE|BRLT|BRHS|,&ZeroWidthSpace;BRHC|BRTS|,&ZeroWidthSpace;BRTC|BRVS|BRVC|BRIE|,&ZeroWidthSpace;BRID)}}
| {{ublist|item_style=font-family:monospace;|LD|ST|MOV|LDI (SER)|IN|OUT|{{mono|LPM}} (not in AT90S1200)|item_style7item7_style=font-family:unset;}}
| {{ublist|item_style=font-family:monospace;|SBI|CBI|LSL|LSR|ROL|ROR|ASR|SWAP|BSET (SEC, SEZ, SEN, SEV, SES, SEH, SET, SEI)|BCLR|BST|BLD|SEC| (CLC|SEN|, CLZ, CLN|SEZ|CLZ|SEI|CLI|SES|, CLV, CLS|SEV|CLV|SET|, CLH, CLT, CLI)|SEHBST|CLHBLD|NOP|SLEEP|WDR}}
|- style="vertical-align:top;"
|- {{ts|vtp}}
! scope=row | Classic Core up to 8K Program Space ("AVR2")
| {{ublist|AT90S2313|AT90S2323|ATtiny22|AT90S2333|AT90S2343|AT90S4414|AT90S4433|AT90S4434|AT90S8515|AT90C8534|AT90S8535|ATtiny26}}
| new instructions: {{ublist|item_style=font-family:monospace;|ADIW|SBIW}}
| new instructions: {{ublist|item_style=font-family:monospace;|IJMP|ICALL}}
| new instructions: {{ublist|item_style=font-family:monospace;|item_style1item1_style=font-family:unset;|{{mono|LD}} (now 9 modes)|LDD|LDS|item_style4item4_style=font-family:unset;|{{mono|ST}} (9 modes)|STD|STS|PUSH|POP}}
| {{CNone|(nothing new)}}
|- style="vertical-align:top;"
|- {{ts|vtp}}
! scope=row | AVR2, with MOVW and LPM instructions ("AVR2.5")
|{{plainlist|
|
* ATa5272
* ATtiny13/a
Line 332 ⟶ 480:
* ATtiny87
* ATtiny88
}}
|{{CNone|(nothing new)}}
|{{CNone|(nothing new)}}
|new instructions:
{{plainlist|
* {{mono|MOVW}}
* {{mono|LPM (Rx, Z[+])}}
* {{mono|SPM}}
}}
|{{CNone|(nothing new)}}
|- style="vertical-align:top;"
|- {{ts|vtp}}
! scope=row | Classic Core with up to 128K ("AVR3")
| {{ublist|ATmega103|ATmega603|AT43USB320|AT76C711}}
Line 345 ⟶ 497:
| new instructions:{{ublist|{{mono|ELPM}} (in "AVR3.1")}}
| {{CNone|(nothing new)}}
|- style="vertical-align:top;"
|- {{ts|vtp}}
! scope=row | Enhanced Core with up to 8K ("AVR4")
| {{ublist|ATmega8|ATmega83|ATmega85|ATmega8515}}
| new instructions:{{ublist|item_style=font-family:monospace;|MUL|MULS|MULSU|FMUL|FMULS|FMULSU<ref> Atmel. [http://www.atmel.com/Images/doc1631.pdf Application Note "AVR201: Using the AVR Hardware Multiplier"]. 2002. quote: "The megaAVR is a series of new devices in the AVR RISC Microcontroller family that includes, among other new enhancements, a hardware multiplier."</ref>}}
| {{CNone|(nothing new)}}
| new instructions:{{ublist|{{mono|MOVW}}|{{mono|LPM}} (3 modes)|{{mono|SPM}}}}
| {{CNone|(nothing new)}}
|- style="vertical-align:top;"
|- {{ts|vtp}}
! scope=row | Enhanced Core with up to 128K ("AVR5", "AVR5.1")
| {{ublist|ATmega16|ATmega161|ATmega163|ATmega32|ATmega323|ATmega64|ATmega128|AT43USB355|[[Atmel At94k|AT94 (FPSLIC)]]|AT90CAN series|AT90PWM series|ATmega48|[[ATmega88]]|ATmega168|ATmega162|ATmega164|ATmega324|[[ATmega328]]|ATmega644|ATmega165|ATmega169|ATmega325|ATmega3250|ATmega645|ATmega6450|ATmega406}}
Line 359 ⟶ 511:
| {{CNone|(nothing new)}}
| new instructions:{{ublist|item_style=font-family:monospace;|BREAK}}
|- style="vertical-align:top;"
|- {{ts|vtp}}
! scope=row | Enhanced Core with up to 4M ("AVR5" and "AVR6")
| {{ublist|ATmega640|ATmega1280|ATmega1281|ATmega2560|ATmega2561}}
Line 366 ⟶ 518:
| {{CNone|(nothing new)}}
| {{CNone|(nothing new)}}
|- style="vertical-align:top;"
|- {{ts|vtp}}
! scope=row | XMEGA Core ("avrxmega" 2-6)
| ATxmega series
Line 373 ⟶ 525:
| new instructions (from second revision silicon - AU,B,C parts) {{ublist|item_style=font-family:monospace;|XCH|LAS|LAC|LAT}}
| {{CNone|(nothing new)}}
|- style="vertical-align:top;"
|- {{ts|vtp}}
! scope=row | Reduced AVRtiny Core ("avrtiny10")
| {{ublist|ATtiny40|ATtiny20|ATtiny10|ATtiny9|ATtiny5|ATtiny4}}
| (Identical to minimal core, except for reduced CPU register set{{note label|reduced|a|a}})
| (Identical to classic core with up to 8K, except for reduced CPU register set{{note label|reduced|a|a}})
| Identical to classic core with up to 8K, with the following exceptions:{{aligned table|cols=2|col1style=font-family:monospace;|LPM|(removed)|LDD|(removed)|STD|(removed)|LD|(also accesses program memory)|LDS
STS|(differentaccess bitis pattern)|STS|(differentlimited to the first 128 bytes bitof patternSRAM)||Reduced CPU register set{{note label|reduced|a|a}}}}
| (Identical to enhanced core with up to 128K, except for reduced CPU register set{{note label|reduced|a|a}})
|}
Line 385 ⟶ 538:
== Instruction encoding ==
Bit assignments:
* {{not a typo|rrrrr / ddddd}} = Source/destination register
* {{not a typo|rrrr / dddd}} = Source/destination register (R16–R31)
* {{not a typo|rrr / ddd}} = Source/destination register (R16–R23)
* RRRR / DDDD = Source/destination register pair (R1:R0–R31:R30)
* {{not a typo|ddddd}} = Destination register
* {{not a typo|dddd}} = Destination register (R16–R31)
* {{not a typo|ddd}} = Destination register (R16–R23)
* DDDD = Destination register pair (R1:R0–R31:R30)
* pp = Register pair, W, X, Y or Z
* y = Y/Z register pair bit (0=Z, 1=Y)
* u = FMUL(SFMULS(U)) signedunsigned withbit (0=FMULS signed or, 1=FMULSU unsigned)
* s = Store/load bit (0=loadLD Rd,mem, 1=storeST mem,Rd)
* c = Call/jump (0=jump, 1=call)
* cy = With carry (0=without carry, 1=with carry)
Line 409 ⟶ 558:
* {{not a typo|KKKKKKKK}} = 8-bit constant
 
The Atmel AVR uses many split fields, where bits are not contiguous in the instruction word. The load/storemost withcommonly offsetencountered instructions areis the 5-bit source register field in bits 9 and 3–0. The most extreme example whereis the load/store with offset instructions, which break a 6-bit offset is broken into three pieces.
 
{|class="wikitable" style="text-align:center"
Line 435 ⟶ 584:
| 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 ||colspan=3| d d d || u ||colspan=3| r r r ||align=left| FMULS(U) Rd,Rr
|-
|colspan=17|
! 0 || 0 ||colspan=4| opcode || r ||colspan=5| d d d d d ||colspan=4| r r r r ||align=left| 2-operand instructions
|-
! 0 || 0 ||colspan=4| opcode || r ||colspan=5| d d d d d ||colspan=4| r r r r ||align=left| Two-operand instructions
|-
| 0 || 0 || 0 || c̅y̅ || 0 || 1 || r ||colspan=5| d d d d d ||colspan=4| r r r r ||align=left| CPC/CP Rd,Rr
Line 473 ⟶ 624:
! 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d ||colspan=4| opcode ||align=left| Load/store operations
|-
| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || 0 || 0 || 0 || 0 ||align=left rowspan=2| LDS rdRd,i/STS i,rdRd
|-
| colspan=16| 16-Bit immediate SRAM address i
|-bgcolor=lightgray
| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || 1 || 0 || 0 || 0 || (reserved)
|-
| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || y || 0 || 0 || 1 ||align=left| LD/ST Rd through Z+/Y+
|-
| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || y || 0 || 1 || 0 ||align=left| LD/ST Rd through &minus;Z/&minus;Y
|-bgcolor=lightgray
| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || y || 0 || 1 || 1 || (reserved)
|-
| 1 || 0 || 0 || 1 || 0 || 0 || 0 ||colspan=5| d d d d d || 0 || 1 || q || 0 ||align=left| LPM/ELPM Rd,Z
Line 533 ⟶ 688:
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 0 || 0 || 0 || 1 || 1 || 0 || 0 || 0 ||align=left| RETI
|-bgcolor=lightgray
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 0 ||colspan=2| 0 ||≠ 100 || x || 1 || 0 || 0 || 0 || (reserved)
|-bgcolor=lightgray
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 0 || 1 || x || x || 1 || 0 || 0 || 0 || (reserved)
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 1 || 0 || 0 || 0 || 1 || 0 || 0 || 0 ||align=left| SLEEP
Line 554 ⟶ 707:
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || c || 0 || 0 || 0 || e || 1 || 0 || 0 || 1 ||align=left| Indirect jump/call to Z or EIND:Z
|-bgcolor=lightgray
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || c ||colspan=3| ≠ 000 || e || 1 || 0 || 0 || 1 || (reserved)
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 ||colspan=5| d d d d d || 1 || 0 || 1 || 0 ||align=left| DEC Rd
Line 601 ⟶ 756:
**[https://web.archive.org/web/20050714015338/http://users.rcn.com/rneswold/avr/ A GNU Development Environment for the AVR Microcontroller] by Rich Neswold
**[https://gcc.gnu.org/onlinedocs/gcc-3.3.5/gcc/AVR-Options.html AVR Options] in GCC-AVR
*[http://starlo.org/blake/boardmicro/ AVR Instruction Set Simulator (ATmega32u4 for GCC Intel Hex Files)]
*[https://github.com/avr-llvm/architecture/blob/master/Instructions/inheritance.md AVR Instruction Set Inheritance] (LLVM note), based on this page and GCC & Binutils code
 
{{DEFAULTSORT:Atmel Avr Instruction Set}}
[[Category:Atmel microcontrollers]]
Retrieved from "https://en.wikipedia.org/wiki/Atmel_AVR_instruction_set"