Extensible Host Controller Interface: Difference between revisions

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'''eXtensible Host Controller Interface (xHCI)''' is a computer interface specification that defines a register-level description of a Host Controller for Universal Serial bus (USB) that is capable of interfacing to USB 1.0, 2.0, and 3.0 compatible devices. The specification is also referred to as the USB 3.0 Host Controller spec.

{{short description|Computer interface specification}}

== Architectural Goals ==

{{More footnotes|date=April 2014}}

The xHCI is a radical break from the previous generations of USB host controller interface architectures (i.e. the Open Host Controller Interface - OHCI, the Universal Host Controller Interface - UHCI, and the Enhanced Host Controller Interface - EHCI) on many counts.

The '''eXtensible Host Controller Interface''' ('''xHCI''') is a technical specification that provides a detailed framework for the functioning of a computer's [[host controller]] for [[Universal Serial Bus]] (USB). Known alternately as the [[USB 3.0]] host controller specification, xHCI is designed to be backward compatible, supporting a wide range of USB devices from older USB 1.x to the more recent USB 3.x versions.

Distinct from its predecessors, the [[Open Host Controller Interface]] (OHCI), the [[Universal Host Controller Interface]] (UHCI) and the [[Host controller interface (USB, Firewire)#EHCI|Enhanced Host Controller Interface]] (EHCI), xHCI offers several technological improvements. Specifically, it is designed to handle multiple data transfer speeds (low, full, high, and SuperSpeed) within a single unified standard. This makes it more efficient in managing computational and power resources, a feature particularly beneficial for mobile devices with limited power capabilities like tablets and smartphones. Additionally, xHCI simplifies the architecture needed to support a mixture of low-speed and high-speed devices, which streamlines the development of drivers and system software.

xHCI marks a significant improvement over its predecessors, the Open Host Controller Interface (OHCI), the Universal Host Controller Interface (UHCI) and the Enhanced Host Controller Interface (EHCI), in several key ways:

# '''Multi-Speed Support''': Unlike OHCI, UHCI and EHCI, which were limited to specific USB speeds, xHCI is capable of managing multiple data transfer speeds—low, full, high, and SuperSpeed—under a single standard. This eliminates the need for multiple host controllers or complex switching mechanisms when dealing with various types of USB devices, thereby improving efficiency.

# '''Power Management''': xHCI includes advanced power management features that allow for selective suspension of USB devices and more granular power distribution. This is especially beneficial for mobile devices with limited battery life, such as tablets and laptops, as it helps to maximize power utilization and extend battery life.

# '''Streamlined Architecture''': xHCI's architecture is designed to be simpler and more straightforward, reducing the complexity of driver development. In older architectures like OHCI, UHCI and EHCI, supporting a mix of low-speed and high-speed devices required complicated algorithms and multiple transaction translators. xHCI simplifies this by integrating these functions into the host controller itself, thus easing the burden on system software and driver developers.

By enhancing support for multiple speeds, optimizing power management, and simplifying the underlying architecture, xHCI serves as a more efficient and unified standard for USB host controllers.

== Architectural Goalsgoals ==

The xHCI is a radical break from the previous generations of USB host controller interface architectures (i.e. the [[Open Host Controller Interface]] - (OHCI), the [[Universal Host Controller Interface]] - (UHCI), and the [[Enhanced Host Controller Interface]] - (EHCI)) on many counts.

Following are the key goals of the xHCI architecture:

* Efficient operation – idle power and performance better than legacy USB host controller architectures.

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* Minimize host memory accesses, fully eliminating them when USB devices are idle

* Eliminate register writes and minimize register reads for normal data transfers

* Eliminate the “Companion"Companion Controller”Controller" model

* Enable hardware “fail"fail-over”over" modes in system resource constrained situations so devices are still accessible, but perhaps at less optimal power/performance point

* Provide the ability for different markets to differentiate hardware capabilities, e.g. target host controller power, performance and cost trade-offs for specific markets

* Define an extensible architecture that provides an easy path for new USB specifications and technologies, such as higher bandwidth interfaces, optical transmission medium, etc., without requiring the definition of yet another USB host controller interface

== Architectural Detailsdetails ==

=== Support for all Speedsspeeds ===

The OHCI and UHCI controllers support only USB 1 speed devices (1.5 Mb/s and 12 Mb/s), and the EHCI only supports USB 2 devices (480 Mb/s).

* The xHCIOHCI architectureand wasUHCI designed tocontrollers support allonly USB speeds,1 includingspeed SuperSpeeddevices (1.5 Mbit/s and Gb12 Mbit/s), and futurethe speeds,EHCI underonly asupports singleUSB driver2 stackdevices (480 Mbit/s).

=== Power Efficiency ===

The xHCI architecture was designed to support all USB speeds, including SuperSpeed (5 Gbit/s) and future speeds, under a single driver stack.

When USB was originally developed in 1995, it was targeted at desktop platforms to stem the proliferation of connectors that were appearing on PCs, e.g. PS-2, Serial Port, Parallel Port, Game Port, etc., and host power consumption was not an important consideration at the time. Since then, mobile platforms have become the platform of choice, and their batteries have made power consumption a key consideration. The architectures of the legacy USB host controllers (OHCI, UHCI, and EHCI) were very similar in that the “schedule” for the transactions to be performed on the USB were built by software in host memory, and the host controller hardware would continuously read the schedules to determine what transactions needed to be driven on the USB, and when, even if no data was moved.

=== Power Efficiencyefficiency ===

When USB was originally developed in 1995, it was targeted at desktop platforms to stem the proliferation of connectors that were appearing on PCs, e.g. [[PS-/2 connector|PS/2]], Serial[[serial Portport]], Parallel[[parallel Portport]], Game[[game Portport]], etc., and host power consumption was not an important consideration at the time. Since then, mobile platforms have become the platform of choice, and their batteries have made power consumption a key consideration. The architectures of the legacy USB host controllers (OHCI, UHCI, and EHCI) were very similar in that the “schedule”"schedule" for the transactions to be performed on the USB were built by software in host memory, and the host controller hardware would continuously read the schedules to determine what transactions needed to be driven on the USB, and when, even if no data was moved. Additionally, in the case of reads from the device, the device was polled each schedule interval, even if there was no data to read.

* The xHCI eliminates host memory based USB transaction schedules, enabling zero host memory activity when there is no USB data movement.

* The xHCI reduces the need for periodic device polling by allowing a USB 3.0 or later device to notify the host controller when it has data available to read, and moves the management of polling USB 2.0 and 1.1 devices that use interrupt transactions from the CPU-driven USB driver to the USB host controller. EHCI, OHCI, and UHCI host controllers would automatically handle polling for the CPU if there are no changes that need to be made and if no device has any interrupts to send but they all rely on the CPU to set the schedule up for the controllers.<ref>{{cite web|url=http://ftp.netbsd.org/pub/NetBSD/misc/blymn/uhci11d.pdf |title=UHCI11D.DOC |website=Ftp.netbsd.org |date= |accessdate=2017-01-09}}</ref><ref>{{cite web |url=http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/ehci-specification-for-usb.pdf |title=Archived copy |accessdate=2014-07-02 |url-status=dead |archiveurl=https://web.archive.org/web/20150810175253/http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/ehci-specification-for-usb.pdf |archivedate=2015-08-10 }}</ref><ref>[ftp://ftp.compaq.com/pub/supportinformation/papers/hcir1_0a.pdf]{{dead link|date=May 2025|bot=medic}}{{cbignore|bot=medic}} </ref> If any USB device using interrupt transactions does have data to send, then an xHCI host controller will send an interrupt to notify the CPU that there is a USB interrupt transaction that needs handling. Since the CPU no longer has to manage the polling of the USB bus, it can spend more time in low power states.

* The xHCI alsodoes requiresnot require that implementations provide support for all advanced USB 2 and 3 power management features, including USB 2 LPM, USB 3 U1 and U2 states, HERD, LTM, Function Wake, etc.; but these features are required to realize all of the advantages of xHCI.

=== Virtualization Support ===

Legacy USB host controller architectures exhibit some serious shortcomings when applied to virtualized environments. Legacy USB host controller interfaces define a relatively simple hardware data pump; where critical state related to overall bus management (Bandwidth allocation, Address assignment, etc.) reside in the software of the host controller driver. Trying to apply the standard hardware IO virtualization technique, of replicating IO interface registers, to the legacy USB host controller interface is problematic because critical state that must be managed across Virtual Machines (VMs) is not available to hardware. The xHCI architecture moves the control of this critical state into hardware, enabling USB resource management across VMs. The xHCI virtualization features also provide for:

=== Virtualization Supportsupport ===

* Direct-Assignment of individual USB devices (irrespective of their ___location in the bus topology) to any VM.

Legacy USB host -controller architectures exhibit some serious shortcomings when applied to virtualized environments. Legacy USB host -controller interfaces define a relatively simple hardware data -pump; where critical state related to overall bus -management (Bandwidthbandwidth allocation, Addressaddress assignment, etc.) resideresides in the software of the [[host controller|host-controller]] driver (HCD). Trying to apply the standard hardware IO virtualization technique, of- replicating IOI/O interface registers, - to the legacy USB host controller interface is problematic because critical state that must be managed across Virtual[[virtual Machinesmachine]]s (VMs) is not available to hardware. The xHCI architecture moves the control of this critical state into hardware, enabling USB resource management across VMs. The xHCI virtualization features also provide for:

* Minimizing run-time inter-VM communications.

* Support for native USB device sharing.

* Directdirect-Assignment of individual USB devices (irrespective of their ___location in the bus topology) to any VM.

* Support of PCIe SR-IOV.

* Minimizingminimizing run-time inter-VM communications.

=== Simplified Driver Architecture ===

* Supportsupport for native USB device -sharing.

The EHCI utilizes OHCI or UHCI controllers as “companion controllers”, where USB 2 devices are managed through the EHCI stack, and the port logic of the EHCI allows a USB 1 or 2 device to be routed to a port of a “companion” UHCI or OHCI controller, where the USB 1 and 2 devices are managed through the respective UHCI or OHCI stack. For example, a USB 2 PCIe host controller card that presents 4 USB “Standard A” connectors typically presents one 4-port EHCI and two 2-port OHCI controllers to system software. When a USB 2 device is attached to any of the 4 connectors, the device is managed through one of the 4 root hub ports of the EHCI controller. If a USB 1 device is attached to connectors 1 or 2 they will be routed to the root hub ports of one of the OHCI controllers for management, and USB 1 devices attached to connectors 3 or 4 will be routed to the root hub ports of the other OHCI controller. The EHCI dependence on separate host controllers for USB 1 and 2 devices results in complex interactions and dependencies between the EHCI and OHCI/UHCI drivers.

* support of PCIe SR-IOV ([http://www.intel.com/content/www/us/en/pci-express/pci-sig-sr-iov-primer-sr-iov-technology-paper.html single root I/O virtualization])

=== Simplified Driverdriver Architecturearchitecture ===

The EHCI utilizes OHCI or UHCI controllers as “companion"companion controllers”controllers", where USB 2 devices are managed through the EHCI stack, and the port logic of the EHCI allows a USB 1low-speed or 2full-speed USB device to be routed to a port of a “companion”"companion" UHCI or OHCI controller, where the USBlow-speed 1or andfull-speed 2USB devices are managed through the respective UHCI or OHCI stack. For example, a USB 2 PCIe host controller card that presents 4 USB “Standard"Standard A”A" connectors typically presents one 4-port EHCI and two 2-port OHCI controllers to system software. When a USBhigh-speed 2USB device is attached to any of the 4 connectors, the device is managed through one of the 4 root hub ports of the EHCI controller. If a USBlow-speed 1or full-speed USB device is attached to connectors 1 or 2, theyit will be routed to the root hub ports of one of the OHCI controllers for management, and USBlow-speed 1and full-speed USB devices attached to connectors 3 or 4 will be routed to the root hub ports of the other OHCI controller. The EHCI dependence on separate host controllers for high-speed USB 1devices and 2the group of low-speed and full-speed USB devices results in complex interactions and dependencies between the EHCI and OHCI/UHCI drivers.

* The xHCI architecture eliminates the need for companion controllers and their separate driver stacks.

* The incorporation of the schedule, bandwidth management, and USB device address assignment functions, that were previously performed by the driver in to the xHCI hardware enable a simpler, leaner, lower latency software stack for the xHCI.

=== Stream Supportsupport ===

Support for Streams was added to the USB 3.0 SuperSpeed specification, primarily to enable high performance storage operations over USB. Classically there has been a 1:1 relationship between a USB endpoint and a buffer in system memory, and the host controller solely responsible for directing all data transfers. Streams changed this paradigm by providing a 1 -to -many “endpoint"endpoint to buffer”buffer" association, and allowing the device to direct the host controller as to which buffer to move. The USB data transfers associated with a USB Stream endpoint are scheduled by the xHCI the same as any other bulk endpoint is, however the data buffer associated with a transfer is determined by the device.

* The xHCI USB Stream support allows up to 64K buffers to be associated with a single endpoint.

* The xHCI Streams protocol support allows a USB device to select which buffer that the xHCI will transfer when the endpoint is scheduled.

=== Scalability ===

The xHCI architecture was designed to be highly scalable, capable of supporting 1 to 255 USB devices and 1 to 255 root hub ports. Since each USB device is allowed to define up to 31 endpoints, an xHCI that supported 255 devices would have to support 7,906 separate total endpoints. Classically, each memory buffer associated with an endpoint is described by a queue of physical memory blocks, where the queue requires a head pointer, tail pointer, length and other registers to define its state. There are many ways to define queue state, however if one were to assume 32 bytes of register space for each queue, then almost a 256KB256&nbsp;KB of register space would be required to support 7,906 queues. Typically only a small number of USB devices are attached to a system at one time, and on the average a USB device supports 3-4 endpoints, of which only a subset of the endpoints are active at the same time.

The xHCI maintains queue state in system memory as Endpoint Context data structures. The contexts are designed so that they can be cached by the xHCI, and “paged”"paged" in and out as a function of endpoint activity. Thus a vendor can scale their internal xHCI Endpoint Context cache space and resources to match the practical usage models expected for their products, rather than the architectural limits that they support. Ideally the internal cache space is selected so that under normal usage conditions, there is no context paging by the xHCI.

Also USB endpoint activity tends to be bursty. That is, at any point in time a large number of endpoints may be ready to move data, however only a subset are actively moving data. For instance, the interrupt IN endpoint of a mouse may not transfer data for hours if the user is away from their desk. xHCI vendor specific algorithms could detect this condition and make that endpoint a candidate for paging out if other endpoints become busy.

* The xHCI architecture allows large maximum values for the number of USB devices, ports, interrupt vectors, etc. supported, however an implementation only needs to define the number necessary to meet its marketing requirements. For instance, a vendor could choose to limit the number of USB devices that it supported for a tablet xHCI implementation to 16 devices.

* A vendor can further take advantage of xHCI architectural features to scale its internal resources to match its target usage models. For instance, if through usability testing a vendor determines that 95% of tablet users will never connect more than 4 USB devices, and each USB device typically defines 4 endpoints (or less), then internal caching for 16 Endpoint Contexts will ensure that under normal conditions there will be no system memory activity due to Endpoint Context paging.

== History ==

The Open Host Controller Interface (OHCI) specspecification was defined by a consortium of companies (Compaq, Microsoft, and National Semiconductor) as open specification to support USB 1.0 devices. The Universal Host Controller Interface (UHCI) refers to a specification that [[Intel]] originally defined as a proprietary interface to support USB 1.0 devices. The UHCI specspecification was eventually made public, but only after the rest of industry had adopted the OHCI specspecification.

The EHCI specspecification was defined by Intel to support USB 2.0 devices. The EHCI architecture was modeled after the UHCI and OHCI controllers, which required software to build the USB transaction schedules in memory, and to manage bandwidth and address allocation. To eliminate a redundant industry effort of defining an open version of a USB 2.0 host controller interface, Intel made the EHCI specspecification available to the industry with no licensing fees. This licensing model was continued for the xHCI spec.

The xHCI spec was also defined by Intel, however with a greatly expanded industry contribution. Over 100 companies have contributed to the xHCI specification. The USB-IF has also funded a set of xHCI Compliance Tests to maximize the compatibility of the various xHCI implementations. xHCI controllers have been shipping since December of 2009. Linux drivers are available online. Windows drivers for XP, Vista, and Win 7 are available from the respective xHCI vendors. xHCI drivers for embedded system are available from MCCI, Jungo, and other software vendors. xHCI IP blocks are also available from several vendors for customization in SOC environments.

The EHCI licensing model was continued for Intel's xHCI specification, however with a greatly expanded industry contribution. Over 100 companies have contributed to the xHCI specification. The [[USB Implementers Forum]] (USB-IF) has also funded a set of xHCI Compliance Tests to maximize the compatibility of the various xHCI implementations.

xHCI 1.0 controllers have been shipping since December 2009. Linux kernels since 2009 contain xHCI drivers,<ref>{{cite web|url=https://hvera.wordpress.com/2009/06/10/usb-3-0-in-linux-kernel/|title=USB 3.0 in Linux kernel|website=hvera.wordpress.com |date= 10 June 2009|accessdate=2017-02-02}}</ref> but for older kernels there are drivers available online. Windows drivers for XP, Vista, and Windows 7 are available from the respective xHCI vendors. xHCI drivers for embedded system are available from [[MCCI Corporation|MCCI]], [[Jungo]], and other software vendors. xHCI IP blocks are also available from several vendors for customization in SOC environments. xHCI 1.1 controllers and devices began shipping in 2015.

=== Version history ===

The xHCI specification uses “errata”"errata" files to define updates and clarifications to a specific release. The changes in the errata files are accumulated in each release. Refer to the associated errata files for the details of specific changes.

Most changes defined in the xHCI errata files are clarifications, grammatical or spelling corrections, additional cross-references, etc., which do not affect a driver implementation. Changes that are determined to be ''architectural'' utilize a ''Capability'' flag to determine whether a particular feature is supported by an xHCI implementation, and an ''Enable'' flag to turn on the feature.

==== Prereleases ====

The xHCI specification evolved through several versions before its official release in 2010:

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* ''USB 0.96'': Released in August 2009.

* ''USB 0.96a'': 1.0 Release Candidate, Released in April 2010. First shipping devices based on this version.

==== xHCI 1.0 ====

* ''xHCI 1.0'': First public release, May 21, 2010. <br />Specified USB data rates of ''1.5&nbsp;Mbit/s'' (''Low-speed''), ''12&nbsp;Mbit/s'' (''Full-speed''), ''480&nbsp;Mbit/s'' (''High-speed'') and ''5&nbsp;Gbit/s'' (''SuperSpeed'').

* ''xHCI 1.0, errata files 1-4'': Released inon January 17, 2011. <br />Incorporated initial review feedback from larger 1.0 public audience, Save-Restore clarifications, and Hardware LPM support.

* ''xHCI 1.0, errata files 1-6'': Released inon March 18, 2011. <br />Clarifications.

* ''xHCI 1.0, errata files 1-7'': Released inon June 13, 2011. <br />Clarifications.

==== xHCI 1.1 ====

* ''xHCI 1.1'': Released on December 21, 2013. Specified USB 3.1 data rate of ''10&nbsp;Gbit/s'' (''SuperSpeed+''). This incorporates xHCI 1.0 errata files 1-21. Allows controller to require a larger number of scratchpad buffers (up to 1023) in HCSPARAMS2 capability register.

==== xHCI 1.2 ====

* ''xHCI 1.2'': Dated May 2019. Specified USB 3.2 data rates of ''10&nbsp;Gbit/s'' (''SuperSpeedPlus Gen1x2'') and ''20&nbsp;Gbit/s'' (''SuperSpeedPlus Gen2x2'').<ref>{{Cite web | url=https://www.intel.com/content/www/us/en/products/docs/io/universal-serial-bus/extensible-host-controler-interface-usb-xhci.html | title=Intel &#124; Data Center Solutions, IoT, and PC Innovation }}</ref>

==References==

{{Reflist}}

== External links ==

{{Commons category|USB}}

{{wikibooks|Serial Programming:USB Technical Manual|USB connectors}}

* [http://www.usb.org/ USB official website (USB Implementers Forum, Inc.)]

* [ftp://ftp.compaq.com/pub/supportinformation/papers/hcir1_0a.pdf Open Host Controller Interface (OHCI)]{{dead link|date=May 2025|bot=medic}}{{cbignore|bot=medic}}

* [http://downloadwww.intelusbman.com/technologyWebDrivers/usbusbpdffiles/UHCI11DUHCI%20Intel%20Specification.pdf Intel Universal Host Controller Interface (UHCI)] [https://web.archive.org/web/20100326195950/http://www.usbman.com/WebDrivers/usbpdffiles/UHCI%20Intel%20Specification.pdf Archived there]

* [http://downloadwww.intel.com/technology/usb/download/ehci-r10.pdf Intel Enhanced Host Controller Interface (EHCI)]

* [http://downloadwww.intel.com/technologycontent/usbdam/xhcispecwww/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.htmpdf Intel eXtensible Host Controller Interface (xHCI)]

[[Category:USB]]