Content deleted Content added
m →top: capitalization fixing |
add Enhanced Host Controller Interface to the list of predecessors. |
||
| (38 intermediate revisions by 27 users not shown) | |||
Line 1:
{{Redirect|XHCI|the radio station|XHCI-FM}}
{{short description|Computer interface specification}}
{{More footnotes|date=April 2014}}
The '''eXtensible Host Controller Interface''' ('''xHCI
Distinct from its predecessors, the [[Open Host Controller Interface]] (OHCI), the [[Universal Host Controller Interface]] (UHCI) and the [[Host controller interface (USB, Firewire)#EHCI|Enhanced Host Controller Interface]] (EHCI), xHCI offers several technological improvements. Specifically, it is designed to handle multiple data transfer speeds (low, full, high, and SuperSpeed) within a single unified standard. This makes it more efficient in managing computational and power resources, a feature particularly beneficial for mobile devices with limited power capabilities like tablets and smartphones. Additionally, xHCI simplifies the architecture needed to support a mixture of low-speed and high-speed devices, which streamlines the development of drivers and system software.
xHCI marks a significant improvement over its predecessors, the Open Host Controller Interface (OHCI), the Universal Host Controller Interface (UHCI) and the Enhanced Host Controller Interface (EHCI), in several key ways:
# '''Multi-Speed Support''': Unlike OHCI, UHCI and EHCI, which were limited to specific USB speeds, xHCI is capable of managing multiple data transfer speeds—low, full, high, and SuperSpeed—under a single standard. This eliminates the need for multiple host controllers or complex switching mechanisms when dealing with various types of USB devices, thereby improving efficiency.
# '''Power Management''': xHCI includes advanced power management features that allow for selective suspension of USB devices and more granular power distribution. This is especially beneficial for mobile devices with limited battery life, such as tablets and laptops, as it helps to maximize power utilization and extend battery life.
# '''Streamlined Architecture''': xHCI's architecture is designed to be simpler and more straightforward, reducing the complexity of driver development. In older architectures like OHCI, UHCI and EHCI, supporting a mix of low-speed and high-speed devices required complicated algorithms and multiple transaction translators. xHCI simplifies this by integrating these functions into the host controller itself, thus easing the burden on system software and driver developers.
By enhancing support for multiple speeds, optimizing power management, and simplifying the underlying architecture, xHCI serves as a more efficient and unified standard for USB host controllers.
== Architectural goals ==
Line 10 ⟶ 22:
* Minimize host memory accesses, fully eliminating them when USB devices are idle
* Eliminate register writes and minimize register reads for normal data transfers
* Eliminate the
* Enable hardware
* Provide the ability for different markets to differentiate hardware capabilities, e.g. target host controller power, performance and cost trade-offs for specific markets
* Define an extensible architecture that provides an easy path for new USB specifications and technologies, such as higher bandwidth interfaces, optical transmission medium, etc., without requiring the definition of yet another USB host controller interface
== Architectural details ==
=== Support for all speeds ===
The OHCI and UHCI controllers support only USB 1 speed devices (1.5
The xHCI architecture was designed to support all USB speeds, including SuperSpeed (5
=== Power efficiency ===
When USB was originally developed in 1995, it was targeted at desktop platforms to stem the proliferation of connectors that were appearing on PCs, e.g. [[PS/2 connector|PS/2]], [[serial port]], [[parallel port]],
* The xHCI eliminates host memory based USB transaction schedules, enabling zero host memory activity when there is no USB data movement.
* The xHCI reduces the need for periodic device polling by allowing a USB 3.0 or later device to notify the host controller when it has data available to read, and moves the management of polling USB 2.0 and 1.1 devices that use interrupt transactions from the CPU-driven USB driver to the USB host controller. EHCI, OHCI, and UHCI host controllers would automatically handle polling for the CPU if there are no changes that need to be made and if no device has any interrupts to send but they all rely on the CPU to set the schedule up for the controllers.<ref>
* The xHCI does not require that implementations provide support for all advanced USB 2 and 3 power management features, including USB 2 LPM, USB 3 U1 and U2 states, HERD, LTM, Function Wake, etc.; but these features are required to realize all of the advantages of xHCI.
=== Virtualization support ===
Legacy USB host
*
*
*
*
=== Simplified driver architecture ===
The EHCI utilizes OHCI or UHCI controllers as
* The xHCI architecture eliminates the need for companion controllers and their separate driver stacks.
* The incorporation of the schedule, bandwidth management, and USB device address assignment functions, that were previously performed by the driver in to the xHCI hardware enable a simpler, leaner, lower latency software stack for the xHCI.
=== Stream support ===
Support for Streams was added to the USB 3.0 SuperSpeed specification, primarily to enable high performance storage operations over USB. Classically there has been a 1:1 relationship between a USB endpoint and a buffer in system memory, and the host controller solely responsible for directing all data transfers. Streams changed this paradigm by providing a 1-to-many
* The xHCI USB Stream support allows up to 64K buffers to be associated with a single endpoint.
* The xHCI Streams protocol support allows a USB device to select which buffer that the xHCI will transfer when the endpoint is scheduled.
=== Scalability ===
The xHCI architecture was designed to be highly scalable, capable of supporting 1 to 255 USB devices and 1 to 255 root hub ports. Since each USB device is allowed to define up to 31 endpoints, an xHCI that supported 255 devices would have to support 7,906 separate total endpoints. Classically, each memory buffer associated with an endpoint is described by a queue of physical memory blocks, where the queue requires a head pointer, tail pointer, length and other registers to define its state. There are many ways to define queue state, however if one were to assume 32 bytes of register space for each queue, then almost a
The xHCI maintains queue state in system memory as Endpoint Context data structures. The contexts are designed so that they can be cached by the xHCI, and
Also USB endpoint activity tends to be bursty. That is, at any point in time a large number of endpoints may be ready to move data, however only a subset are actively moving data. For instance, the interrupt IN endpoint of a mouse may not transfer data for hours if the user is away from their desk. xHCI vendor specific algorithms could detect this condition and make that endpoint a candidate for paging out if other endpoints become busy.
* The xHCI architecture allows large maximum values for the number of USB devices, ports, interrupt vectors, etc. supported, however an implementation only needs to define the number necessary to meet its marketing requirements. For instance, a vendor could choose to limit the number of USB devices that it supported for a tablet xHCI implementation to 16 devices.
Line 54 ⟶ 66:
== History ==
The Open Host Controller Interface (OHCI) specification was defined by a consortium of companies (Compaq, Microsoft, and National Semiconductor) as open specification to support USB 1.0 devices. The Universal Host Controller Interface (UHCI) refers to a specification that [[Intel]] originally defined as a proprietary interface to support USB 1.0 devices. The UHCI specification was eventually made public, but only after the rest of industry had adopted the OHCI specification.
The EHCI specification was defined by Intel to support USB 2.0 devices. The EHCI architecture was modeled after the UHCI and OHCI controllers, which required software to build the USB transaction schedules in memory, and to manage bandwidth and address allocation. To eliminate a redundant industry effort of defining an open version of a USB 2.0 host controller interface, Intel made the EHCI specification available to the industry with no licensing fees
The EHCI licensing model was continued for Intel's xHCI specification, however with a greatly expanded industry contribution. Over 100 companies have contributed to the xHCI specification. The [[USB Implementers Forum]] (USB-IF) has also funded a set of xHCI Compliance Tests to maximize the compatibility of the various xHCI implementations.
xHCI 1.0 controllers have been shipping since December 2009. Linux kernels since 2009 contain xHCI drivers,<ref>{{cite web|url=https://hvera.wordpress.com/2009/06/10/usb-3-0-in-linux-kernel/|title=USB 3.0 in Linux kernel|website=hvera.wordpress.com |date= 10 June 2009|accessdate=2017-02-02}}</ref> but for older kernels there are drivers available online. Windows drivers for XP, Vista, and Windows 7 are available from the respective xHCI vendors. xHCI drivers for embedded system are available from [[MCCI Corporation|MCCI]], [[Jungo]], and other software vendors. xHCI IP blocks are also available from several vendors for customization in SOC environments. xHCI 1.1 controllers and devices began shipping in 2015.
=== Version history ===
Line 70 ⟶ 86:
==== xHCI 1.0 ====
* ''xHCI 1.0'': First public release, May 21, 2010. <br />Specified USB data rates of ''1.5 Mbit/s'' (''Low-speed''), ''12 Mbit/s'' (''Full-speed''), ''480 Mbit/s'' (''High-speed'') and ''5 Gbit/s'' (''SuperSpeed'').
* ''xHCI 1.0, errata files 1-4'': Released
* ''xHCI 1.0, errata files 1-6'': Released
* ''xHCI 1.0, errata files 1-7'': Released
==== xHCI 1.1 ====
* ''xHCI 1.1'': Released on December 21, 2013. Specified USB 3.1 data rate of ''10 Gbit/s'' (''SuperSpeed+''). This incorporates xHCI 1.0 errata files 1-21.
==== xHCI 1.2 ====
* ''xHCI 1.2'': Dated May 2019. Specified USB 3.2 data rates of ''10 Gbit/s'' (''SuperSpeedPlus Gen1x2'') and ''20 Gbit/s'' (''SuperSpeedPlus Gen2x2'').<ref>{{Cite web | url=https://www.intel.com/content/www/us/en/products/docs/io/universal-serial-bus/extensible-host-controler-interface-usb-xhci.html | title=Intel | Data Center Solutions, IoT, and PC Innovation }}</ref>
==References==
Line 81 ⟶ 100:
== External links ==
{{wikibooks|Serial Programming:USB Technical Manual|USB connectors}}
* [http://www.usb.org/ USB official website (USB Implementers Forum, Inc.)]
* [ftp://ftp.compaq.com/pub/supportinformation/papers/hcir1_0a.pdf Open Host Controller Interface (OHCI)]{{dead link|date=May 2025|bot=medic}}{{cbignore|bot=medic}}
* [http://www.usbman.com/WebDrivers/usbpdffiles/UHCI%20Intel%20Specification.pdf Intel Universal Host Controller Interface (UHCI)] [https://web.archive.org/web/20100326195950/http://www.usbman.com/WebDrivers/usbpdffiles/UHCI%20Intel%20Specification.pdf Archived there]
* [http://www.intel.com/technology/usb/download/ehci-r10.pdf Intel Enhanced Host Controller Interface (EHCI)]
* [http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf Intel eXtensible Host Controller Interface (xHCI)]
[[Category:USB]]
| |||