Programmable ROM: Difference between revisions

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{{Memory types}}

{{short description|TypeWrite of solid stateonce computer memory that becomes read only after being written once}}

A '''programmable read-only memory''' ('''PROM''') is a form of digital memory where the contents can be changed once after manufacture of the device. The data is then permanent and cannot be changed. It is one type of [[read-only memory]] (ROM). PROMs are usually used in digital electronic devices to store permanent data, usually low level programs such as [[firmware]] or [[microcode]]. ThePROMs keymay differencebe fromused aduring standarddevelopment [[Read-onlyof memory|ROM]]a issystem that thewill dataultimately isbe writtenconverted intoto aROMs ROM during manufacture, while within a PROMmass theproduced data is programmed into them after manufactureversion. Thus,These ROMstypes tendof tomemories beare used onlyin for[[microcontroller]]s, large[[video productiongame runsconsole]]s, withmobile wellphones, radio-verifiedfrequency data.identification PROMs([[RFID]]) maytags, beimplantable usedmedical wheredevices, thehigh-definition volumemultimedia requiredinterfaces does not make a factory-programmed ROM economical([[HDMI]]), orand duringin developmentmany ofother aconsumer systemand thatautomotive may ultimately be converted to ROMs in a mass produced versionproducts.

PROMs are manufactured blank and, depending on the technology, can be programmed at the wafer, final test, or in system stage. Blank PROM chips are programmed by plugging them into a device called a ''PROM programmer''. CompaniesA cantypical keepPROM adevice supplyhas ofan blankarray PROMsof inmemory stock, and program them at the last minute to avoid large volume commitmentcells. These types of memories are frequently used inThe [[microcontroller]]s,bipolar [[video game consoletransistor]]s, mobile phones, radio-frequency identification ([[RFID]]) tags, implantable medical devices, high-definition multimedia interfaces ([[HDMI]]) and in manythe othercells consumer and automotive electronics products. A typical PROM device is made up ofhave an arrayemitter of memory cells, each made up of a transistor, whichthat is a [[bipolar transistor]], connected to a [[Fuse (electrical)|fuse]] called a [[polyfuse (PROM)|polyfuse]]. inTo theprogram emitter of the transistor. Aa PROM programmer is used to strategically blow the polyfuse, programming the PROMpolyfuses.<ref>{{cite book | url=https://books.google.com/books?id=9VHMBQAAQBAJ&dq=prom+fuse&pg=PA760 | title=The Electronics Handbook | isbn=978-1-4200-3666-4 | last1=Whitaker | first1=Jerry C. | date=3 October 2018 | publisher=CRC Press }}</ref>

== History ==

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=== One time programmable memory ===

OTP (one time programmable) memory is a special type of [[non-volatile memory]] (NVM) that permits data to be written to memory only once. Once the memory has been programmed, it retains its value upon loss of power (i.e., is non-volatile). OTP memory is used in applications where reliable and repeatable reading of data is required. Examples include boot code, encryption keys and configuration parameters for analog, sensor or display circuitry. OTP NVM is characterized, over other types of NVM like [[eFuse]] or EEPROM, by offering a low power, small area footprint memory structure. As such, OTP memory finds application in products from microprocessors & display drivers to Powerpower Managementmanagement ICs (PMICs).

Commercially available semiconductor antifuse-based OTP memory arrays have been around at least since 1969, with initial antifuse bit cells dependent on blowing a capacitor between crossing conductive lines. [[Texas Instruments]] developed a MOS [[gate oxide]] breakdown antifuse in 1979.<ref>See [http://patimg2.uspto.gov/.piw?Docid=4184207&idkey=NONE US Patent 4184207] {{Webarchive|url=https://web.archive.org/web/20180427183945/http://patimg2.uspto.gov/.piw?Docid=4184207&idkey=NONE |date=2018-04-27 }} - High density floating gate electrically programmable ROM, and [http://patimg2.uspto.gov/.piw?Docid=4151021&idkey=NONE US Patent 4151021] {{webarchive|url=https://web.archive.org/web/20180427092847/http://patimg2.uspto.gov/.piw?Docid=4151021&idkey=NONE |date=2018-04-27 }} - Method of making a high density floating gate electrically programmable ROM</ref> A dual-gate-oxide two-transistor (2T) MOS antifuse was introduced in 1982.<ref>[http://www.chipestimate.com/techtalk/techtalk_071218.html Chip Planning Portal]. ChipEstimate.com. Retrieved on 2013-08-10.</ref> Early oxide breakdown technologies exhibited a variety of scaling, programming, size and manufacturing problems that prevented volume production of memory devices based on these technologies.

Another form of one-time programmable memory device uses the same semiconductor chip as an ultraviolet-[[EPROM|erasable programmable read-only memory]] (UV-EPROM), but the finished device is put into an opaque package, instead of the expensive ceramic package with transparent quartz window required for erasing. These devices are programmed with the same methods as the UV EPROM parts but are less costly. Embedded controllers may be available in both field-erasable and one-time styles, allowing a cost saving in volume production without the expense and lead time of factory-programmed mask ROM chips. <ref>Ken Arnold, "Embedded Controller Hardware Design", Newnes, 2004, ISBN 1-878707-52-3, page 102</ref>

Although antifuse-based PROM has been available for decades, it wasn’t available in standard [[CMOS]] until 2001 when Kilopass Technology Inc. patented 1T, 2T, and 3.5T antifuse bit cell technologies using a standard CMOS process, enabling integration of PROM into logic CMOS chips. The first process node antifuse can be implemented in standard CMOS is 0.18&nbsp;um. Since the gate oxide breakdown is less than the junction breakdown, special diffusion steps were not required to create the antifuse programming element. In 2005, a split channel antifuse device<ref>See [http://patimg2.uspto.gov/.piw?Docid=7402855&idkey=NONE US Patent 7402855] {{Webarchive|url=https://web.archive.org/web/20150904051044/http://patimg2.uspto.gov/.piw?Docid=7402855&idkey=NONE |date=2015-09-04 }} split channel antifuse device</ref> was introduced by Sidense. This split channel bit cell combines the thick (IO) and thin (gate) oxide devices into one transistor (1T) with a common [[Polycrystalline silicon|polysilicon]] gate.

== Programming ==

[[File:ANT Nachrichtentechnik DBT-03 - Texas Instruments TBP18SA030N-0019.jpg|thumb|Texas Instruments PROM type TBP18SA030N]]

A typical PROM comes with all bits reading as "1". Burning a fuse bit during programming causes the bit to be read as "0" by "blowing" the fuses, which is an irreversible process. Some devices can be "reprogrammed" if the new data replaces "1"s with "0"s. Some CPU instruction sets (e.g. [[MOS Technology 6502#Bugs and quirks|6502]]) took advantage of this by defining a break (BRK) instruction with the operation code of '00'. In cases where there was an incorrect instruction, it could be "reprogrammed" to a BRK causing the CPU to transfer control to a patch. This would execute the correct instruction and return to the instruction after the BRK.

The bit cell is programmed by applying a high-voltage pulse not encountered during a normal operation across the gate and substrate of the thin oxide transistor (around 6{{nbsp}}V for a 2&nbsp;nm thick oxide, or 30{{nbsp}}MV/cm) to break down the oxide between gate and substrate. The positive voltage on the transistor's gate forms an inversion channel in the substrate below the gate, causing a tunneling current to flow through the oxide. The current produces additional traps in the oxide, increasing the current through the oxide and ultimately melting the oxide and forming a conductive channel from gate to substrate. The current required to form the conductive channel is around 100{{nbsp}}µAμA/100{{nbsp}}nm{{sup|2}} and the breakdown occurs in approximately 100{{nbsp}}µsμs or less.<ref>{{cite web |url=http://www.sidense.com/images/stories/designcon_8_a_eval_embedded_nvm_65nm_and_beyond.pdf |title=Evaluating Embedded Non-Volatile Memory for 65nm and Beyond |author=Wlodek Kurjanowicz |year=2008 |access-date=2009-09-04 |url-status=dead |archive-url=https://web.archive.org/web/20160304025935/http://www.sidense.com/images/stories/designcon_8_a_eval_embedded_nvm_65nm_and_beyond.pdf |archive-date=2016-03-04 }}</ref>

==See also==

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==References==

* [https://archive.org/details/bitsavers_inteldataBMay77_21293903 1977 Intel Memory Design Handbook] - archive.org

* {{usurped|1=[https://web.archive.org/web/20130812120201/http://www.intel-vintage.info/intelmemory.htm Intel PROM datasheets]}} - intel-vintage.info

* View the US "Switch Matrix" Patent #3028659 at [http://patimg2.uspto.gov/.piw?Docid=03028659&idkey=NONE US Patent Office] {{Webarchive|url=https://web.archive.org/web/20151016080757/http://patimg2.uspto.gov/.piw?Docid=03028659&idkey=NONE |date=2015-10-16 }} or [httphttps://wwwpatents.google.com/patents?id=ydtHAAAAEBAJpatent/US3028659 Google]

* View Kilopass Technology Patent US "High density semiconductor memory cell and memory array using a single transistor and having variable gate oxide breakdown" Patent #6940751 at [http://patimg2.uspto.gov/.piw?Docid=6940751&idkey=NONE US Patent Office] {{Webarchive|url=https://web.archive.org/web/20150904051044/http://patimg2.uspto.gov/.piw?Docid=6940751&idkey=NONE |date=2015-09-04 }} or [httphttps://wwwpatents.google.com/patentspatent/about?id=bM0VAAAAEBAJUS6940751 Google]

* View Sidense US "Split Channel Antifuse Array Architecture" Patent #7402855 at [http://patimg2.uspto.gov/.piw?Docid=7402855&idkey=NONE US Patent Office] {{Webarchive|url=https://web.archive.org/web/20150904051044/http://patimg2.uspto.gov/.piw?Docid=7402855&idkey=NONE |date=2015-09-04 }} or [httphttps://wwwpatents.google.com/patents?id=AYOZAAAAEBAJpatent/US20060244099 Google]

* View the US "Method of Manufacturing Semiconductor Integrated Circuits" Patent #3634929 at [http://patimg2.uspto.gov/.piw?Docid=3634929&idkey=NONE US Patent Office] {{Webarchive|url=https://web.archive.org/web/20150904051044/http://patimg2.uspto.gov/.piw?Docid=3634929&idkey=NONE |date=2015-09-04 }} or [httphttps://wwwpatents.google.com/patents?id=9MEzAAAAEBAJpatent/US3634929 Google]

* CHOI et al. (2008). {{usurped|1=[https://wayback.archive-it.org/all/20081031153339/http://www.ee.ucla.edu/~ipl/New_Non-Volatile_Memory_Structures_for_FPGA_Architectures.pdf "New Non-Volatile Memory Structures for FPGA Architectures"]}}

* For the Advantages and Disadvantages table, see Ramamoorthy, G: "Dataquest Insight: Nonvolatile Memory IP Market, Worldwide, 2008-2013", page 10. Gartner, 2009