OpenPIC and MPIC: Difference between revisions

Revision as of 16:27, 7 August 2022

Latest revision as of 03:11, 12 August 2025

(3 intermediate revisions by 3 users not shown)

Line 1:

In order to compete with [[Intel]]'s [[Advanced Programmable Interrupt Controller]] (APIC), which had enabled the first [[Intel 486]]-based [[multiprocessor]] systems, in early 1995 [[AMD]] and [[Cyrix]] proposed as somewhat similar-in-purpose '''OpenPIC''' architecture supporting up to 32 processors.<ref>{{cite web |url=https://www.pcmag.com/encyclopedia_term/0,2542,t=OpenPIC&i=48497,00.asp |title=OpenPIC Definition from PC Magazine Encyclopedia |publisher=Pcmag.com |date=1994-12-01 |accessdate=2011-11-03 }}{{Dead link|date=August 2025 |bot=InternetArchiveBot |fix-attempted=yes }}</ref><ref>AMD and Cyrix, [https://web.archive.org/web/20180817035617/http://mess.redump.net/_media/datasheets/chrp/19725c_opic_spec_1.2_oct95.pdf The Open Programmable Interrupt Controller (PIC) Register Interface Specification Revision 1.2], October 1995. Archived from the [http://mess.redump.net/_media/datasheets/chrp/19725c_opic_spec_1.2_oct95.pdf original] on 17 Aug 2018.</ref> The OpenPIC architecture had at least declarative support from [[IBM]] and [[Compaq]] around 1995.<ref name="Inc.1995">{{cite book|title=AMD, Cyrix offer up alternative SMP spec|author=Brooke Crothers|publisher=[[InfoWorld]]|url=https://books.google.com/books?id=lToEAAAAMBAJ&pg=PA8|date=20 March 1995|page=8|issn=0199-6649}}</ref> No x86 motherboard was released with OpenPIC however.<ref>André D. Balsa, [http://linuxgazette.net/issue24/Article3e-7.html Note attached to "Linux Benchmarking: Part III -- Interpreting Benchmark Results"] appearing in Issue 24 of Linux Gazette, January 1998</ref> After the OpenPIC's failure in the x86 market, AMD licensed the [[Intel APIC Architecture]] for its [[AMD Athlon]] and later processors.

IBM however developed their '''Multiprocessor Interrupt Controller''' ('''MPIC''') based on the OpenPIC register specification.<ref name="mpic db"/> In the reference IBM design, the processors share the MPIC over a [[CoreConnect#Device_Control_Register_(DCR)_bus|DCR bus]], with their access to the bus controlled by a DCR Arbiter. MPIC supports up to four processors and up to 128 interrupt sources.<ref name="mpic db">IBM [https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/F27971551C9EED8E8525774A0048770A/$file/mpic_db_05_16_2011.pdf Multiprocessor Interrupt Controller. Data Book] {{Webarchive|url=https://web.archive.org/web/20140223012746/https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/F27971551C9EED8E8525774A0048770A/%24file/mpic_db_05_16_2011.pdf |date=2014-02-23 }}</ref> Through various implementations, the MPIC was included in [[PowerPC]] reference designs and some retail computers.

IBM used a MPIC based on OpenPIC 1.0 in their [[RS/6000]] F50 and one based on OpenPIC 1.2 in their RS/6000 S70. Both of these systems also used a dual [[8259]] on their PCI-ISA bridges.<ref>Arca Systems TTAP Evaluation Facility, "[http://www.ashtonlabs.com/library/FERs/CSC-FER-98-004.pdf The IBM Corporation RS/6000 Distributed System Running AIX Version 4.3.1. TCSEC Evaluated C2 Security]", p. 29</ref> An IBM MPIC was also used in the RS/6000 7046 Model B50.<ref>RS/6000 7046 Model B50 Handbook, November 1999, IBM document G24-7046-00, p. 107</ref>

Line 20:

[[Category:Motherboard]]

[[Category:Interrupts]]

[[Category:Advanced Micro DevicesAMD platforms]]

[[Category:Macintosh platform]]

[[Category:IBM computer hardware]]