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In order to compete with [[Intel]]'s [[Advanced Programmable Interrupt Controller]] (APIC), which had enabled the first [[Intel 486]]-based [[multiprocessor]] systems, in early 1995 [[AMD]] and [[Cyrix]] proposed as somewhat similar-in-purpose '''OpenPIC''' architecture supporting up to 32 processors.<ref>{{cite web |url=httphttps://www.pcmag.com/encyclopedia_term/0,2542,t=OpenPIC&i=48497,00.asp |title=OpenPIC Definition from PC Magazine Encyclopedia |publisher=Pcmag.com |date=1994-12-01 |accessdate=2011-11-03 }}{{Dead link|date=August 2025 |bot=InternetArchiveBot |fix-attempted=yes }}</ref><ref>AMD and Cyrix, [https://web.archive.org/web/20180817035617/http://mess.redump.net/_media/datasheets/chrp/19725c_opic_spec_1.2_oct95.pdf The Open Programmable Interrupt Controller (PIC) Register Interface Specification Revision 1.2], October 1995. Archived from the [http://mess.redump.net/_media/datasheets/chrp/19725c_opic_spec_1.2_oct95.pdf original] on 17 Aug 2018.</ref> The OpenPIC architecture had at least declarative support from [[IBM]] and [[Compaq]] around 1995.<ref name="Inc.1995">{{cite book|authortitle=InfoWorldAMD, MediaCyrix Group,offer Inc.up alternative SMP spec|titleauthor=Brooke Crothers|publisher=[[InfoWorld]]|url=httphttps://books.google.com/books?id=lToEAAAAMBAJ&pg=PA8|date=20 March 1995|publisher=InfoWorld Media Group, Inc.|page=8|idissn={{ISSN|01996649}}0199-6649}}</ref> No x86 motherboard was released with OpenPIC however.<ref>André D. Balsa, [http://linuxgazette.net/issue24/Article3e-7.html Note attached to "Linux Benchmarking: Part III -- Interpreting Benchmark Results"] appearing in Issue 24 of Linux Gazette, January 1998</ref> After the OpenPIC's failure in the x86 market, AMD licensed the [[Intel APIC Architecture]] for its [[AMD Athlon]] and later processors.
IBM however developed their '''MultiProcessorMultiprocessor Interrupt Controller''' ('''MPIC''') based on the OpenPIC register specification.<ref Throughname="mpic various implementations, the MPIC was included used in some [[PowerPC]] reference designs and concrete computers. MPIC supports up to four processors and up to 128 interrupt sources.db"/> In the reference IBM design, the processors share the MPIC over a [[CoreConnect#Device_Control_Register_(DCR)_bus|DCR bus]], with their access to the bus cotrolledcontrolled by a DCR Arbiter. MPIC supports up to four processors and up to 128 interrupt sources.<ref name="mpic db">IBM [https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/F27971551C9EED8E8525774A0048770A/$file/mpic_db_05_16_2011.pdf Multiprocessor Interrupt Controller. Data Book]</ref> IBM used a MPIC based on OpenPIC 1.0 in their [[RS{{Webarchive|url=https:/6000]] F50 and one based on OpenPIC 1.2 in their RS/6000 S70web. Both of these systems used a dual [[8259]] on their PCI-ISA bridgesarchive.<ref>Arca Systems TTAP Evaluation Facility [httporg/web/20140223012746/https://www-01.ashtonlabsibm.com/librarychips/FERstechlib/CSC-FER-98-004techlib.pdf The IBM Corporation RSnsf/6000 Distributed System Running AIX Version 4.3.1. TCSEC Evaluated C2 Security], p. 29<techdocs/ref> An IBM MPIC was also used in the RSF27971551C9EED8E8525774A0048770A/6000 7046 Model B50%24file/mpic_db_05_16_2011.<ref>RS/6000pdf 7046 Model B50 Handbook, November 1999, IBM document G24|date=2014-704602-00, p.23 107}}</ref> TheThrough Applevarious Hydra chip (fromimplementations, the 1990s [[MacOS]] era) implemented a MPIC alongsidewas aincluded [[SCSI]] controller,in [[Apple Desktop Bus|ADBPowerPC]] controller,reference [[GeoPort]] controller,designs and timers.<ref>[http://cache.freescale.com/files/archives/doc/ref_manual/YKNIFEX4HW.pdf Yellowknife Reference Platform Hardware Design Manual], p. 11</ref> The MPIC was also incorporated in the newer K2 I/O controller used in some [[Powerretail Mac G5]]scomputers.<ref>[http://www.informit.com/articles/article.aspx?p=606582 Take a Look Inside the G5-Based Dual-Processor Power Mac]</ref><ref>[https://developer.apple.com/legacy/library/documentation/Hardware/Developer_Notes/Macintosh_CPUs-G5/PowerMacG5/PowerMacG5.pdf Power Mac G5 Developer Note (Legacy)], p. 26</ref>
IBM used a MPIC based on OpenPIC 1.0 in their [[RS/6000]] F50 and one based on OpenPIC 1.2 in their RS/6000 S70. Both of these systems also used a dual [[8259]] on their PCI-ISA bridges.<ref>Arca Systems TTAP Evaluation Facility, "[http://www.ashtonlabs.com/library/FERs/CSC-FER-98-004.pdf The IBM Corporation RS/6000 Distributed System Running AIX Version 4.3.1. TCSEC Evaluated C2 Security]", p. 29</ref> An IBM MPIC was also used in the RS/6000 7046 Model B50.<ref>RS/6000 7046 Model B50 Handbook, November 1999, IBM document G24-7046-00, p. 107</ref>
The [[Apple Inc.|Apple]] Hydra [[Mac I/O]] (MIO) chip (from the 1990s [[classic Mac OS]] era) implemented a MPIC alongside a [[SCSI]] controller, [[Apple Desktop Bus|ADB]] controller, [[GeoPort]] controller, and timers.<ref>[http://cache.freescale.com/files/archives/doc/ref_manual/YKNIFEX4HW.pdf Yellowknife Reference Platform Hardware Design Manual], p. 11</ref> The Apple implementation of "Open PIC" (as the Apple documentation of this era spells it) in their first MIO chip for the [[Common Hardware Reference Platform]] was based on version 1.2 of the register specification and supported up to two processors and up to 20 interrupt sources.<ref>Macintosh Technology in the Common Hardware Reference Platform, section "2.4.7 Open PIC Interrupt Controller", p. 11, {{ISBN|155860393X}}</ref> A MPIC was also incorporated in the newer K2 I/O controller used in the [[Power Mac G5]]s.<ref>[http://www.informit.com/articles/article.aspx?p=606582 Take a Look Inside the G5-Based Dual-Processor Power Mac]</ref><ref>[https://web.archive.org/web/20140222145839/https://developer.apple.com/legacy/library/documentation/Hardware/Developer_Notes/Macintosh_CPUs-G5/PowerMacG5/PowerMacG5.pdf Power Mac G5 Developer Note (Legacy)], p. 26</ref>
[[Freescale]] also uses a MPIC ("compatible with the Open PIC") on all its [[PowerQUICC]] and [[QorIQ]] processors.<ref>[https://www.kernel.org/doc/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt Freescale MPIC Interrupt Controller Node]</ref> The Linux [[Kernel-based Virtual Machine]] (KVM) supports a virtualized MPIC with up to 256 interrupts, based on the Freescale variants.<ref>{{cite web|url=https://github.com/torvalds/linux/blob/master/Documentation/virtual/kvm/devices/mpic.txt |title=linux/Documentation/virtual/kvm/devices/mpic.txt at master |publisher=Github.com |date=2013-04-30 |accessdate=2014-02-12}}</ref>
== See also ==
== References ==
{{Reflist|30em}}
== External links ==
* [http://opensource.apple.com/source/AppleMPIC/ AppleMPIC open source code]
[[Category:Motherboard]]
[[Category:Interrupts]]
[[Category:AMD platforms]]
[[Category:CyrixMacintosh platform]]
[[Category:AppleIBM computer hardware]]
[[Category:IBMFreescale Semiconductor]]
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