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[[File:Intel_82PM45_Memory_Controller_Hub_-_MCH_AC82PM45-SLB97_-3718.jpg | thumb|right | Intel 82PM45 Memory Controller Hub]]

A '''memory controller''' is a digital circuit that manages the flow of data going to and from a computer's [[main memory]]. A memory controller can be a separate chip or integrated into another chip, such as being placed on the same [[die (integrated circuit)|die]] or as an integral part of a [[microprocessor]]; in the latter case, it is usually called an '''integrated memory controller''' ('''IMC'''). A memory controller is sometimes also called a '''memory controller chip''' ('''MCC''')<ref>Comptia A+ Certification Exam Guide, Seventh Edition, by Mike Meyers, in the glossary, bottom of page 1278: "Chip that handles memory requests from the CPU."</ref> or a '''memory controller unit''' ('''MCU''').<ref>{{cite book|url=https://books.google.com/books?id=PJ49xcoRb1QC&q=%22memory+controller+unit%22&pg=PA100|title=Maximizing Performance and Scalability with IBM WebSphere|access-date=6 February 2015|isbn=9781590591307|last1=Neat|first1=Adam G.|date=2003-12-04}}</ref>

A '''memory controller''', also known as '''memory chip controller''' ('''MCC''') or a '''memory controller unit''' ('''MCU'''), is a digital circuit that manages the flow of data going to and from a computer's [[main memory]].<ref>Comptia A+ Certification Exam Guide, Seventh Edition, by Mike Meyers, in the glossary, bottom of page 1278: "Chip that handles memory requests from the CPU."</ref><ref>{{cite book |last1=Neat |first1=Adam G. |url=https://books.google.com/books?id=PJ49xcoRb1QC&q=%22memory+controller+unit%22&pg=PA100 |title=Maximizing Performance and Scalability with IBM WebSphere |date=2003-12-04 |publisher=Apress |isbn=9781590591307 |access-date=6 February 2015}}</ref> When a memory controller is integrated into another chip, such as an integral part of a [[microprocessor]], it is usually called an '''integrated memory controller''' ('''IMC''').

Memory controllers contain the logic necessary to read and write to [[dynamic random-access memory]] (DRAM), and to provide the critical [[memory refresh]] and other functions. Reading and writing to DRAM is performed by selecting the row and column data addresses of the DRAM as the inputs to the [[multiplexer]] circuit, where the [[demultiplexer]] on the DRAM uses the converted inputs to select the correct memory ___location and return the data, which is then passed back through a multiplexer to consolidate the data in order to reduce the required [[Bus (computing)|bus]] width for the operation. Memory controllers' bus widths range from [[8-bit]] in earlier systems, to 512-bit in more complicated systems, where they are typically implemented as four [[64-bit]] simultaneous memory controllers operating in parallel, though some operate with two 64-bit memory controllers being used to access a [[128-bit]] memory device.

Memory controllers contain the logic necessary to read and write to DRAM, and to "refresh" the DRAM. Without periodic refresh, DRAM will lose the data written to it. Some memory controllers include [[error detection and correction]] hardware.

Some memory controllers, such as the one integrated into [[PowerQUICC]] II processors, include [[error detection and correction]] hardware.<ref>[http://www.freescale.com/files/training_pdf/24815_PQ2_MEM_CONTROL_WBT.pdf "Memory Controller"]</ref> Many modern processors are also integrated [[memory management unit]] (MMU), which in many [[operating system]]s implements [[virtual addressing]]. On early x86-32 processors, the MMU is integrated in the CPU, but the memory controller is usually part of [[northbridge (computing)|northbridge]].<ref>{{Cite web | title=Archived copy | url=https://vikramuniv.ac.in/files/academic/e-Resources2020-21/engg2020-21/BE_6_SEM_EE_MP_MC-_COMP._OF_8086_FAMILY-AMIT_THAKUR-converted-converted.pdf | archive-url=https://web.archive.org/web/20250704122950/https://vikramuniv.ac.in/files/academic/e-Resources2020-21/engg2020-21/BE_6_SEM_EE_MP_MC-_COMP._OF_8086_FAMILY-AMIT_THAKUR-converted-converted.pdf | archive-date=2025-07-04}}</ref>

A common form of memory controller is the [[memory management unit]] (MMU) which in many [[operating system]]s implements [[virtual addressing]].

== History ==

Older Intel and [[PowerPC]]-based computers have memory controller chips that are separate from the main processor. Often these are integrated into the [[Northbridge (computing)|northbridge]] of the computer, also sometimes called a memory controller hub.

{{Anchor|IMC}}Most modern desktop or workstation microprocessors use an '''integrated memory controller''' ('''IMC'''), including microprocessors from [[Intel]], [[AMD]], and those built around the [[ARM architecture]]. Prior to [[AMD K8|K8]] (circa 2003), [[Advanced Micro Devices|AMD]] microprocessors had a memory controller implemented on their motherboard's [[Northbridge_Northbridge (computing)|northbridge]]. In K8 and later, AMD employed an integrated memory controller.<ref>{{Cite web|url=http://www.chip-architect.com/news/2001_10_02_Hammer_microarchitecture.html|title=Chip Architect: AMD's Next Generation Micro Processor's Architecture|last=Vries|first=Hans de|website=www.chip-architect.com|access-date=2018-03-17}}</ref> Likewise, until [[Nehalem (microarchitecture)|Nehalem]] (circa 2008), [[Intel]] microprocessors used memory controllers implemented on the motherboard's northbridge. Nehalem and later switched to an integrated memory controller.<ref>{{cite web|last1=Torres|first1=Gabriel|title=Inside Intel Nehalem Microarchitecture|url=http://www.hardwaresecrets.com/inside-intel-nehalem-microarchitecture/|website=Hardware Secrets|access-date=7 September 2017|page=2|date=2008-08-26}}</ref> Other examples of microprocessor architectures that use ''integrated memory controllers'' include [[NVIDIA]]'s [[Fermi (microarchitecture)|Fermi]], [[IBM]]'s [[POWER5]], and [[Sun Microsystems]]'s [[UltraSPARC T1]].

{{Anchor|IMC}}

Most modern desktop or workstation microprocessors use an ''integrated memory controller'' (IMC), including microprocessors from [[Intel]], [[AMD]], and those built around the [[ARM architecture]].

Prior to [[AMD K8|K8]] (circa 2003), [[Advanced Micro Devices|AMD]] microprocessors had a memory controller implemented on their motherboard's [[Northbridge_(computing)|northbridge]]. In K8 and later, AMD employed an integrated memory controller.<ref>{{Cite web|url=http://www.chip-architect.com/news/2001_10_02_Hammer_microarchitecture.html|title=Chip Architect: AMD's Next Generation Micro Processor's Architecture|last=Vries|first=Hans de|website=www.chip-architect.com|access-date=2018-03-17}}</ref> Likewise, until [[Nehalem (microarchitecture)|Nehalem]] (circa 2008), [[Intel]] microprocessors used memory controllers implemented on the motherboard's northbridge. Nehalem and later switched to an integrated memory controller.<ref>{{cite web|last1=Torres|first1=Gabriel|title=Inside Intel Nehalem Microarchitecture|url=http://www.hardwaresecrets.com/inside-intel-nehalem-microarchitecture/|website=Hardware Secrets|access-date=7 September 2017|page=2|date=2008-08-26}}</ref>

Other examples of microprocessor architectures that use ''integrated memory controllers'' include [[NVIDIA]]'s [[Fermi (microarchitecture)|Fermi]], [[IBM]]'s [[POWER5]], and [[Sun Microsystems]]'s [[UltraSPARC T1]].

While an integrated memory controller has the potential to increase the system's performance, such as by reducing [[memory latency]], it locks the microprocessor to a specific type (or types) of memory, forcing a redesign in order to support newer memory technologies. When [[DDR2 SDRAM]] was introduced, AMD released new [[Athlon 64]] CPUs. These new models, with a DDR2 controller, use a different physical socket (known as [[Socket AM2]]), so that they will only fit in motherboards designed for the new type of RAM. When the memory controller is not on-die, the same CPU may be installed on a new motherboard, with an updated northbridge to use newer memory.

Some microprocessors in the 1990s, such as the DEC [[Alpha 21066]] and HP [[PA-7300LC]], had integrated memory controllers; however, rather than for performance gains, this was implemented to reduce the cost of systems by eliminating the need for an external memory controller.{{citation needed|reason=The linked articles do mention a cost motivator but there are no supporting citations.|date=July 2024}}

Some CPUs are designed to have their memory controllers as dedicated external components that are not part of the chipset. An example is IBM [[POWER8]], which uses external [[Centaur (computing)|Centaur]] chips that are mounted onto [[DIMM]] modules and act as memory buffers, [[L4 cache]] chips, and as the actual memory controllers. The first version of the Centaur chip used DDR3 memory but an updated version was later released which can use DDR4.<ref>{{cite web|url=https://www.itjungle.com/2016/10/17/tfh101716-story02/|title=IBM Brings DDR4 Memory To Bear On Power Systems|last=Prickett Morgan|first=Timothy|date=2016-10-17|website=IT Jungle|pages=1|access-date=2017-09-07}}</ref>

== Security<span class="anchor" id="SCRAMBLING"></span> ==

== Purpose ==

A few experimental memory controllers contain a second level of address translation, in addition to the first level of address translation performed by the CPU's [[memory management unit]] to improve cache and bus performance.<ref>John Carter, Wilson Hsieh, Leigh Stoller, Mark Swansony, Lixin Zhang, et al. [http://www.cs.utah.edu/~ald/pubs/hpca99.pdf "Impulse: Building a Smarter Memory Controller"].</ref>

Memory controllers contain the logic necessary to read and write to [[dynamic random access memory|DRAM]], and to [[memory refresh|"refresh" the DRAM]]. Without constant refreshes, DRAM will lose the data written to it as the [[capacitors]] leak their [[electric charge|charge]] within a fraction of a second (not more than 64 milliseconds according to [[JEDEC]] standards).

Memory controllers integrated into certain [[Intel Core]] processors also provide '''memory scrambling''' as a feature that turns user data written to the main memory into [[pseudo-random]] patterns.<ref>{{cite web

Reading and writing to DRAM is performed by selecting the row and column data addresses of the DRAM as the inputs to the [[multiplexer]] circuit, where the [[demultiplexer]] on the DRAM uses the converted inputs to select the correct memory ___location and return the data, which is then passed back through a multiplexer to consolidate the data in order to reduce the required bus width for the operation.

Bus width is the number of parallel lines available to communicate with the memory cell. Memory controllers' bus widths range from [[8-bit]] in earlier systems, to 512-bit in more complicated systems and video cards (typically implemented as four [[64-bit]] simultaneous memory controllers operating in parallel, though some are designed to operate in "gang mode" where two 64-bit memory controllers can be used to access a [[128-bit]] memory device).

Some memory controllers, such as the one integrated into [[PowerQUICC]] II processors, include [[error detection and correction]] hardware.<ref>[http://www.freescale.com/files/training_pdf/24815_PQ2_MEM_CONTROL_WBT.pdf "Memory Controller"]</ref>

== {{Anchor|SCRAMBLING}}Security ==

A few experimental memory controllers (mostly aimed at the server market where data protection is legally required) contain a second level of address translation, in addition to the first level of address translation performed by the CPU's [[memory management unit]].<ref> This is a security feature in that it allows the Operating System to provide better protection separate from using a bit to deny arbitrary code execution in (System and/or User) RAM memory areas.

John Carter, Wilson Hsieh, Leigh Stoller, Mark Swansony, Lixin Zhang, et al.

[http://www.cs.utah.edu/~ald/pubs/hpca99.pdf "Impulse: Building a Smarter Memory Controller"].

</ref>

Memory controllers integrated into certain [[Intel Core]] processors also provide ''memory scrambling'' as a feature that turns user data written to the main memory into [[pseudo-random]] patterns.<ref>{{cite web

| url = http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/2nd-gen-core-desktop-vol-1-datasheet.pdf

| title = 2nd Generation Intel Core Processor Family Desktop, Intel Pentium Processor Family Desktop, and Intel Celeron Processor Family Desktop

Line 51 ⟶ 33:

| date = September 2012 | access-date = 2015-11-03

| page = 24

}}</ref> Memory Scramblingscrambling (in Cryptographic Theory)has isthe supposedpotential to prevent [[Computer forensics|forensic]] and [[reverse-engineering]] analysis based on [[DRAM data remanence]] by effectively rendering various types of [[cold boot attack]]s ineffective. In current practice, this has not been achieved; memory scrambling has only been designed to address DRAM-related electrical problems. The late 2010s memory scrambling standards do address security issues and are not cryptographically secure or open to public revision or analysis.<ref>{{cite web

}}</ref>

Memory Scrambling (in Cryptographic Theory) is supposed to prevent [[Computer forensics|forensic]] and [[reverse-engineering]] analysis based on [[DRAM data remanence]] by effectively rendering various types of [[cold boot attack]]s ineffective. In current practice this has not been achieved.

However Memory Scrambling has only been designed to address DRAM-related electrical problems. The late 2010s Memory Scrambling Standards do not fix or prevent security issues or problems. The 2010s Memory Scrambling standards are not cryptographically secure, or necessarily open sourced or open to public revision or analysis.<ref>{{cite web

| url = http://www.slideshare.net/codeblue_jp/igor-skochinsky-enpub

| title = Secret of Intel Management Engine

Line 63 ⟶ 41:

}}</ref>

ASUS and Intel have their ownseparate memory scrambling standards. Currently ASUS motherboards have allowed the user to choose which memory scrambling standardsstandard to use [(ASUS or Intel]) or whether to turn the feature off entirely.{{citation needed|date=September 2024}}

== Variants ==

=== Double data rate memory ===

[[Double data rate]] (DDR) memory controllers are used to drive [[DDR SDRAM]], where data is transferred on both rising and falling edges of the system's memory clock. DDR memory controllers are significantly more complicated when compared to single data rate controllers ,{{Citation needed| reason= Why would it be significantly more complicated - provide reliable source if possible | date=April 2018}}, but they allow for twice the data to be transferred without increasing the memory cell's clock rate or bus width.

=== Multichannel memory ===

{{Main|Multi-channel memory architecture}}

Multichannel memory memory controllers are memory controllers where the DRAM devices are separated on toonto multiple different buses to allow the memory controller(s) to access them in parallel. This increases the theoretical amount of bandwidth of the bus by a factor of the number of channels. While a channel for every DRAM cell would be the ideal solution, adding more channels isincreases very difficult due to wire count, [[line capacitance]],complexity and the need for parallel access lines to have identical lengthscost.

=== Fully buffered memory ===

{{Main|Fully Buffered DIMM}}

Fully buffered memory systems place a memory buffer device on every [[DIMM|memory module]] (called an [[FB-DIMM]] when Fullyfully Bufferedbuffered RAM is used), which unlike traditional memory controller devices, use a serial data link to the memory controller instead of the parallel link used in previous RAM designs. This decreases the number of the wires necessary to place the memory devices on a motherboard (allowing for a smaller number of layers to be used, meaning more memory devices can be placed on a single board), at the expense of increasing latency (the time necessary to access a memory ___location). This increase is due to the time required to convert the parallel information read from the DRAM cell to the serial format used by the FB-DIMM controller, and back to a parallel form in the memory controller on the motherboard.

In theory, the FB-DIMM's memory buffer device could be built to access any DRAM cells, allowing for memory cell agnostic memory controller design, but this has not been demonstrated, as the technology is in its infancy.

=== Flash memory controller ===

{{Main|Flash memory controller}}

Many [[flash memory]] devices, such as [[USB flash drive]]s and [[solid -state drive]]s, include a [[flash memory controller]]. Flash memory is inherently slower to access than RAM and often becomes unusable after a few million write cycles, which generally makes it unsuitable for RAM applications.

== See also ==

* [[Memory scrubbing]]

* [[Memory management unit|MMU]]

* [[Address generation unit]]

* [[Memory scrubbing]]

* [[Multi-channel memory architecture]]

* [[Storage controller]]

== References ==

{{Reflist|30em}}

== External links ==

* [{{web archive |url=https://web.archive.org/web/20110929024052/http://www.kingston.com/newtech/MKF_520DDRwhitepaper.pdf |title=Infineon/Kingston (a memory vendor) Dual Channel DDR Memory Whitepaper]}}{{snd}} explains dual channel memory controllers, and how to use them

* [https://www.utmel.com/blog/categories/memory%20chip/what-is-a-memory-controller/ Introduction to Memory Controller]

* [https://www.intel.com/content/www/us/en/support/articles/000005657/boards-and-kits.html Intel guide on Single- and Multichannel Memory Modes]{{dead link|date=January 2025}}

* [https://www.embedic.com/technology/details/what-is-a-memory-controller What is a Memory Controller and How Does it Work]

* [https://www.jotrin.com/technology/details/what-is-memory-controller What is Memory Controller?]

* [https://www.lisleapex.com/blog-memory-controllers-history-and-how-it-work Memory Controllers:History and How it Work] {{sic}}

* [https://www.dyethin.com/blog/industry/what-is-a-flash-memory-everything-you-need-to-know! Flash Memory: Types and Development History]{{dead link|date=January 2025}}

{{CPU technologies}}