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[[File:Intel_82PM45_Memory_Controller_Hub_-_MCH_AC82PM45-SLB97_-3718.jpg | thumb|right | Intel 82PM45 Memory Controller Hub]]
A '''memory controller''', also known as '''memory chip controller''' ('''MCC''') or a '''memory controller unit''' ('''MCU'''), is a digital circuit that manages the flow of data going to and from a computer's [[main memory]].<ref>Comptia A+ Certification Exam Guide, Seventh Edition, by Mike Meyers, in the glossary, bottom of page 1278: "Chip that handles memory requests from the CPU."</ref><ref>{{cite book |last1=Neat |first1=Adam G. |url=https://books.google.com/books?id=PJ49xcoRb1QC&q=%22memory+controller+unit%22&pg=PA100 |title=Maximizing Performance and Scalability with IBM WebSphere |date=2003-12-04 |publisher=Apress |isbn=9781590591307 |access-date=6 February 2015}}</ref> When a memory controller is integrated into another chip, such as an integral part of a [[microprocessor]], it is usually called an '''integrated memory controller''' ('''IMC''').
Memory controllers contain the logic necessary to read and write to [[dynamic random-access memory]] (DRAM), and to provide the critical [[memory refresh]] and other functions. Reading and writing to DRAM is performed by selecting the row and column data addresses of the DRAM as the inputs to the [[multiplexer]] circuit, where the [[demultiplexer]] on the DRAM uses the converted inputs to select the correct memory ___location and return the data, which is then passed back through a multiplexer to consolidate the data in order to reduce the required [[Bus (computing)|bus]] width for the operation. Memory controllers' bus widths range from [[8-bit]] in earlier systems, to 512-bit in more complicated systems, where they are typically implemented as four [[64-bit]] simultaneous memory controllers operating in parallel, though some operate with two 64-bit memory controllers being used to access a [[128-bit]] memory device.
Some memory controllers, such as the one integrated into [[PowerQUICC]] II processors, include [[error detection and correction]] hardware.<ref>[http://www.freescale.com/files/training_pdf/24815_PQ2_MEM_CONTROL_WBT.pdf "Memory Controller"]</ref> Many modern processors are also integrated [[memory management unit]] (MMU), which in many [[operating system]]s implements [[virtual addressing]]. On early x86-32 processors, the MMU is integrated in the CPU, but the
== History ==
Older Intel and [[PowerPC]]-based computers have memory controller chips that are separate from the main processor. Often these are integrated into the [[Northbridge (computing)|northbridge]] of the computer, also sometimes called a memory controller hub.
{{Anchor|IMC}}Most modern desktop or workstation microprocessors use an '''integrated memory controller''' ('''IMC'''), including microprocessors from [[Intel]], [[AMD]], and those built around the [[ARM architecture]]. Prior to [[AMD K8|K8]] (circa 2003), [[AMD]] microprocessors had a memory controller implemented on their motherboard's [[
While an integrated memory controller has the potential to increase the system's performance, such as by reducing [[memory latency]], it locks the microprocessor to a specific type (or types) of memory, forcing a redesign in order to support newer memory technologies. When [[DDR2 SDRAM]] was introduced, AMD released new [[Athlon 64]] CPUs. These new models, with a DDR2 controller, use a different physical socket (known as [[Socket AM2]]), so that they will only fit in motherboards designed for the new type of RAM. When the memory controller is not on-die, the same CPU may be installed on a new motherboard, with an updated northbridge to use newer memory.
Some microprocessors in the 1990s, such as the DEC [[Alpha 21066]] and HP [[PA-7300LC]], had integrated memory controllers; however, rather than for performance gains, this was implemented to reduce the cost of systems by eliminating the need for an external memory controller.{{
Some CPUs are designed to have their memory controllers as dedicated external components that are not part of the chipset. An example is IBM [[POWER8]], which uses external [[Centaur (computing)|Centaur]] chips that are mounted onto [[DIMM]] modules and act as memory buffers, [[L4 cache]] chips, and as the actual memory controllers. The first version of the Centaur chip used DDR3 memory but an updated version was later released which can use DDR4.<ref>{{cite web|url=https://www.itjungle.com/2016/10/17/tfh101716-story02/|title=IBM Brings DDR4 Memory To Bear On Power Systems|last=Prickett Morgan|first=Timothy|date=2016-10-17|website=IT Jungle|pages=1|access-date=2017-09-07}}</ref>
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ASUS and Intel have their separate memory scrambling standards. ASUS motherboards have allowed the user to choose which memory scrambling standard to use (ASUS or Intel) or whether to turn the feature off entirely.{{
== Variants ==
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* {{web archive |url=https://web.archive.org/web/20110929024052/http://www.kingston.com/newtech/MKF_520DDRwhitepaper.pdf |title=Infineon/Kingston (a memory vendor) Dual Channel DDR Memory Whitepaper}}{{snd}} explains dual channel memory controllers, and how to use them
* [https://www.utmel.com/blog/categories/memory%20chip/what-is-a-memory-controller/ Introduction to Memory Controller]
* [https://www.intel.com/content/www/us/en/support/articles/000005657/boards-and-kits.html Intel guide on Single- and Multichannel Memory Modes]{{
* [https://www.embedic.com/technology/details/what-is-a-memory-controller What is a Memory Controller and How Does it Work]
* [https://www.jotrin.com/technology/details/what-is-memory-controller What is Memory Controller?]
* [https://www.lisleapex.com/blog-memory-controllers-history-and-how-it-work Memory Controllers:History and How it Work] {{sic}}
* [https://www.dyethin.com/blog/industry/what-is-a-flash-memory-everything-you-need-to-know! Flash Memory: Types and Development History]{{
{{CPU technologies}}
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