Memory controller: Difference between revisions

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The{{Short '''memorydescription|Digital controller'''circuit is a chip on a computer's [[motherboard]] or CPU die whichthat manages the flow of data going to and from the [[randomcomputer's accessmain memory|memory]]. }}

{{Update|date=August 2022}}

[[File:Intel_82PM45_Memory_Controller_Hub_-_MCH_AC82PM45-SLB97_-3718.jpg | thumb|right | Intel 82PM45 Memory Controller Hub]]

Memory controllers contain the logic necessary to read and write [[dynamic RAM]], and to "refresh" the DRAM by sending current through the entire device. Without constant refreshes, DRAM will lose the data written to it as the capacitors leak their current within a number of milliseconds (64 milliseconds according to [[JEDEC]] standards).

A '''memory controller''', also known as '''memory chip controller''' ('''MCC''') or a '''memory controller unit''' ('''MCU'''), is a digital circuit that manages the flow of data going to and from a computer's [[main memory]].<ref>Comptia A+ Certification Exam Guide, Seventh Edition, by Mike Meyers, in the glossary, bottom of page 1278: "Chip that handles memory requests from the CPU."</ref><ref>{{cite book |last1=Neat |first1=Adam G. |url=https://books.google.com/books?id=PJ49xcoRb1QC&q=%22memory+controller+unit%22&pg=PA100 |title=Maximizing Performance and Scalability with IBM WebSphere |date=2003-12-04 |publisher=Apress |isbn=9781590591307 |access-date=6 February 2015}}</ref> When a memory controller is integrated into another chip, such as an integral part of a [[microprocessor]], it is usually called an '''integrated memory controller''' ('''IMC''').

ReadingMemory andcontrollers writingcontain tothe DRAMlogic isnecessary facilitatedto byread useand ofwrite to [[multiplexerdynamic random-access memory]]s (DRAM), and to provide the critical [[demultiplexermemory refresh]]s, and other functions. Reading and writing to DRAM is performed by selecting the correct row and column addressdata addresses of the DRAM as the inputs to the [[multiplexer]] circuit, where the [[demultiplexer]] on the DRAM canuses the converted inputs to select the correct memory ___location and return the data, (oncewhich againis then passed back through a multiplexer to reduceconsolidate the numberdata ofin wires necessaryorder to assemblereduce the systemrequired [[Bus (computing)|bus]] width for the operation. Memory controllers' bus widths range from [[8-bit]] in earlier systems, to 512-bit in more complicated systems, where they are typically implemented as four [[64-bit]] simultaneous memory controllers operating in parallel, though some operate with two 64-bit memory controllers being used to access a [[128-bit]] memory device.

Some memory controllers, such as the one integrated into [[PowerQUICC]] II processors, include [[error detection and correction]] hardware.<ref>[http://www.freescale.com/files/training_pdf/24815_PQ2_MEM_CONTROL_WBT.pdf "Memory Controller"]</ref> Many modern processors are also integrated [[memory management unit]] (MMU), which in many [[operating system]]s implements [[virtual addressing]]. On early x86-32 processors, the MMU is integrated in the CPU, but the memory controller is usually part of [[northbridge (computing)|northbridge]].<ref>{{Cite web | title=Archived copy | url=https://vikramuniv.ac.in/files/academic/e-Resources2020-21/engg2020-21/BE_6_SEM_EE_MP_MC-_COMP._OF_8086_FAMILY-AMIT_THAKUR-converted-converted.pdf | archive-url=https://web.archive.org/web/20250704122950/https://vikramuniv.ac.in/files/academic/e-Resources2020-21/engg2020-21/BE_6_SEM_EE_MP_MC-_COMP._OF_8086_FAMILY-AMIT_THAKUR-converted-converted.pdf | archive-date=2025-07-04}}</ref>

Bus width is the measure of how many parallel lanes of traffic are available to communicate with the memory cell. Memory controllers bus width ranges from 8-bit in earlier systems, to 256-bit systems in more complicated systems and video cards (typically implemented as four, 64-bit simultaneous memory controllers operating in parallel, though some are designed to operate in "gang mode" where two 64-bit memory controllers can be used to access a 128-bit memory device).

== History ==

'''Dual Data Rate'''(DDR) memory controllers are used to drive [[DDR SDRAM]], where data is transfered on the rising and falling access of the memory clock of the system. DDR memory controllers are significantly more complicated than Single Data Rate controllers, but allow for twice the data to be transfered without increasing the clock rate or increasing the bus width to the memory cell.

Older Intel and [[PowerPC]]-based computers have memory controller chips that are separate from the main processor. Often these are integrated into the [[Northbridge (computing)|northbridge]] of the computer, also sometimes called a memory controller hub.

{{Anchor|IMC}}Most modern desktop or workstation microprocessors use an '''integrated memory controller''' ('''IMC'''), including microprocessors from [[Intel]], [[AMD]], and those built around the [[ARM architecture]]. Prior to [[AMD K8|K8]] (circa 2003), [[AMD]] microprocessors had a memory controller implemented on their motherboard's [[Northbridge (computing)|northbridge]]. In K8 and later, AMD employed an integrated memory controller.<ref>{{Cite web|url=http://www.chip-architect.com/news/2001_10_02_Hammer_microarchitecture.html|title=Chip Architect: AMD's Next Generation Micro Processor's Architecture|last=Vries|first=Hans de|website=www.chip-architect.com|access-date=2018-03-17}}</ref> Likewise, until [[Nehalem (microarchitecture)|Nehalem]] (circa 2008), [[Intel]] microprocessors used memory controllers implemented on the motherboard's northbridge. Nehalem and later switched to an integrated memory controller.<ref>{{cite web|last1=Torres|first1=Gabriel|title=Inside Intel Nehalem Microarchitecture|url=http://www.hardwaresecrets.com/inside-intel-nehalem-microarchitecture/|website=Hardware Secrets|access-date=7 September 2017|page=2|date=2008-08-26}}</ref> Other examples of microprocessor architectures that use ''integrated memory controllers'' include [[NVIDIA]]'s [[Fermi (microarchitecture)|Fermi]], [[IBM]]'s [[POWER5]], and [[Sun Microsystems]]'s [[UltraSPARC T1]].

'''[[Dual Channel]]''' memory controllers are memory controllers where the DRAM devices are seperated onto two different busses to allow two memory controllers to access them in parallel. This doubles the theoretical amount of bandwidth of the bus. In theory, more channels can be built (a channel for every DRAM cell would be the ideal solution), but due to wire count, [[Crosstalk (electronics)|line capacitance]], and the need for parallel access lines to have identical lengths, more channels are very difficult to add.

While an integrated memory controller has the potential to increase the system's performance, such as by reducing [[memory latency]], it locks the microprocessor to a specific type (or types) of memory, forcing a redesign in order to support newer memory technologies. When [[DDR2 SDRAM]] was introduced, AMD released new [[Athlon 64]] CPUs. These new models, with a DDR2 controller, use a different physical socket (known as [[Socket AM2]]), so that they will only fit in motherboards designed for the new type of RAM. When the memory controller is not on-die, the same CPU may be installed on a new motherboard, with an updated northbridge to use newer memory.

Fully-Buffered memory systems places a memory buffer device on every [[DIMM|memory module]] (called an [[FB-DIMM]] when Fully Buffered RAM is used), which unlike traditional memory controller devices, uses a serial data link to the memory controller instead of the parallel link used in previous RAM designs. This decreases the number of the wires necessary to place the memory devices on a motherboard (allowing for a smaller number of layers to be used, meaning more memory devices can be placed on a single board), at the expense of increasing latency (the time necessary to access a memory ___location). This increase is due to the time required to convert the parallel information read from the DRAM cell to the serial format used by the FB-DIMM controller, and back to a parallel form in the memory controller on the motherboard. In theory, the FB-DIMM's memory buffer device could be built to access any DRAM cells, allowing for memory cell agnostic memory controller design, but this has not been demonstrated, as the technology is in its infancy.

Some microprocessors in the 1990s, such as the DEC [[Alpha 21066]] and HP [[PA-7300LC]], had integrated memory controllers; however, rather than for performance gains, this was implemented to reduce the cost of systems by eliminating the need for an external memory controller.{{citation needed|reason=The linked articles do mention a cost motivator but there are no supporting citations.|date=July 2024}}

As of [[2006]], most computers have a memory controller implemented on their motherboard's [[northbridge (computing)|north bridge]], though some modern [[microprocessors]], such as [[AMD]]'s Athlon 64, and [[Opteron]], [[IBM]]'s [[POWER5]], and [[Sun Microsystems]] [[UltraSPARC T1]] have a memory controller on the CPU die to reduce the [[memory latency]]. As this greatly increases the computer's performance, it locks the processor to that generation of memory, making the entire platform vulnerable to changes in memory technologies. This was witnessed in the shift to [[socket AM2]] on the Athlon 64 processor to allow the processor to use [[DDR2 SDRAM]].

Some CPUs are designed to have their memory controllers as dedicated external components that are not part of the chipset. An example is IBM [[POWER8]], which uses external [[Centaur (computing)|Centaur]] chips that are mounted onto [[DIMM]] modules and act as memory buffers, [[L4 cache]] chips, and as the actual memory controllers. The first version of the Centaur chip used DDR3 memory but an updated version was later released which can use DDR4.<ref>{{cite web|url=https://www.itjungle.com/2016/10/17/tfh101716-story02/|title=IBM Brings DDR4 Memory To Bear On Power Systems|last=Prickett Morgan|first=Timothy|date=2016-10-17|website=IT Jungle|pages=1|access-date=2017-09-07}}</ref>

== Security<span class="anchor" id="SCRAMBLING"></span> ==

A few experimental memory controllers contain a second level of address translation, in addition to the first level of address translation performed by the CPU's [[memory management unit]] to improve cache and bus performance.<ref>John Carter, Wilson Hsieh, Leigh Stoller, Mark Swansony, Lixin Zhang, et al. [http://www.cs.utah.edu/~ald/pubs/hpca99.pdf "Impulse: Building a Smarter Memory Controller"].</ref>

Memory controllers integrated into certain [[Intel Core]] processors provide '''memory scrambling''' as a feature that turns user data written to the main memory into [[pseudo-random]] patterns.<ref>{{cite web

| url = http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/2nd-gen-core-desktop-vol-1-datasheet.pdf

| title = 2nd Generation Intel Core Processor Family Desktop, Intel Pentium Processor Family Desktop, and Intel Celeron Processor Family Desktop

| date = June 2013 | access-date = 2015-11-03

| page = 23

}}</ref><ref>{{cite web

| url = http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/2nd-gen-core-family-mobile-vol-1-datasheet.pdf

| title = 2nd Generation Intel Core Processor Family Mobile and Intel Celeron Processor Family Mobile

| date = September 2012 | access-date = 2015-11-03

| page = 24

}}</ref> Memory scrambling has the potential to prevent [[Computer forensics|forensic]] and [[reverse-engineering]] analysis based on [[DRAM data remanence]] by effectively rendering various types of [[cold boot attack]]s ineffective. In current practice, this has not been achieved; memory scrambling has only been designed to address DRAM-related electrical problems. The late 2010s memory scrambling standards do address security issues and are not cryptographically secure or open to public revision or analysis.<ref>{{cite web

| url = http://www.slideshare.net/codeblue_jp/igor-skochinsky-enpub

| title = Secret of Intel Management Engine

| date = 2014-03-12 | access-date = 2014-07-13

| author = Igor Skochinsky | website = SlideShare

| pages = 26&ndash;29

}}</ref>

ASUS and Intel have their separate memory scrambling standards. ASUS motherboards have allowed the user to choose which memory scrambling standard to use (ASUS or Intel) or whether to turn the feature off entirely.{{citation needed|date=September 2024}}

== Variants ==

=== Double data rate memory ===

'''Dual[[Double Datadata rate]] Rate'''(DDR) memory controllers are used to drive [[DDR SDRAM]], where data is transferedtransferred on theboth rising and falling accessedges of the system's memory clock of the system. DDR memory controllers are significantly more complicated thanwhen Singlecompared Datato Ratesingle data rate controllers,{{Citation needed| reason= Why would it be significantly more complicated - provide reliable source if possible | date=April 2018}} but they allow for twice the data to be transferedtransferred without increasing the memory's clock rate or increasing the bus width to the memory cell.

=== Multichannel memory ===

{{Main|Multi-channel memory architecture}}

'''[[Dual Channel]]'''Multichannel memory controllers are memory controllers where the DRAM devices are seperatedseparated onto twomultiple different bussesbuses to allow twothe memory controllerscontroller(s) to access them in parallel. This doublesincreases the theoretical amount of bandwidth of the bus. Inby theory,a morefactor channelsof canthe benumber builtof channels. While (a channel for every DRAM cell would be the ideal solution), but due to wire count, [[Crosstalk (electronics)|line capacitance]], and the need for parallel access lines to have identical lengths,adding more channels areincreases verycomplexity difficultand to addcost.

=== Fully buffered memory ===

{{Main|Fully Buffered DIMM}}

Fully-Buffered buffered memory systems placesplace a memory buffer device on every [[DIMM|memory module]] (called an [[FB-DIMM]] when Fullyfully Bufferedbuffered RAM is used), which unlike traditional memory controller devices, usesuse a serial data link to the memory controller instead of the parallel link used in previous RAM designs. This decreases the number of the wires necessary to place the memory devices on a motherboard (allowing for a smaller number of layers to be used, meaning more memory devices can be placed on a single board), at the expense of increasing latency (the time necessary to access a memory ___location). This increase is due to the time required to convert the parallel information read from the DRAM cell to the serial format used by the FB-DIMM controller, and back to a parallel form in the memory controller on the motherboard. In theory, the FB-DIMM's memory buffer device could be built to access any DRAM cells, allowing for memory cell agnostic memory controller design, but this has not been demonstrated, as the technology is in its infancy.

=== Flash memory controller ===

{{Main|Flash memory controller}}

Many [[flash memory]] devices, such as [[USB flash drive]]s and [[solid-state drive]]s, include a [[flash memory controller]]. Flash memory is inherently slower to access than RAM and often becomes unusable after a few million write cycles, which generally makes it unsuitable for RAM applications.

== See also ==

* [[Address generation unit]]

* [[Memory scrubbing]]

* [[Storage controller]]

== References ==

{{Reflist}}

== External links ==

* {{web archive |url=https://web.archive.org/web/20110929024052/http://www.kingston.com/newtech/MKF_520DDRwhitepaper.pdf |title=Infineon/Kingston (a memory vendor) Dual Channel DDR Memory Whitepaper}}{{snd}} explains dual channel memory controllers, and how to use them

* [https://www.utmel.com/blog/categories/memory%20chip/what-is-a-memory-controller/ Introduction to Memory Controller]

* [https://www.intel.com/content/www/us/en/support/articles/000005657/boards-and-kits.html Intel guide on Single- and Multichannel Memory Modes]{{dead link|date=January 2025}}

* [https://www.embedic.com/technology/details/what-is-a-memory-controller What is a Memory Controller and How Does it Work]

* [https://www.jotrin.com/technology/details/what-is-memory-controller What is Memory Controller?]

* [https://www.lisleapex.com/blog-memory-controllers-history-and-how-it-work Memory Controllers:History and How it Work] {{sic}}

* [https://www.dyethin.com/blog/industry/what-is-a-flash-memory-everything-you-need-to-know! Flash Memory: Types and Development History]{{dead link|date=January 2025}}

{{CPU technologies}}

{{computer-stub}}

[[Category:Computer memory]]

[[Category:Integrated circuits]]