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{{Memory types}}
[[File:SDRAM_memory_module.jpg|thumb|SDRAM memory module]]
'''Synchronous dynamic random-access memory''' ('''synchronous dynamic RAM''' or '''SDRAM''') is any [[Dynamic
DRAM [[integrated circuit]]s (ICs) produced from the early 1970s to the early 1990s used an ''asynchronous'' interface, in which input control signals have a direct effect on internal functions
[[Pipeline (computing)|Pipelining]] means that the chip can accept a new command before it has finished processing the previous one. For a pipelined write, the write command can be immediately followed by another command without waiting for the data to be written into the memory array. For a pipelined read, the requested data appears a fixed number of clock cycles (latency) after the read command, during which additional commands can be sent.
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[[Image:SDR SDRAM-1.jpg|thumb|Eight [[Hyundai Electronics|Hyundai]] SDRAM ICs on a PC100 [[DIMM]] package]]
The earliest DRAMs were often synchronized with the CPU clock (clocked) and were used with early microprocessors. In the mid-1970s, DRAMs moved to the asynchronous design, but in the 1990s returned to synchronous operation.<ref>{{cite book | author=P. Darche | title=Microprocessor: Prolegomenes
The first commercial SDRAM was the [[Samsung]] KM48SL2000 [[memory chip]], which had a capacity of 16{{nbsp}}Mbit.<ref name="electronic-design">{{cite journal|date=1993|title=Electronic Design|url=https://books.google.com/books?id=QmpJAQAAIAAJ|journal=[[Electronic Design]]|publisher=Hayden Publishing Company|volume=41|issue=15–21|quote=The first commercial synchronous DRAM, the Samsung 16-Mbit KM48SL2000, employs a single-bank architecture that lets system designers easily transition from asynchronous to synchronous systems.}}</ref> It was manufactured by [[Samsung Electronics]] using a [[CMOS]] (complementary [[metal–oxide–semiconductor]]) [[fabrication process]] in 1992,<ref name="KM48SL2000"/> and mass-produced in 1993.<ref name="electronic-design"/> By 2000, SDRAM had replaced virtually all other types of [[DRAM]] in modern
SDRAM latency is not inherently lower (faster access times) than asynchronous DRAM. Indeed, early SDRAM was somewhat slower than contemporaneous [[burst EDO DRAM]] due to the additional logic. The benefits of SDRAM's internal buffering come from its ability to interleave operations to multiple banks of memory, thereby increasing effective [[Bandwidth (computing)|bandwidth]].
[[Double data rate]] SDRAM, known as [[DDR SDRAM]], was first demonstrated by Samsung in 1997.<ref name="techpowerup">{{cite web |title=Samsung 30 nm Green PC3-12800 Low Profile 1.35 V DDR3 Review |url=https://www.techpowerup.com/review/samsung-mv-3v4g3/ |website=TechPowerUp |access-date=25 June 2019 |date= March 8, 2012}}</ref> Samsung released the first commercial DDR SDRAM chip (64{{nbsp}}Mbit{{binpre}}) in June 1998,<ref name="samsung99"/><ref name="samsung98"/><ref name="phys"/> followed soon after by [[Hyundai Electronics]] (now [[SK Hynix]]) the same year.<ref name="hynix90s"/>
Today, virtually all SDRAM is manufactured in compliance with standards established by [[JEDEC]], an electronics industry association that adopts [[open standards]] to facilitate interoperability of electronic components. JEDEC formally adopted its first SDRAM standard in 1993 and subsequently adopted other SDRAM standards, including those for [[DDR SDRAM|DDR]], [[DDR2 SDRAM|DDR2]] and [[DDR3 SDRAM]].
SDRAM is also available in [[Registered memory|registered]] varieties, for systems that require greater scalability such as [[Server (computing)|server]]s and [[workstations]].
Today, the world's largest manufacturers of SDRAM include
== Timing ==
There are several limits on DRAM performance. Most noted is the read cycle time, the time between successive read operations to an open row. This time decreased from
Another limit is the [[CAS latency]], the time between supplying a column address and receiving the corresponding data. Again, this has remained relatively constant at 10–15 ns through the last few generations of DDR SDRAM.
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In operation, CAS latency is a specific number of clock cycles programmed into the SDRAM's mode register and expected by the DRAM controller. Any value may be programmed, but the SDRAM will not operate correctly if it is too low. At higher clock rates, the useful CAS latency in clock cycles naturally increases. 10–15 ns is 2–3 cycles (CL2–3) of the 200 MHz clock of DDR-400 SDRAM, CL4-6 for DDR2-800, and CL8-12 for DDR3-1600. Slower clock cycles will naturally allow lower numbers of CAS latency cycles.
SDRAM modules have their own timing specifications, which may be slower than those of the chips on the module. When 100 MHz SDRAM chips first appeared, some manufacturers sold "100 MHz" modules that could not reliably operate at that clock rate. In response, Intel published the PC100 standard, which outlines requirements and guidelines for producing a memory module that can operate reliably at 100 MHz. This standard was widely influential, and the term "PC100" quickly became a common identifier for 100 MHz SDRAM modules, and modules are now commonly designated with "PC"-prefixed numbers (PC66, PC100 or PC133
== Control signals ==
All commands are timed relative to the rising edge of a clock signal. In addition to the clock, there are six control signals, mostly [[Logic level|active low]], which are sampled on the rising edge of the clock:
* '''CKE''' clock enable. When this signal is low, the chip behaves as if the clock has stopped. No commands are interpreted and command latency times do not elapse. The state of other control lines is not relevant. The effect of this signal is actually delayed by one clock cycle.
* '''{{overline|CS}}''' chip select.
* '''DQM''' data mask.
=== Command signals ===
* '''{{overline|RAS}}''', row address strobe.
* '''{{overline|CAS}}''', column address strobe.
* '''{{overline|WE}}''', write enable.
=== Bank selection (BAn) ===
SDRAM devices are internally divided into either two, four or eight independent internal data banks.
=== Addressing (A10/An) ===
Many commands also use an address presented on the address input pins.
=== Commands ===
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|bgcolor=#ccffcc| L ||bgcolor=#ccffcc| L ||bgcolor=#ffcccc| H ||bgcolor=#ccffcc| L ||bgcolor=lightgrey| x ||bgcolor=#ffcccc| H ||bgcolor=lightgrey| x ||align="left"| Precharge all: deactivate (close) the current row of all banks
|-
|bgcolor=#ccffcc| L ||bgcolor=#ccffcc| L ||bgcolor=#ccffcc| L ||bgcolor=#ffcccc| H ||bgcolor=lightgrey| x ||bgcolor=lightgrey| x ||bgcolor=lightgrey| x ||align="left"| Auto refresh: refresh one row of each bank, using an internal counter.
|-
|bgcolor=#ccffcc| L ||bgcolor=#ccffcc| L ||bgcolor=#ccffcc| L ||bgcolor=#ccffcc| L || 0 0 ||colspan="2"| mode ||align="left"| Load mode register: A0 through A9 are loaded to configure the DRAM chip.<br/>The most significant settings are CAS latency (2 or 3 cycles) and burst length (1, 2, 4 or 8 cycles)
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* Additional extended mode registers (selected by the bank address bits)
* DDR2 deletes the burst terminate command; DDR3 reassigns it as "ZQ calibration"
* DDR3 and DDR4
* [[DDR4#Command encoding|DDR4 changes the encoding]] of the activate command.
== Construction and operation==
[[File:SDRAM_memory_module,_zoomed.jpg|thumb|SDRAM [[memory module]], zoomed]]
The ''active'' command activates an idle bank.
Once the row has been activated or "opened", ''read'' and ''write'' commands are possible to that row. Activation requires a minimum amount of time, called the row-to-column delay, or t<sub>RCD</sub> before reads or writes to it may occur.
Both ''read'' and ''write'' commands require a column address. Because each chip accesses eight bits of data at a time, there are 2,048 possible column addresses thus requiring only 11 address lines (A0–A9, A11).
When a ''read'' command is issued, the SDRAM will produce the corresponding output data on the DQ lines in time for the rising edge of the clock a few clock cycles later, depending on the configured CAS latency.
A ''write'' command is accompanied by the data to be written driven on to the DQ lines during the same rising clock edge. It is the duty of the memory controller to ensure that the SDRAM is not driving read data on to the DQ lines at the same time that it needs to drive write data on to those lines.
When the memory controller needs to access a different row, it must first return that bank's sense amplifiers to an idle state, ready to sense the next row.
Although refreshing a row is an automatic side effect of activating it, there is a minimum time for this to happen, which requires a minimum row access time t<sub>RAS</sub> delay between an ''active'' command opening a row, and the corresponding precharge command closing it.
== Command interactions ==
The no operation command is always permitted, while the load mode register command requires that all banks be idle, and a delay afterward for the changes to take effect.
When a bank is open, there are four commands permitted: read, write, burst terminate, and precharge.
=== Interrupting a read burst ===
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== {{Anchor|BURST}} Burst ordering ==
A modern microprocessor with a [[CPU cache|cache]] will generally access memory in units of [[cache line]]s.
Bursts always access an aligned block of BL consecutive words beginning on a multiple of BL. So, for example, a four-word burst access to any column address from four to seven will return words four to seven. The ordering, however, depends on the requested address, and the configured burst type option: sequential or interleaved. Typically, a memory controller will require one or the other. When the burst length is one or two, the burst type does not matter. For a burst length of one, the requested word is the only word accessed. For a burst length of two, the requested word is accessed first, and the other word in the aligned block is accessed second.
For the sequential [[Burst mode (computing)|burst mode]], later words are accessed in increasing address order, wrapping back to the start of the block when the end is reached. So, for example, for a burst length of four, and a requested column address of five, the words would be accessed in the order 5-6-7-4. If the burst length were eight, the access order would be 5-6-7-0-1-2-3-4. This is done by adding a counter to the column address, and ignoring carries past the burst length. The interleaved burst mode computes the address using an [[exclusive or]] operation between the counter and the address.
| url = http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/nanya-nt5ds-datasheet.pdf#page=13
| title = Nanya 256 Mb DDR SDRAM Datasheet
| date = April 2003 | access-date = 2015-08-02
| website = intel.com
}}</ref>
If the requested column address is at the start of a block, both burst modes (sequential and interleaved) return data in the same sequential sequence 0-1-2-3-4-5-6-7. The difference only matters if fetching a cache line from memory in critical-word-first order.
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* M8, M7: Operating mode. Reserved, and must be 00.
* M6, M5, M4: CAS latency. Generally only 010 (CL2) and 011 (CL3) are legal. Specifies the number of cycles between a read command and data output from the chip. The chip has a fundamental limit on this value in nanoseconds; during initialization, the memory controller must use its knowledge of the clock frequency to translate that limit into cycles.
* M3: Burst type. 0
* M2, M1, M0: Burst length. Values of 000, 001, 010 and 011 specify a burst size of 1, 2, 4 or 8 words, respectively. Each read (and write, if M9 is 0) will perform that many accesses, unless interrupted by a burst stop or other command. A value of 111 specifies a full-row burst.
Later (double data rate) SDRAM standards use more mode register bits, and provide additional mode registers called "extended mode registers". The register number is encoded on the bank address pins during the load mode register command. For example, DDR2 SDRAM has a 13-bit mode register, a 13-bit extended mode register No. 1 (EMR1), and a 5-bit extended mode register No. 2 (EMR2).
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== Low power modes ==
As mentioned, the clock enable (CKE) input can be used to effectively stop the clock to an SDRAM.
If CKE is lowered while the SDRAM is performing operations, it simply "freezes" in place until CKE is raised again.
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Finally, if CKE is lowered at the same time as an auto-refresh command is sent to the SDRAM, the SDRAM enters self-refresh mode. This is like power down, but the SDRAM uses an on-chip timer to generate internal refresh cycles as necessary. The clock may be stopped during this time. While self-refresh mode consumes slightly more power than power-down mode, it allows the memory controller to be disabled entirely, which commonly more than makes up the difference.
SDRAM designed for battery-powered devices offers some additional power-saving options. One is temperature-dependent refresh; an on-chip temperature sensor reduces the refresh rate at lower temperatures, rather than always running it at the worst-case rate.
== {{Anchor|PREFETCH}} DDR SDRAM prefetch architecture==
DDR SDRAM employs prefetch architecture to allow quick and easy access to multiple [[data word]]s located on a common physical row in the memory.
The prefetch architecture takes advantage of the specific characteristics of memory accesses to DRAM. Typical DRAM memory operations involve three phases: [[bitline]] precharge, row access, column access. Row access is the heart of a read operation, as it involves the careful sensing of the tiny signals in DRAM memory cells; it is the slowest phase of memory operation. However, once a row is read, subsequent column accesses to that same row can be very quick, as the sense amplifiers also act as latches. For reference, a row of a 1 [[Gigabit|Gbit]]{{binpre}} [[DDR3]] device is 2,048 [[bit]]s wide, so internally 2,048 bits are read into 2,048 separate sense amplifiers during the row access phase.
Traditional DRAM architectures have long supported fast column access to bits on an open row. For an 8-bit-wide memory chip with a 2,048 bit wide row, accesses to any of the 256 datawords (2048/8) on the row can be very quick, provided no intervening accesses to other rows occur.
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The drawback of the older fast column access method was that a new column address had to be sent for each additional dataword on the row. The address bus had to operate at the same frequency as the data bus. Prefetch architecture simplifies this process by allowing a single address request to result in multiple data words.
In a prefetch buffer architecture, when a memory access occurs to a row the buffer grabs a set of adjacent data words on the row and reads them out ("bursts" them) in rapid-fire sequence on the IO pins, without the need for individual column address requests. This assumes the CPU wants adjacent datawords in memory, which in practice is very often the case.
The prefetch buffer depth can also be thought of as the ratio between the core memory frequency and the IO frequency.
Each generation of SDRAM has a different prefetch buffer size:
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* [[DDR3 SDRAM]]'s prefetch buffer size is 8n (eight datawords per memory access)
* [[DDR4 SDRAM]]'s prefetch buffer size is 8n (eight datawords per memory access)
* [[DDR5 SDRAM]]'s prefetch buffer size is 8n; there is an additional mode of 16n
== Generations ==
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! scope="row" | SDRAM
| {{Unbulleted list
| {{Nowrap|V{{Sub|cc}} {{=}} 3.3
| Signal: [[Transistor–transistor logic#Sub-types|LVTTL]]
}}
|-
! scope="row" |
| {{Unbulleted list
| Access is
| [[Double data rate|Double clocked]]
| {{Nowrap|V{{Sub|cc}} {{=}} 2.5
| {{Nowrap|2.5
| Signal: [[Stub Series Terminated Logic|SSTL_2]] (2.
}}
|-
! scope="row" |
| Access is
|-
! scope="row" |
| Access is
|-
! scope="row" |
| {{Nowrap|V{{Sub|cc}} ≤
|}
=== SDR ===
[[Image:Micron 48LC32M8A2-AB.jpg|thumb|upright=1.25|The 64 MB{{binpre}} of sound memory on the [[Sound Blaster X-Fi|Sound Blaster X-Fi Fatality Pro]] [[sound card]] is built from
Originally simply known as ''SDRAM'', single data rate SDRAM can accept one command and transfer one word of data per clock cycle. Chips are made with a variety of data bus sizes (most commonly 4, 8 or 16 bits), but chips are generally assembled into 168-pin [[DIMM]]s that read or write 64 (non-ECC) or 72 ([[ECC memory|ECC]]) bits at a time.
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==== PC66 ====
'''PC66''' refers to internal removable computer [[random-access memory|memory]] standard defined by the [[Joint Electron Device Engineering Council|JEDEC]]. PC66 is Synchronous DRAM operating at a clock frequency of 66.66 MHz, on a 64-bit bus, at a voltage of 3.3 V. PC66 is available in 168-pin [[DIMM]] and 144-pin [[SO-DIMM]] form factors. The theoretical bandwidth is 533 MB/s. (1
This standard was used by [[Original Intel Pentium (P5 microarchitecture)|Intel Pentium]] and [[AMD K6]]-based PCs. It also features in the Beige [[Power Mac G3]], early [[iBook]]s and [[PowerBook G3]]s. It is also used in many early [[Intel Celeron]] systems with a 66 MHz [[front-side bus|FSB]]. It was superseded by the PC100 and PC133 standards.
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==== PC100 ====
{{For|the Japanese home computer|NEC PC-100}}
[[Image:
'''PC100''' is a standard for internal removable computer [[random-access memory]], defined by the [[Joint Electron Device Engineering Council|JEDEC]]. PC100 refers to Synchronous DRAM operating at a clock frequency of 100 MHz, on a 64-bit-wide bus, at a voltage of 3.3 V. PC100 is available in 168-pin [[DIMM]] and 144-pin [[SO-DIMM]] [[Computer form factor|form factor]]s.
A module built out of 100 MHz SDRAM chips is not necessarily capable of operating at 100 MHz.
==== PC133 ====
'''PC133''' is a computer memory standard defined by the [[Joint Electron Device Engineering Council|JEDEC]]. PC133 refers to [[SDR SDRAM]] operating at a clock frequency of 133 MHz, on a 64-bit-wide bus, at a voltage of 3.3 V. PC133 is available in 168-pin [[DIMM]] and 144-pin [[SO-DIMM]] form factors. PC133 is the fastest and final SDR SDRAM standard ever approved by the JEDEC, and delivers a bandwidth of 1.066 GB per second ([133.33 MHz * 64/8]=1.066 GB/s). (1
=== {{Anchor|DDR1}} DDR ===
{{Main|DDR SDRAM}}
While the access latency of DRAM is fundamentally limited by the DRAM array, DRAM has very high potential bandwidth because each internal read is actually a row of many thousands of bits.
DDR SDRAM (sometimes called ''DDR1'' for greater clarity) doubles the minimum read or write unit; every access refers to at least two consecutive words.
Typical DDR SDRAM clock rates are 133, 166 and 200 MHz (7.5, 6, and 5 ns/cycle), generally described as DDR-266, DDR-333 and DDR-400 (3.75, 3, and 2.5 ns per beat).
=== DDR2 ===
{{Main|DDR2 SDRAM}}
DDR2 SDRAM is very similar to DDR SDRAM, but doubles the minimum read or write unit again, to four consecutive words.
Typical DDR2 SDRAM clock rates are 200, 266, 333 or 400 MHz (periods of 5, 3.75, 3 and 2.5 ns), generally described as DDR2-400, DDR2-533, DDR2-667 and DDR2-800 (periods of 2.5, 1.875, 1.5 and 1.25 ns).
Note that because internal operations are at 1/2 the clock rate, DDR2-400 memory (internal clock rate 100 MHz) has somewhat higher latency than DDR-400 (internal clock rate 200 MHz).
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{{Main|DDR3 SDRAM}}
DDR3 continues the trend, doubling the minimum read or write unit to eight consecutive words.
Again, with every doubling, the downside is the increased [[Latency (engineering)|latency]]. As with all DDR SDRAM generations, commands are still restricted to one clock edge and command latencies are given in terms of clock cycles, which are half the speed of the usually quoted transfer rate (a [[CAS latency]] of 8 with DDR3-800 is 8/(400 MHz) = 20 ns, exactly the same latency of CAS2 on PC100 SDR SDRAM).
DDR3 memory chips are being made commercially,<ref>{{cite web|url=http://www.simmtester.com/page/news/showpubnews.asp?num=145|title=What is DDR memory?}}</ref> and computer systems using them were available from the second half of 2007,<ref>{{cite news|url=http://www.tomshardware.com/2007/06/05/pipe_dreams_six_p35-ddr3_motherboards_compared/|title=Pipe Dreams: Six P35-DDR3 Motherboards Compared |date=June 5, 2007 |author=Thomas Soderstrom |newspaper=Tom's Hardware}}</ref> with significant usage from 2008 onwards.<ref>{{cite web|url=http://news.softpedia.com/news/AMD-to-Adopt-DDR3-in-Three-Years-13486.shtml|title=AMD to Adopt DDR3 in Three Years|date=28 November 2005}}</ref> Initial clock rates were 400 and 533 MHz, which are described as DDR3-800 and DDR3-1066 (PC3-6400 and PC3-8500 modules), but 667 and 800 MHz, described as DDR3-1333 and DDR3-1600 (PC3-10600 and PC3-12800 modules) are now common.<ref>{{cite web|url=http://www.anandtech.com/printarticle.aspx?i=3045|archive-url=https://archive.today/20120719141605/http://www.anandtech.com/printarticle.aspx?i=3045|url-status=dead|archive-date=July 19, 2012|title=Super Talent & TEAM: DDR3-1600 Is Here! |date=July 20, 2007 |author=Wesly Fink |publisher=Anandtech}}</ref> Performance up to DDR3-2800 (PC3 22400 modules) are available.<ref>{{cite web |url=http://hothardware.com/News/GSKILL-Announces-DDR3-Memory-Kit-For-Ivy-Bridge/ |title=G.SKILL Announces DDR3 Memory Kit For Ivy Bridge |date=24 April 2012 |author=Jennifer Johnson}}</ref>
=== DDR4 ===
{{Main|DDR4 SDRAM}}
DDR4 SDRAM is the successor to [[DDR3 SDRAM]]. It was revealed at the [[Intel Developer Forum]] in San Francisco in 2008, and was due to be released to market during 2011. The timing varied considerably during its development
The DDR4 chips run at 1.2 [[Volt|V]] or less,<ref>{{cite web|url=http://www.pcpro.co.uk/news/220257/idf-ddr3-wont-catch-up-with-ddr2-during-2009.html|title=IDF: "DDR3 won't catch up with DDR2 during 2009"|work=Alphr}}</ref><ref>{{cite web|url=http://www.heise-online.co.uk/news/IDF-DDR4-the-successor-to-DDR3-memory--/111367|title=heise online
DDR4 did ''not'' double the internal prefetch width again, but uses the same 8''n'' prefetch as DDR3.<ref name="jedec_ddr3_ddr4">{{cite press release |url=http://www.jedec.org/news/pressreleases/jedec-announces-key-attributes-upcoming-ddr4-standard |title=JEDEC Announces Key Attributes of Upcoming DDR4 Standard |publisher=[[JEDEC]] |date=2011-08-22 |access-date=2011-01-06}}</ref>
In February 2009, [[Samsung]] validated 40 nm DRAM chips, considered a "significant step" towards DDR4 development<ref>{{cite news |url=http://www.tgdaily.com/content/view/41316/139/ |title=Samsung hints to DDR4 with first validated 40 nm DRAM |last=Gruener |first=Wolfgang |date=February 4, 2009 |publisher=tgdaily.com |access-date=2009-06-16 |url-status=dead |archive-url=https://web.archive.org/web/20090524133306/http://www.tgdaily.com/content/view/41316/139/ |archive-date=May 24, 2009 }}</ref> since, as of 2009, current DRAM chips were only beginning to migrate to a 50 nm process.<ref>{{cite web |url=http://www.dailytech.com/DDR3+Will+be+Cheaper+Faster+in+2009/article13977.htm |title=DDR3 Will be Cheaper, Faster in 2009 |last=Jansen |first=Ng |date=January 20, 2009 |publisher=dailytech.com |access-date=2009-06-17 |url-status=dead |archive-url=https://web.archive.org/web/20090622084614/http://www.dailytech.com/DDR3+Will+be+Cheaper+Faster+in+2009/article13977.htm |archive-date=June 22, 2009 }}</ref> In January 2011, [[Samsung]] announced the completion and release for testing of a 30 nm 2048 MB{{binpre}} DDR4 DRAM module. It has a maximum bandwidth of 2.13 [[Gbit/s]] at 1.2 V, uses [[pseudo open drain]] technology and draws 40% less power than an equivalent DDR3 module.<ref>{{cite web |title=Samsung Develops Industry's First DDR4 DRAM, Using 30nm Class Technology |url=http://www.samsung.com/us/business/semiconductor/newsView.do?news_id=1202 |publisher=Samsung |access-date=2011-03-13 |date=2011-01-04}}</ref><ref>{{cite web |url=http://www.techspot.com/news/41818-samsung-develops-ddr4-memory-up-to-40-more-efficient.html |title=Samsung develops DDR4 memory, up to 40% more efficient |work=TechSpot|date=4 January 2011 }}</ref>
=== DDR5 ===
{{Main|DDR5 SDRAM}}
In March 2017, JEDEC announced a DDR5 standard is under development,<ref>{{cite press release |title=JEDEC DDR5 & NVDIMM-P Standards Under Development |url=https://www.jedec.org/news/pressreleases/jedec-ddr5-nvdimm-p-standards-under-development |date=30 March 2017 |publisher=[[JEDEC]]}}</ref> but provided no details except for the goals of doubling the bandwidth of DDR4, reducing power consumption, and publishing the standard in 2018. The standard was released on 14 July 2020.<ref name="anandtech-ddr5">{{cite web|url=https://www.anandtech.com/show/15912/ddr5-specification-released-setting-the-stage-for-ddr56400-and-beyond|archive-url=https://web.archive.org/web/20200714225042/https://www.anandtech.com/show/15912/ddr5-specification-released-setting-the-stage-for-ddr56400-and-beyond|url-status=dead|archive-date=July 14, 2020|title=DDR5 Memory Specification Released: Setting the Stage for DDR5-6400 And Beyond|last=Smith|first=Ryan|date=2020-07-14|website=AnandTech|access-date=2020-07-15}}</ref>
== Failed successors ==
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=== Rambus DRAM (RDRAM) ===
[[RDRAM]] was a proprietary technology that competed against DDR. Its relatively high price and disappointing performance (resulting from high latencies and a narrow 16-bit data channel versus DDR's 64 bit channel) caused it to lose the race to succeed SDR
=== Synchronous-link DRAM (SLDRAM) ===
SLDRAM boasted higher performance and competed against RDRAM. It was developed during the late 1990s by the SLDRAM Consortium. The SLDRAM Consortium consisted of about 20 major DRAM and computer industry manufacturers. (The SLDRAM Consortium became incorporated as SLDRAM Inc. and then changed its name to Advanced Memory International, Inc.)
SLDRAM used an 11-bit command bus (10 command bits CA9:0 plus one start-of-command FLAG line) to transmit 40-bit command packets on 4 consecutive edges of a differential command clock (CCLK/CCLK#).
The basic read/write command consisted of (beginning with CA9 of the first word):
{|class="wikitable" style="text-align:center"
|+ SLDRAM Read, write or row op request packet
! FLAG || CA9 || CA8 || CA7 || CA6 || CA5 || CA4 || CA3 || CA2 || CA1 || CA0
|-
! 1
|-
! 0
|colspan=
|-
! 0
|colspan=9 bgcolor=#ffffcc|
|-
! 0
|
|}
* 9 bits of
* 6 bits of
* 3 bits of
* 10 or 11 bits of row address
* 5 or 4 bits spare for row or column expansion
* 7 bits of column address
Individual devices had 8-bit IDs.
A read/write command had the msbit clear:
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A notable omission from the specification was per-byte write enables; it was designed for systems with [[CPU cache|cache]]s and [[ECC memory]], which always write in multiples of a cache line.
Additional commands (with CMD5 set) opened and closed rows without a data transfer, performed refresh operations, read or wrote configuration registers, and performed other maintenance operations.
There were a number of 8-bit control registers and 32-bit status registers to control various device timing parameters.
=== Virtual channel memory (VCM) SDRAM ===
VCM was a proprietary type of SDRAM that was designed by [[NEC]], but released as an open standard with no licensing fees.
VCM inserts an SRAM cache of 16 "channel" buffers, each 1/4 row "segment" in size, between DRAM banks' sense amplifier rows and the data I/O pins.
To read from VCSDRAM, after the active command, a "prefetch" command is required to copy data from the sense amplifier array to the channel SDRAM.
Unlike a normal SDRAM write, which must be performed to an active (open) row, the VCSDRAM bank must be precharged (closed) when the restore command is issued.
Although normally a segment is restored to the same memory address as it was prefetched from, the channel buffers may also be used for very efficient copying or clearing of large, aligned memory blocks.
The above are the JEDEC-standardized commands.
A 13-bit address bus, as illustrated here, is suitable for a device up to 128 Mbit{{binpre}}.
== {{Anchor|SGRAM}}Synchronous Graphics RAM (SGRAM) ==
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{{Main|GDDR SDRAM}}
Graphics [[double data rate]] SDRAM ([[GDDR SDRAM]]) is a type of specialized [[DDR SDRAM]] designed to be used as the main memory of [[graphics processing unit]]s (GPUs). GDDR SDRAM is distinct from commodity types of DDR SDRAM such as DDR3, although they share some core technologies. Their primary characteristics are higher clock frequencies for both the DRAM core and I/O interface, which provides greater memory bandwidth for GPUs. As of
GDDR was initially known as DDR SGRAM. It was commercially introduced as a 16{{nbsp}}[[Megabit|Mbit]]{{binpre}} memory chip by [[Samsung Electronics]] in 1998.<ref name="samsung98"/>
Line 375 ⟶ 374:
== Timeline ==
{{See also|Random-access memory#Timeline|Flash memory#Timeline|Transistor count#Memory}}{{Update section|date=December 2023|reason=Advances in DDR5 need to be included}}
=== SDRAM ===
<section begin="SDRAM timeline"/>
{| class="wikitable sortable" style="text-align:center; white-space:nowrap;"
|+ Synchronous dynamic random-access memory (SDRAM)
|-
! style="line-height:110%"|Date of<br>intro-<br>duction
! Chip
! Capacity
! SDRAM
!
! data-sort-type="number" |[[Semiconductor device fabrication|
! [[MOSFET|MOS-<br>FET]]
! data-sort-type="number" | Area<br>(mm<sup>2</sup>)
! {{Abbr|Ref|Reference(s)}}
|-
Line 397 ⟶ 396:
|[[SDR SDRAM|SDR]]
|[[Samsung Electronics|Samsung]]
|style="color:#AAAAAA"| ''?''
|[[CMOS]]
|style="color:#AAAAAA"| ''?''
|<ref name="KM48SL2000">{{cite web |title=KM48SL2000-7 Datasheet |url=https://www.datasheetarchive.com/KM48SL2000-7-datasheet.html |publisher=[[Samsung]] |access-date=19 June 2019 |date=August 1992}}</ref><ref name="electronic-design"/>
|-
Line 407 ⟶ 406:
|[[RDRAM]]
|[[Oki Electric Industry|Oki]]
|style="color:#AAAAAA"| ''?''
|CMOS
|325
|<ref name="oki-rdram">{{cite web |title=MSM5718C50/MD5764802 |url=https://retrocdn.net/images/c/c3/Oki_Concurrent_RDRAM_datasheet.pdf |archive-url=https://web.archive.org/web/20190621151518/https://retrocdn.net/images/c/c3/Oki_Concurrent_RDRAM_datasheet.pdf |archive-date=2019-06-21 |url-status=live |publisher=[[Oki Electric Industry|Oki Semiconductor]] |date=February 1999 |access-date=21 June 2019}}</ref>
|-
Line 416 ⟶ 415:
|RDRAM
|[[NEC]]
|style="color:#AAAAAA"| ''?''
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref>{{cite magazine|title=Ultra 64 Tech Specs|magazine=[[Next Generation (magazine)|Next Generation]]|issue=14 |publisher=[[Imagine Media]] |date=February 1996|page=40}}</ref>
|-
|style="color:#AAAAAA"| ''?''
|1024 Mbit
|SDR
Line 427 ⟶ 426:
|[[180 nanometer|150 nm]]
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="stol">{{cite web|url=http://maltiel-consulting.com/Semiconductor_technology_memory.html|title=Memory|website=STOL (Semiconductor Technology Online)|access-date=25 June 2019}}</ref>
|-
|1997
|style="color:#AAAAAA"| ''?''
|1024 Mbit
|SDR
|[[Hyundai Electronics|Hyundai]]
|style="color:#AAAAAA"| ''?''
|[[Silicon on insulator|SOI]]
|style="color:#AAAAAA"| ''?''
|<ref name="hynix90s">{{cite web |title=History: 1990s |url=http://www.az5miao.com/history1990.html |access-date=4 April 2022 |website=az5miao}}</ref>
|-
|1998
Line 445 ⟶ 444:
|RDRAM
|Oki
|style="color:#AAAAAA"| ''?''
|CMOS
|325
|<ref name="oki-rdram"/>
|-
|{{sort|1998|
|Direct RDRAM
|72 Mbit
|RDRAM
|[[Rambus]]
|style="color:#AAAAAA"| ''?''
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref>{{cite web |title=Direct RDRAM |url=https://retrocdn.net/images/6/68/Direct_RDRAM_datasheet.pdf |archive-url=https://web.archive.org/web/20190621151523/https://retrocdn.net/images/6/68/Direct_RDRAM_datasheet.pdf |archive-date=2019-06-21 |url-status=live |publisher=[[Rambus]] |date=12 March 1998 |access-date=21 June 2019}}</ref>
|-
|{{sort|1998|
|style="color:#AAAAAA"| ''?''
|64 Mbit
|[[DDR SDRAM|DDR]]
|Samsung
|style="color:#AAAAAA"| ''?''
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="samsung98">{{cite news |title=Samsung Electronics Comes Out with Super-Fast 16M DDR SGRAMs |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-comes-out-with-super-fast-16m-ddr-sgrams/ |access-date=23 June 2019 |work=[[Samsung Electronics]] |publisher=[[Samsung]] |date=17 September 1998}}</ref><ref name="samsung99">{{cite news |title=Samsung Electronics Develops First 128Mb SDRAM with DDR/SDR Manufacturing Option |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-develops-first-128mb-sdram-with-ddr-sdr-manufacturing-option/ |access-date=23 June 2019 |work=[[Samsung Electronics]] |publisher=[[Samsung]] |date=10 February 1999}}</ref><ref name="phys">{{cite news |title=Samsung Demonstrates World's First DDR 3 Memory Prototype |url=https://phys.org/news/2005-02-samsung-world-ddr-memory-prototype.html |access-date=23 June 2019 |work=[[Phys.org]] |date=17 February 2005 |language=en-us}}</ref>
|-
| rowspan="2" |1998
| rowspan="2" style="color:#AAAAAA"|
|64 Mbit
|DDR
|Hyundai
|style="color:#AAAAAA"| ''?''
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="hynix90s"/>
|-
Line 483 ⟶ 482:
|SDR
|Samsung
|style="color:#AAAAAA"| ''?''
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="samsung-history">{{cite web |title=History |url=https://www.samsung.com/us/aboutsamsung/company/history/ |website=[[Samsung Electronics]] |publisher=[[Samsung]] |access-date=19 June 2019}}</ref><ref name="samsung99"/>
|-
| rowspan="2" |1999
| rowspan="2" style="color:#AAAAAA"|
|128 Mbit
|DDR
|Samsung
|style="color:#AAAAAA"| ''?''
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="samsung99"/>
|-
Line 503 ⟶ 502:
|[[130 nanometer|140 nm]]
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="stol"/>
|-
Line 513 ⟶ 512:
|[[180 nm]]
|CMOS
|279
|<ref name="sony2003">{{cite news |title=EMOTION ENGINE AND GRAPHICS SYNTHESIZER USED IN THE CORE OF PLAYSTATION BECOME ONE CHIP |url=https://www.sie.com/content/dam/corporate/en/corporate/release/pdf/030421be.pdf |archive-url=https://web.archive.org/web/20170227150247/https://www.sie.com/content/dam/corporate/en/corporate/release/pdf/030421be.pdf |archive-date=2017-02-27 |url-status=live |access-date=26 June 2019 |publisher=[[Sony]] |date=April 21, 2003}}</ref>
|-
| rowspan="2" |2001
| rowspan="2" style="color:#AAAAAA"|
|288 Mbit
|RDRAM
|Hynix
|style="color:#AAAAAA"| ''?''
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="hynix2000s">{{cite web |title=History: 2000s |url=http://www.az5miao.com/history2000.html
|-
|style="color:#AAAAAA"| ''?''
|[[DDR2 SDRAM|DDR2]]
|Samsung
|[[100 nm]]
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="phys"/><ref name="stol"/>
|-
|2002
|style="color:#AAAAAA"| ''?''
|256 Mbit
|SDR
|Hynix
|style="color:#AAAAAA"| ''?''
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="hynix2000s"/>
|-
Line 551 ⟶ 550:
|[[90 nm]]
|CMOS
|{{0}}86
|<ref name="sony2003"/>
|-
| rowspan="4" style="color:#AAAAAA"|
|72 Mbit
|[[DDR3]]
Line 560 ⟶ 559:
|90 nm
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref>{{cite news |title=Samsung Develops the Industry's Fastest DDR3 SRAM for High Performance EDP and Network Applications |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-develops-the-industrys-fastest-ddr3-sram-for-high-performance-edp-and-network-applications/ |access-date=25 June 2019 |work=[[Samsung Semiconductor]] |publisher=[[Samsung]] |date=29 January 2003}}</ref>
|-
Line 566 ⟶ 565:
| rowspan="2" |DDR2
|Hynix
|style="color:#AAAAAA"| ''?''
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="hynix2000s"/>
|-
Line 574 ⟶ 573:
|[[110 nanometer|110 nm]]
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref>{{cite news |title=Elpida ships 2GB DDR2 modules |url=https://www.theinquirer.net/inquirer/news/1044210/elpida-ships-2gb-ddr2-modules |archive-url=https://web.archive.org/web/20190710115030/https://www.theinquirer.net/inquirer/news/1044210/elpida-ships-2gb-ddr2-modules |url-status=unfit |archive-date=July 10, 2019 |access-date=25 June 2019 |work=[[The Inquirer]] |date=4 November 2003}}</ref>
|-
Line 580 ⟶ 579:
|DDR2
|Hynix
|style="color:#AAAAAA"| ''?''
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="hynix2000s"/>
|-
|2004
|style="color:#AAAAAA"| ''?''
|2048 Mbit
|DDR2
Line 592 ⟶ 591:
|80 nm
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="samsung2004">{{cite news |title=Samsung Shows Industry's First 2-Gigabit DDR2 SDRAM |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-shows-industrys-first-2-gigabit-ddr2-sdram/ |access-date=25 June 2019 |work=[[Samsung Semiconductor]] |publisher=[[Samsung]] |date=20 September 2004}}</ref>
|-
Line 602 ⟶ 601:
|[[65 nm]]
|CMOS
|{{0}}86
|<ref name="impress">{{cite web|url=https://pc.watch.impress.co.jp/docs/2003/0421/sony1.htm|title=ソニー、65nm対応の半導体設備を導入。3年間で2,000億円の投資|website=pc.watch.impress.co.jp|url-status=live|archive-url=https://web.archive.org/web/20160813020249/http://pc.watch.impress.co.jp/docs/2003/0421/sony1.htm|archive-date=2016-08-13}}</ref>
|-
Line 611 ⟶ 610:
|90 nm
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref>ATI engineers by way of Beyond 3D's Dave Baumann</ref>
|-
|style="color:#AAAAAA"| ''?''
|512 Mbit
|DDR3
Line 620 ⟶ 619:
|80 nm
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="phys"/><ref name="samsung2000s">{{cite web |title=Our Proud Heritage from 2000 to 2009 |url=https://www.samsung.com/semiconductor/about-us/history-03/ |website=[[Samsung Semiconductor]] |publisher=[[Samsung]] |access-date=25 June 2019}}</ref>
|-
|2006
|style="color:#AAAAAA"| ''?''
|1024 Mbit
|DDR2
Line 630 ⟶ 629:
|60 nm
|rowspan="2" | CMOS
|rowspan="2" style="color:#AAAAAA"|
|rowspan="2" | <ref name="hynix2000s"/>
|-
|2008
|style="color:#AAAAAA"| ''?''
|style="color:#AAAAAA"| ''?''
|[[LPDDR2]]
|Hynix
|style="color:#AAAAAA"| ''?''
|-
|{{sort|2008|
|style="color:#AAAAAA"| ''?''
|8192 Mbit
|DDR3
Line 647 ⟶ 646:
|50 nm
|CMOS
|style="color:#AAAAAA"| ''?''
|rowspan="2" | <ref>{{cite news |title=Samsung 50nm 2GB DDR3 chips are industry's smallest |url=https://www.slashgear.com/samsung-50nm-2gb-ddr3-chips-are-industrys-smallest-2917676/ |access-date=25 June 2019 |work=SlashGear |date=29 September 2008}}</ref>
|-
|2008
|style="color:#AAAAAA"| ''?''
|16384 Mbit
|DDR3
Line 657 ⟶ 656:
|50 nm
|CMOS
|style="color:#AAAAAA"| ''?''
|-
| rowspan="2" |2009
| rowspan="2" style="color:#AAAAAA"|
|style="color:#AAAAAA"| ''?''
|DDR3
|Hynix
|[[45 nanometer|44 nm]]
|rowspan="2" | CMOS
|rowspan="2" style="color:#AAAAAA"|
|rowspan="2" | <ref name="hynix2000s"/>
|-
Line 675 ⟶ 674:
|-
| rowspan="2" |2011
| rowspan="2" style="color:#AAAAAA"|
|16384 Mbit
|DDR3
Line 681 ⟶ 680:
|40 nm
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="hynix2010s">{{cite web |title=History: 2010s |url=http://www.az5miao.com/history2010.html |website=az5miao |access-date=4 April 2022}}</ref>
|-
Line 689 ⟶ 688:
|[[32 nanometer|30 nm]]
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="hynix2010s"/>
|-
|2013
|style="color:#AAAAAA"| ''?''
|style="color:#AAAAAA"| ''?''
|[[LPDDR4]]
|Samsung
|[[20 nm]]
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="hynix2010s"/>
|-
|2014
|style="color:#AAAAAA"| ''?''
|8192 Mbit
|LPDDR4
Line 709 ⟶ 708:
|20 nm
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref>{{cite web |title=Our Proud Heritage from 2010 to Now |url=https://www.samsung.com/semiconductor/about-us/history-04/ |website=[[Samsung Semiconductor]] |publisher=[[Samsung]] |access-date=25 June 2019}}</ref>
|-
|2015
|style="color:#AAAAAA"| ''?''
|12 Gbit
|LPDDR4
Line 719 ⟶ 718:
|20 nm
|CMOS
|style="color:#AAAAAA"| ''?''
|<ref name="samsung-history"/>
|-
| rowspan="2" |2018
| rowspan="2" style="color:#AAAAAA"|
|8192 Mbit
|[[LPDDR#LP-DDR5|LPDDR5]]
|Samsung
|[[10 nm process|10 nm]]
|[[FinFET]]
|style="color:#AAAAAA"| ''?''
|<ref>{{cite news |title=Samsung Electronics Announces Industry's First 8Gb LPDDR5 DRAM for 5G and AI-powered Mobile Applications |url=https://news.samsung.com/global/samsung-electronics-announces-industrys-first-8gb-lpddr5-dram-for-5g-and-ai-powered-mobile-applications |access-date=8 July 2019 |publisher=[[Samsung]] |date=July 17, 2018}}</ref>
|-
Line 737 ⟶ 736:
|10 nm
|FinFET
|style="color:#AAAAAA"| ''?''
|<ref>{{cite news |date=6 September 2018 |title=Samsung Unleashes a Roomy DDR4 256GB RAM |work=[[Tom's Hardware]] |url=https://www.tomshardware.co.uk/samsung-256gb-ddr4-ram,news-59123.html |url-status=dead |access-date=4 April 2022 |archive-url=https://web.archive.org/web/20190621205106if_/https://www.tomshardware.co.uk/samsung-256gb-ddr4-ram,news-59123.html |archive-date=June 21, 2019}}</ref>
|}
=== SGRAM
{| class="wikitable sortable" style="text-align:center"
|+ [[Synchronous graphics random-access memory]] (SGRAM
|-
! Date of introduction
Line 802 ⟶ 801:
|{{?}}
|CMOS
|280 mm<sup>2</sup>
|<ref>{{cite news |title=Samsung Announces the World's First 222 MHz 32Mbit SGRAM for 3D Graphics and Networking Applications |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-announces-the-worlds-first-222-mhz-32mbit-sgram-for-3d-graphics-and-networking-application/ |access-date=10 July 2019 |work=[[Samsung Semiconductor]] |publisher=[[Samsung]] |date=12 July 1999}}</ref>
|-
Line 885 ⟶ 884:
|4096 Mbit
|SGRAM (GDDR3)
|-
|{{sort|2016|March 2016}}
Line 904 ⟶ 898:
|CMOS
|140 mm<sup>2</sup>
|<ref>{{cite news |last1=Shilov |first1=Anton |title=Micron Begins to Sample GDDR5X Memory, Unveils Specs of Chips |url=https://www.anandtech.com/show/10193/micron-begins-to-sample-gddr5x-memory |archive-url=https://web.archive.org/web/20160330094652/http://www.anandtech.com/show/10193/micron-begins-to-sample-gddr5x-memory |url-status=dead |archive-date=March 30, 2016 |access-date=16 July 2019 |work=[[AnandTech]] |date=March 29, 2016}}</ref>
|-
|{{sort|2018|January 2018}}
|K4ZAF325BM
|16 Gbit
|SGRAM ([[GDDR6]])
|Samsung
|[[10 nm process|10 nm]]
|[[FinFET]]
|225 mm<sup>2</sup>
|<ref>{{cite news |title=Samsung Electronics Starts Producing Industry's First 16-Gigabit GDDR6 for Advanced Graphics Systems |url=https://news.samsung.com/global/samsung-electronics-starts-producing-industrys-first-16-gigabit-gddr6-for-advanced-graphics-systems |access-date=15 July 2019 |publisher=[[Samsung]] |date=January 18, 2018}}</ref><ref name='tr_gddr6'>{{cite news|last1=Killian|first1=Zak|title=Samsung fires up its foundries for mass production of GDDR6 memory|url=https://techreport.com/news/33129/samsung-fires-up-its-foundries-for-mass-production-of-gddr6-memory|access-date=18 January 2018|publisher=Tech Report|date=18 January 2018}}</ref><ref>{{cite news |title=Samsung Begins Producing The Fastest GDDR6 Memory In The World |url=https://wccftech.com/samsung-gddr6-16gb-18gbps-mass-production-official/ |access-date=16 July 2019 |work=Wccftech |date=18 January 2018}}</ref>
|} <section end="SDRAM timeline"/>
=== HBM ===
{| class="wikitable sortable" style="text-align:center"
|+ [[High Bandwidth Memory]] (HBM)
|-
! Date of introduction
! Chip name
! Capacity ([[bit]]s){{binpre}}
! SDRAM type
! Manufacturer(s)
! data-sort-type="number" |[[Semiconductor device fabrication|Process]]
! [[MOSFET]]
! data-sort-type="number" | Area
! {{Abbr|Ref|Reference(s)}}
|-
|2013
|{{?}}
|{{?}}
|[[High Bandwidth Memory|HBM]]
|[[SK Hynix]]
|{{?}}
|CMOS
|{{?}}
|<ref name="hynix2010s" />
|-
|{{sort|2016|June 2016}}
Line 911 ⟶ 940:
|[[HBM2]]
|Samsung
|[[20
|CMOS
|{{?}}
|<ref name="Shilov2017">{{cite news |last1=Shilov |first1=Anton |date=July 19, 2017 |title=Samsung Increases Production Volumes of 8 GB HBM2 Chips Due to Growing Demand |url=https://www.anandtech.com/show/11643/samsung-increases-8gb-hbm2-production-volume |archive-url=https://web.archive.org/web/20170720000946/http://anandtech.com/show/11643/samsung-increases-8gb-hbm2-production-volume |url-status=dead |archive-date=July 20, 2017 |access-date=29 June 2019 |work=[[AnandTech]]
|-
|2017
Line 924 ⟶ 953:
|CMOS
|{{?}}
|<ref name="Shilov2017" />
|
== See also ==
* [[GDDR]] (graphics DDR) and its subtypes [[GDDR2]], [[GDDR3]], [[GDDR4]], [[GDDR5]], [[GDDR6]] and [[
* [[List of device bandwidths]]
* [[Serial presence detect]]
* [http://taututorial.yolasite.com/ SDRAM Tutorial]
* A concise but thorough review of SDRAM architecture/terminology and command timing dependencies in [http://drum.lib.umd.edu/bitstream/1903/11269/1/Gross_umd_0117N_11844.pdf High-Performance DRAM System Design Constraints and Considerations], a master thesis from the University of Maryland.
Line 948 ⟶ 966:
== External links ==
* [https://web.archive.org/web/20121016082506/http://www.anandtech.com/show/3851
* [http://www.hardwaresecrets.com/understanding-ram-timings/ Understanding RAM Timings], May 2011, Hardware Secrets
* [https://web.archive.org/web/20030803094457/http://developer.intel.com/technology/memory/pc133sdram/spec/sdram133.pdf PC SDRAM Specification, Rev 1.7]
* [https://web.archive.org/web/20030429115837/http://developer.intel.com/technology/memory/pc133sdram/spec/PC133sodm1_0c1.pdf
* [https://web.archive.org/web/20030803113813/http://developer.intel.com/technology/memory/pc133sdram/spec/Spdsd12b.pdf PC SDRAM Serial Presence Detect (SPD) Specification, Rev 1.2B]
| |||