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{{Memory types}}
[[File:SDRAM_memory_module.jpg|thumb|SDRAM memory module]]
'''Synchronous dynamic random-access memory''' ('''synchronous dynamic RAM''' or '''SDRAM''') is any [[Dynamic RAMrandom-access memory|DRAM]] where the operation of its external pin interface is coordinated by an externally supplied [[clock signal]].
 
DRAM [[integrated circuit]]s (ICs) produced from the early 1970s to the early 1990s used an ''asynchronous'' interface, in which input control signals have a direct effect on internal functions only delayed only by the trip across its semiconductor pathways. SDRAM has a ''synchronous'' interface, whereby changes on control inputs are recognised after a rising edge of its clock input. In SDRAM families standardized by [[JEDEC]], the clock signal controls the stepping of an internal [[finite-state machine]] that responds to incoming commands. These commands can be pipelined to improve performance, with previously started operations completing while new commands are received. The memory is divided into several equally sized but independent sections called ''[[Memory bank|bank]]s'', allowing the device to operate on a memory access command in each bank simultaneously and speed up access in an [[Interleaved memory|interleaved]] fashion. This allows SDRAMs to achieve greater concurrency and higher data transfer rates than asynchronous DRAMs could.
 
[[Pipeline (computing)|Pipelining]] means that the chip can accept a new command before it has finished processing the previous one. For a pipelined write, the write command can be immediately followed by another command without waiting for the data to be written into the memory array. For a pipelined read, the requested data appears a fixed number of clock cycles (latency) after the read command, during which additional commands can be sent.
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[[Image:SDR SDRAM-1.jpg|thumb|Eight [[Hyundai Electronics|Hyundai]] SDRAM ICs on a PC100 [[DIMM]] package]]
 
The earliest DRAMs were often synchronized with the CPU clock (clocked) and were used with early microprocessors. In the mid-1970s, DRAMs moved to the asynchronous design, but in the 1990s returned to synchronous operation.<ref>{{cite book | author=P. Darche | title=Microprocessor: Prolegomenes -– Calculation and Storage Functions -– Calculation Models and Computer | year=2020 | page=59 | publisher=John Wiley & Sons | isbn=9781786305633 | url=https://books.google.com/books?id=rLC9zQEACAAJ}}</ref><ref>{{cite book |author1=B. Jacob |author2=S. W. Ng |author3=D. T. Wang | title=Memory Systems: Cache, DRAM, Disk | year=2008 | publisher=Morgan Kaufmann | page=324 | isbn=9780080553849 | url=https://books.google.com/books?id=SrP3aWed-esC}}</ref> In the late 1980s [[IBM]] had built DRAMs using a [[double data rate|dual-edge clocking]] feature and presented their results at the International Solid-State Circuits Convention in 1990. However, it was standard [[DRAM]], not SDRAM.<ref>{{cite book |first1=B. |last1=Jacob |first2=S. W. |last2=Ng |first3=D. T. |last3=Wang | title=Memory Systems: Cache, DRAM, Disk | year=2008 | publisher=Morgan Kaufmann | page=333 | isbn=9780080553849 | url=https://books.google.com/books?id=SrP3aWed-esC}}</ref><ref>{{cite journal |first1=H. L. |last1=Kalter |first2=C. H. |last2=Stapper |first3=J. E. |last3=Barth |first4=J. |last4=Dilorenzo |first5=C. E. |last5=Drake |first6=J. A. |last6=Fifield |first7=G. A. |last7=Kelley |first8=S. C. |last8=Lewis |first9=W. B. |last9=van der Hoeven |first10=J. A. |last10=Jankosky | title=A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC | year=1990 | journal=IEEE Journal of Solid-State Circuits | volume=25 | issue=5| page=1118 | doi=10.1109/4.62132 | bibcode=1990IJSSC..25.1118K }}</ref>
 
The first commercial SDRAM was the [[Samsung]] KM48SL2000 [[memory chip]], which had a capacity of 16{{nbsp}}Mbit.<ref name="electronic-design">{{cite journal|date=1993|title=Electronic Design|url=https://books.google.com/books?id=QmpJAQAAIAAJ|journal=[[Electronic Design]]|publisher=Hayden Publishing Company|volume=41|issue=15–21|quote=The first commercial synchronous DRAM, the Samsung 16-Mbit KM48SL2000, employs a single-bank architecture that lets system designers easily transition from asynchronous to synchronous systems.}}</ref> It was manufactured by [[Samsung Electronics]] using a [[CMOS]] (complementary [[metal–oxide–semiconductor]]) [[fabrication process]] in 1992,<ref name="KM48SL2000"/> and mass-produced in 1993.<ref name="electronic-design"/> By 2000, SDRAM had replaced virtually all other types of [[DRAM]] in modern [[computer]]scomputers, because of its greater performance.
 
SDRAM latency is not inherently lower (faster access times) than asynchronous DRAM. Indeed, early SDRAM was somewhat slower than contemporaneous [[burst EDO DRAM]] due to the additional logic. The benefits of SDRAM's internal buffering come from its ability to interleave operations to multiple banks of memory, thereby increasing effective [[Bandwidth (computing)|bandwidth]].
 
[[Double data rate]] SDRAM, known as [[DDR SDRAM]], was first demonstrated by Samsung in 1997.<ref name="techpowerup">{{cite web |title=Samsung 30 nm Green PC3-12800 Low Profile 1.35 V DDR3 Review |url=https://www.techpowerup.com/review/samsung-mv-3v4g3/ |website=TechPowerUp |access-date=25 June 2019 |date= March 8, 2012}}</ref> Samsung released the first commercial DDR SDRAM chip (64{{nbsp}}Mbit{{binpre}}) in June 1998,<ref name="samsung99"/><ref name="samsung98"/><ref name="phys"/> followed soon after by [[Hyundai Electronics]] (now [[SK Hynix]]) the same year.<ref name="hynix90s"/>
Today, virtually all SDRAM is manufactured in compliance with standards established by [[JEDEC]], an electronics industry association that adopts [[open standards]] to facilitate interoperability of electronic components. JEDEC formally adopted its first SDRAM standard in 1993 and subsequently adopted other SDRAM standards, including those for [[DDR SDRAM|DDR]], [[DDR2 SDRAM|DDR2]] and [[DDR3 SDRAM]].
 
Today, virtually all SDRAM is manufactured in compliance with standards established by [[JEDEC]], an electronics industry association that adopts [[open standards]] to facilitate interoperability of electronic components. JEDEC formally adopted its first SDRAM standard in 1993 and subsequently adopted other SDRAM standards, including those for [[DDR SDRAM|DDR]], [[DDR2 SDRAM|DDR2]] and [[DDR3 SDRAM]].
[[Double data rate]] SDRAM, known as [[DDR SDRAM]], was first demonstrated by Samsung in 1997.<ref name="techpowerup">{{cite web |title=Samsung 30 nm Green PC3-12800 Low Profile 1.35 V DDR3 Review |url=https://www.techpowerup.com/review/samsung-mv-3v4g3/ |website=TechPowerUp |access-date=25 June 2019 |date= March 8, 2012}}</ref> Samsung released the first commercial DDR SDRAM chip (64{{nbsp}}Mbit{{binpre}}) in June 1998,<ref name="samsung99"/><ref name="samsung98"/><ref name="phys"/> followed soon after by [[Hyundai Electronics]] (now [[SK Hynix]]) the same year.<ref name="hynix90s">{{cite web |title=History: 1990s |url=http://www.az5miao.com/history1990.html |website=az5miao |access-date=4 April 2022}}</ref>
 
SDRAM is also available in [[Registered memory|registered]] varieties, for systems that require greater scalability such as [[Server (computing)|server]]s and [[workstations]].
 
Today, the world's largest manufacturers of SDRAM include: [[Samsung Electronics]], [[SK Hynix]], [[Micron Technology]], and [[Nanya Technology]].
 
== Timing ==
There are several limits on DRAM performance. Most noted is the read cycle time, the time between successive read operations to an open row. This time decreased from 1015&nbsp;ns for 10066&nbsp;MHz SDRAM (1&nbsp;MHz = 10<mathsup>10^{6}</mathsup>&nbsp;Hz) to 5&nbsp;ns for DDR-400, but has remained relatively unchanged through DDR2-800 and DDR3-1600 generations. However, by operating the interface circuitry at increasingly higher multiples of the fundamental read rate, the achievable bandwidth has increased rapidly.
 
Another limit is the [[CAS latency]], the time between supplying a column address and receiving the corresponding data. Again, this has remained relatively constant at 10–15 ns through the last few generations of DDR SDRAM.
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In operation, CAS latency is a specific number of clock cycles programmed into the SDRAM's mode register and expected by the DRAM controller. Any value may be programmed, but the SDRAM will not operate correctly if it is too low. At higher clock rates, the useful CAS latency in clock cycles naturally increases. 10–15&nbsp;ns is 2–3 cycles (CL2–3) of the 200&nbsp;MHz clock of DDR-400 SDRAM, CL4-6 for DDR2-800, and CL8-12 for DDR3-1600. Slower clock cycles will naturally allow lower numbers of CAS latency cycles.
 
SDRAM modules have their own timing specifications, which may be slower than those of the chips on the module. When 100&nbsp;MHz SDRAM chips first appeared, some manufacturers sold "100&nbsp;MHz" modules that could not reliably operate at that clock rate. In response, Intel published the PC100 standard, which outlines requirements and guidelines for producing a memory module that can operate reliably at 100&nbsp;MHz. This standard was widely influential, and the term "PC100" quickly became a common identifier for 100&nbsp;MHz SDRAM modules, and modules are now commonly designated with "PC"-prefixed numbers (PC66, PC100 or PC133 -– although the actual meaning of the numbers has changed).
 
== Control signals ==
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* Additional extended mode registers (selected by the bank address bits)
* DDR2 deletes the burst terminate command; DDR3 reassigns it as "ZQ calibration"
* DDR3 and DDR4 use A12 during read and write command to indicate "burst chop", half-length data transfer
* [[DDR4#Command encoding|DDR4 changes the encoding]] of the activate command. A new signal {{overline|ACT}} controls it, during which the other control lines are used as row address bits 16, 15 and 14. When {{overline|ACT}} is high, other commands are the same as above.
 
== Construction and operation==
[[File:SDRAM_memory_module,_zoomed.jpg|thumb|SDRAM [[memory module]], zoomed]]
As an example, a '512&nbsp;MB' SDRAM DIMM (which contains 512&nbsp;MB), might be made of eight or nine SDRAM chips, each containing 512&nbsp;Mbit of storage, and each one contributing 8 bits to the DIMM's 64- or 72-bit width. A typical 512&nbsp;Mbit SDRAM ''chip'' internally contains four independent 16&nbsp;MB memory banks. Each bank is an array of 8,192 rows of 16,384 bits each. (2048 8-bit columns). A bank is either idle, active, or changing from one to the other.{{binpre}}
 
The ''active'' command activates an idle bank. It presents a two-bit bank address (BA0&ndash;BA1) and a 13-bit row address (A0&ndash;A12), and causes a read of that row into the bank's array of all 16,384 column sense amplifiers. This is also known as "opening" the row. This operation has the side effect of [[Memory refresh|refresh]]ing the dynamic (capacitive) memory storage cells of that row.
 
Once the row has been activated or "opened", ''read'' and ''write'' commands are possible to that row. Activation requires a minimum amount of time, called the row-to-column delay, or t<sub>RCD</sub> before reads or writes to it may occur. This time, rounded up to the next multiple of the clock period, specifies the minimum number of wait cycles between an ''active'' command, and a ''read'' or ''write'' command. During these wait cycles, additional commands may be sent to other banks; because each bank operates completely independently.
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* M8, M7: Operating mode. Reserved, and must be 00.
* M6, M5, M4: CAS latency. Generally only 010 (CL2) and 011 (CL3) are legal. Specifies the number of cycles between a read command and data output from the chip. The chip has a fundamental limit on this value in nanoseconds; during initialization, the memory controller must use its knowledge of the clock frequency to translate that limit into cycles.
* M3: Burst type. 0 -– requests sequential burst ordering, while 1 requests interleaved burst ordering.
* M2, M1, M0: Burst length. Values of 000, 001, 010 and 011 specify a burst size of 1, 2, 4 or 8 words, respectively. Each read (and write, if M9 is 0) will perform that many accesses, unless interrupted by a burst stop or other command. A value of 111 specifies a full-row burst. The burst will continue until interrupted. Full-row bursts are only permitted with the sequential burst type.
 
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! scope="row" | SDRAM
| {{Unbulleted list
| {{Nowrap|V{{Sub|cc}} {{=}} 3.3 &nbsp;V}}
| Signal: [[Transistor–transistor logic#Sub-types|LVTTL]]
}}
|-
! scope="row" | [[DDR SDRAM|DDR1]]
| {{Unbulleted list
| Access is ≥2≥&nbsp;2 words
| [[Double data rate|Double clocked]]
| {{Nowrap|V{{Sub|cc}} {{=}} 2.5 &nbsp;V}}
| {{Nowrap|2.5 - &nbsp;−&nbsp;7.5 &nbsp;ns}} per cycle
| Signal: [[Stub Series Terminated Logic|SSTL_2]] (2.5V5&nbsp;V)<ref name="edn-dramconsumer">{{cite web|title=The outlook for DRAMs in consumer electronics|url=https://www.edn.com/the-outlook-for-drams-in-consumer-electronics/|last=Graham |first=Allan |publisher=AspenCore Media |website=EDN|date=2007-01-12 |access-date=2021-04-13}}</ref>
}}
|-
! scope="row" | [[DDR2 SDRAM|DDR2]]
| Access is ≥4≥&nbsp;4 words<br/> "Burst terminate" removed<br/> 4 units used in parallel<br/> {{Nowrap|1.25 - 5 ns&nbsp;−&nbsp;5ns}} per cycle<br/> Internal operations are <br>&nbsp;at 1/2 the clock rate.<br/> Signal: [[Stub Series Terminated Logic|SSTL_18]] (1.8V8&nbsp;V)<ref name="edn-dramconsumer"/>
|-
! scope="row" | [[DDR3 SDRAM|DDR3]]
| Access is ≥8≥&nbsp;8 words<br/> Signal: [[Stub Series Terminated Logic|SSTL_15]] (1.5V5&nbsp;V)<ref name="edn-dramconsumer"/><br/> Much longer CAS latencies
|-
! scope="row" | [[DDR4 SDRAM|DDR4]]
| {{Nowrap|V{{Sub|cc}} ≤ &nbsp;1.2 &nbsp;V}} point-to-point <br>(single module per channel)
|}
 
=== SDR ===
[[Image:Micron 48LC32M8A2-AB.jpg|thumb|upright=1.25|The 64&nbsp;MB{{binpre}} of sound memory on the [[Sound Blaster X-Fi|Sound Blaster X-Fi Fatality Pro]] [[sound card]] is built from two2 [[Micron Technology|Micron]] 48LC32M8A2 SDRAM chips. TeThey corresrun at 133&nbsp;MHz (7.5&nbsp;ns clock period) and have 8-bit wide data buses.<!-- x8 3.3V TSOP-54 CL=3 PC133 --><ref>{{cite web|title=SDRAM Part Catalog|url=http://www.micron.com/products/dram/sdram/partlist}} 070928 micron.com</ref>]]
 
Originally simply known as ''SDRAM'', single data rate SDRAM can accept one command and transfer one word of data per clock cycle. Chips are made with a variety of data bus sizes (most commonly 4, 8 or 16 bits), but chips are generally assembled into 168-pin [[DIMM]]s that read or write 64 (non-ECC) or 72 ([[ECC memory|ECC]]) bits at a time.
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==== PC66 ====
'''PC66''' refers to internal removable computer [[random-access memory|memory]] standard defined by the [[Joint Electron Device Engineering Council|JEDEC]]. PC66 is Synchronous DRAM operating at a clock frequency of 66.66&nbsp;MHz, on a 64-bit bus, at a voltage of 3.3&nbsp;V. PC66 is available in 168-pin [[DIMM]] and 144-pin [[SO-DIMM]] form factors. The theoretical bandwidth is 533&nbsp;MB/s. (1 &nbsp;MB/s = one million bytes per second)
 
This standard was used by [[Original Intel Pentium (P5 microarchitecture)|Intel Pentium]] and [[AMD K6]]-based PCs. It also features in the Beige [[Power Mac G3]], early [[iBook]]s and [[PowerBook G3]]s. It is also used in many early [[Intel Celeron]] systems with a 66&nbsp;MHz [[front-side bus|FSB]]. It was superseded by the PC100 and PC133 standards.
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==== PC100 ====
{{For|the Japanese home computer|NEC PC-100}}
[[Image:SDRAM 128MB 133MHz.jpg|thumb|250pxupright=1.25|DIMM: 168 pins and two notches]]
'''PC100''' is a standard for internal removable computer [[random-access memory]], defined by the [[Joint Electron Device Engineering Council|JEDEC]]. PC100 refers to Synchronous DRAM operating at a clock frequency of 100&nbsp;MHz, on a 64-bit-wide bus, at a voltage of 3.3&nbsp;V. PC100 is available in 168-pin [[DIMM]] and 144-pin [[SO-DIMM]] [[Computer form factor|form factor]]s. PC100 is [[backward compatible]] with PC66 and was superseded by the PC133 standard.
 
A module built out of 100&nbsp;MHz SDRAM chips is not necessarily capable of operating at 100&nbsp;MHz. The PC100 standard specifies the capabilities of the [[memory module]] as a whole. PC100 is used in many older computers; PCs around the late 1990s were the most common computers with PC100 memory.
 
==== PC133 ====
'''PC133''' is a computer memory standard defined by the [[Joint Electron Device Engineering Council|JEDEC]]. PC133 refers to [[SDR SDRAM]] operating at a clock frequency of 133&nbsp;MHz, on a 64-bit-wide bus, at a voltage of 3.3&nbsp;V. PC133 is available in 168-pin [[DIMM]] and 144-pin [[SO-DIMM]] form factors. PC133 is the fastest and final SDR SDRAM standard ever approved by the JEDEC, and delivers a bandwidth of 1.066&nbsp;GB per second ([133.33&nbsp;MHz * 64/8]=1.066&nbsp;GB/s). (1 &nbsp;GB/s = one billion bytes per second) PC133 is [[backward compatible]] with PC100 and PC66.
 
=== {{Anchor|DDR1}} DDR ===
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DDR2 SDRAM is very similar to DDR SDRAM, but doubles the minimum read or write unit again, to four consecutive words. The bus protocol was also simplified to allow higher performance operation. (In particular, the "burst terminate" command is deleted.) This allows the bus rate of the SDRAM to be doubled without increasing the clock rate of internal RAM operations; instead, internal operations are performed in units four times as wide as SDRAM. Also, an extra bank address pin (BA2) was added to allow eight banks on large RAM chips.
 
Typical DDR2 SDRAM clock rates are 200, 266, 333 or 400&nbsp;MHz (periods of 5, 3.75, 3 and 2.5&nbsp;ns), generally described as DDR2-400, DDR2-533, DDR2-667 and DDR2-800 (periods of 2.5, 1.875, 1.5 and 1.25&nbsp;ns). Corresponding 240-pin DIMMs are known as PC2-3200 through PC2-6400. DDR2 SDRAM is now available at a clock rate of 533&nbsp;MHz generally described as DDR2-1066 and the corresponding DIMMs are known as PC2-8500 (also named PC2-8600 depending on the manufacturer). Performance up to DDR2-1250 (PC2-10000) is available.
 
Note that because internal operations are at 1/2 the clock rate, DDR2-400 memory (internal clock rate 100&nbsp;MHz) has somewhat higher latency than DDR-400 (internal clock rate 200&nbsp;MHz).
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Again, with every doubling, the downside is the increased [[Latency (engineering)|latency]]. As with all DDR SDRAM generations, commands are still restricted to one clock edge and command latencies are given in terms of clock cycles, which are half the speed of the usually quoted transfer rate (a [[CAS latency]] of 8 with DDR3-800 is 8/(400&nbsp;MHz) = 20 ns, exactly the same latency of CAS2 on PC100 SDR SDRAM).
 
DDR3 memory chips are being made commercially,<ref>{{cite web|url=http://www.simmtester.com/page/news/showpubnews.asp?num=145|title=What is DDR memory?}}</ref> and computer systems using them were available from the second half of 2007,<ref>{{cite news|url=http://www.tomshardware.com/2007/06/05/pipe_dreams_six_p35-ddr3_motherboards_compared/|title=Pipe Dreams: Six P35-DDR3 Motherboards Compared |date=June 5, 2007 |author=Thomas Soderstrom |newspaper=Tom's Hardware}}</ref> with significant usage from 2008 onwards.<ref>{{cite web|url=http://news.softpedia.com/news/AMD-to-Adopt-DDR3-in-Three-Years-13486.shtml|title=AMD to Adopt DDR3 in Three Years|date=28 November 2005}}</ref> Initial clock rates were 400 and 533&nbsp;MHz, which are described as DDR3-800 and DDR3-1066 (PC3-6400 and PC3-8500 modules), but 667 and 800&nbsp;MHz, described as DDR3-1333 and DDR3-1600 (PC3-10600 and PC3-12800 modules) are now common.<ref>{{cite web|url=http://www.anandtech.com/printarticle.aspx?i=3045|archive-url=https://archive.today/20120719141605/http://www.anandtech.com/printarticle.aspx?i=3045|url-status=dead|archive-date=July 19, 2012|title=Super Talent & TEAM: DDR3-1600 Is Here! |date=July 20, 2007 |author=Wesly Fink |publisher=Anandtech}}</ref> Performance up to DDR3-2800 (PC3 22400 modules) are available.<ref>{{cite web |url=http://hothardware.com/News/GSKILL-Announces-DDR3-Memory-Kit-For-Ivy-Bridge/ |title=G.SKILL Announces DDR3 Memory Kit For Ivy Bridge |date=24 April 2012 |author=Jennifer Johnson}}</ref>
 
=== DDR4 ===
{{Main|DDR4 SDRAM}}
 
DDR4 SDRAM is the successor to [[DDR3 SDRAM]]. It was revealed at the [[Intel Developer Forum]] in San Francisco in 2008, and was due to be released to market during 2011. The timing varied considerably during its development -– it was originally expected to be released in 2012,<ref>[http://intel.wingateweb.com/US08/published/sessions/MASS006/SF08_MASS006_100s.pdf DDR4 PDF page 23]</ref> and later (during 2010) expected to be released in 2015,<ref>{{cite web|url=http://www.semiaccurate.com/2010/08/16/ddr4-not-expected-until-2015/|title=DDR4 not expected until 2015|work=semiaccurate.com|date=16 August 2010}}</ref> before samples were announced in early 2011 and manufacturers began to announce that commercial production and release to market was anticipated in 2012. DDR4 reached mass market adoption around 2015, which is comparable with the approximately five years taken for DDR3 to achieve mass market transition over DDR2.
 
The DDR4 chips run at 1.2&nbsp;[[Volt|V]] or less,<ref>{{cite web|url=http://www.pcpro.co.uk/news/220257/idf-ddr3-wont-catch-up-with-ddr2-during-2009.html|title=IDF: "DDR3 won't catch up with DDR2 during 2009"|work=Alphr}}</ref><ref>{{cite web|url=http://www.heise-online.co.uk/news/IDF-DDR4-the-successor-to-DDR3-memory--/111367|title=heise online -– IT-News, Nachrichten und Hintergründe|work=heise online}}</ref> compared to the 1.5&nbsp;V of DDR3 chips, and have in excess of 2 billion [[data transfer]]s per second. They were expected to be introduced at frequency rates of 2133&nbsp;MHz, estimated to rise to a potential 4266&nbsp;MHz<ref>{{cite web |url=http://www.xbitlabs.com/news/memory/display/20100816124343_Next_Generation_DDR4_Memory_to_Reach_4_266GHz_Report.html |title=Next-Generation DDR4 Memory to Reach 4.266GHz -– Report |date=August 16, 2010 |publisher=Xbitlabs.com |access-date=2011-01-03 |url-status=dead |archive-url=https://web.archive.org/web/20101219085440/http://www.xbitlabs.com/news/memory/display/20100816124343_Next_Generation_DDR4_Memory_to_Reach_4_266GHz_Report.html |archive-date=December 19, 2010 }}</ref> and lowered voltage of 1.05&nbsp;V<ref>{{cite news|url=http://www.hardware-infos.com/news.php?news=2332|title=IDF: DDR4 memory targeted for 2012|publisher=hardware-infos.com|language=de|access-date=2009-06-16|archive-url=https://web.archive.org/web/20090713025046/http://www.hardware-infos.com/news.php?news=2332|archive-date=2009-07-13|url-status=dead}}</ref> by 2013.
 
DDR4 did ''not'' double the internal prefetch width again, but uses the same 8''n'' prefetch as DDR3.<ref name="jedec_ddr3_ddr4">{{cite press release |url=http://www.jedec.org/news/pressreleases/jedec-announces-key-attributes-upcoming-ddr4-standard |title=JEDEC Announces Key Attributes of Upcoming DDR4 Standard |publisher=[[JEDEC]] |date=2011-08-22 |access-date=2011-01-06}}</ref> Thus, it will be necessary to interleave reads from several banks to keep the data bus busy.
 
In February 2009, [[Samsung]] validated 40&nbsp;nm DRAM chips, considered a "significant step" towards DDR4 development<ref>{{cite news |url=http://www.tgdaily.com/content/view/41316/139/ |title=Samsung hints to DDR4 with first validated 40&nbsp;nm DRAM |last=Gruener |first=Wolfgang |date=February 4, 2009 |publisher=tgdaily.com |access-date=2009-06-16 |url-status=dead |archive-url=https://web.archive.org/web/20090524133306/http://www.tgdaily.com/content/view/41316/139/ |archive-date=May 24, 2009 }}</ref> since, as of 2009, current DRAM chips were only beginning to migrate to a 50&nbsp;nm process.<ref>{{cite web |url=http://www.dailytech.com/DDR3+Will+be+Cheaper+Faster+in+2009/article13977.htm |title=DDR3 Will be Cheaper, Faster in 2009 |last=Jansen |first=Ng |date=January 20, 2009 |publisher=dailytech.com |access-date=2009-06-17 |url-status=dead |archive-url=https://web.archive.org/web/20090622084614/http://www.dailytech.com/DDR3+Will+be+Cheaper+Faster+in+2009/article13977.htm |archive-date=June 22, 2009 }}</ref> In January 2011, [[Samsung]] announced the completion and release for testing of a 30&nbsp;nm 2048&nbsp;MB{{binpre}} DDR4 DRAM module. It has a maximum bandwidth of 2.13&nbsp;[[Gbit/s]] at 1.2&nbsp;V, uses [[pseudo open drain]] technology and draws 40% less power than an equivalent DDR3 module.<ref>{{cite web |title=Samsung Develops Industry's First DDR4 DRAM, Using 30nm Class Technology |url=http://www.samsung.com/us/business/semiconductor/newsView.do?news_id=1202 |publisher=Samsung |access-date=2011-03-13 |date=2011-01-04}}</ref><ref>{{cite web |url=http://www.techspot.com/news/41818-samsung-develops-ddr4-memory-up-to-40-more-efficient.html |title=Samsung develops DDR4 memory, up to 40% more efficient |work=TechSpot|date=4 January 2011 }}</ref>
 
=== DDR5 ===
{{Main|DDR5 SDRAM}}
 
In March 2017, JEDEC announced a DDR5 standard is under development,<ref>{{cite press release |title=JEDEC DDR5 & NVDIMM-P Standards Under Development |url=https://www.jedec.org/news/pressreleases/jedec-ddr5-nvdimm-p-standards-under-development |date=30 March 2017 |publisher=[[JEDEC]]}}</ref> but provided no details except for the goals of doubling the bandwidth of DDR4, reducing power consumption, and publishing the standard in 2018. The standard was released on 14 July 2020.<ref name="anandtech-ddr5">{{cite web|url=https://www.anandtech.com/show/15912/ddr5-specification-released-setting-the-stage-for-ddr56400-and-beyond|archive-url=https://web.archive.org/web/20200714225042/https://www.anandtech.com/show/15912/ddr5-specification-released-setting-the-stage-for-ddr56400-and-beyond|url-status=dead|archive-date=July 14, 2020|title=DDR5 Memory Specification Released: Setting the Stage for DDR5-6400 And Beyond|last=Smith|first=Ryan|date=2020-07-14|website=AnandTech|access-date=2020-07-15}}</ref>
 
== Failed successors ==
Line 296:
 
=== Synchronous-link DRAM (SLDRAM) ===
SLDRAM boasted higher performance and competed against RDRAM. It was developed during the late 1990s by the SLDRAM Consortium. The SLDRAM Consortium consisted of about 20 major DRAM and computer industry manufacturers. (The SLDRAM Consortium became incorporated as SLDRAM Inc. and then changed its name to Advanced Memory International, Inc.) SLDRAM was an [[open standard]] and did not require licensing fees. The specifications called for a 64-bit bus running at a 200, 300 or 400&nbsp;MHz clock frequency. This is achieved by all signals being on the same line and thereby avoiding the synchronization time of multiple lines. Like [[DDR SDRAM]], SLDRAM uses a double-pumped bus, giving it an effective speed of 400,<ref>{{Citation |url=http://www.tomshardware.com/reviews/ram-guide,89-15.html |title=RAM Guide: SLDRAM |author=Dean Kent |publisher=Tom's Hardware |date=1998-10-24 |access-date=2011-01-01}}</ref> 600,<ref>{{Citation |url=http://icwic.cn/icwic/data/pdf/cd/cd011/12452.pdf |title=HYSL8M18D600A 600 Mb/s/pin 8M x 18 SLDRAM |type=data sheet |author=Hyundai Electronics |date=1997-12-20 |access-date=2011-12-27 |archive-url=https://web.archive.org/web/20120426081302/http://icwic.cn/icwic/data/pdf/cd/cd011/12452.pdf |archive-date=2012-04-26 |url-status=dead }}</ref> or 800&nbsp;[[MT/s]]. (1 &nbsp;MT/s &nbsp;= &nbsp;1000^<sup>2</sup> transfers per second)
 
SLDRAM used an 11-bit command bus (10 command bits CA9:0 plus one start-of-command FLAG line) to transmit 40-bit command packets on 4 consecutive edges of a differential command clock (CCLK/CCLK#). Unlike SDRAM, there were no per-chip select signals; each chip was assigned an ID when reset, and the command contained the ID of the chip that should process it. Data was transferred in 4- or 8-word bursts across an 18-bit (per chip) data bus, using one of two differential data clocks (DCLK0/DCLK0# and DCLK1/DCLK1#). Unlike standard SDRAM, the clock was generated by the data source (the SLDRAM chip in the case of a read operation) and transmitted in the same direction as the data, greatly reducing data skew. To avoid the need for a pause when the source of the DCLK changes, each command specified which DCLK pair it would use.<ref>{{Citation |url=http://icwic.cn/icwic/data/pdf/cd/cd011/12407.pdf |pages=32–33 |title=SLD4M18DR400 400 Mb/s/pin 4M x 18 SLDRAM |type=data sheet |author=SLDRAM Inc. |date=1998-07-09 |access-date=2011-12-27 |archive-url=https://web.archive.org/web/20120426081159/http://icwic.cn/icwic/data/pdf/cd/cd011/12407.pdf |archive-date=2012-04-26 |url-status=dead }}</ref>
Line 302:
The basic read/write command consisted of (beginning with CA9 of the first word):
{|class="wikitable" style="text-align:center"
|+ SLDRAM Read, write or row op request packet
! FLAG || CA9 || CA8 || CA7 || CA6 || CA5 || CA4 || CA3 || CA2 || CA1 || CA0
|-
! 1
|bgcolor=#ffcccc| ID8 ||colspan=7"9" bgcolor="#ffccccFFCCCC"| Device ID ||bgcolor=#ffcccc| ID08:0 ||bgcolor="#ccffccCCFFCC"| CMD5Co...
|-
! 0
|colspan=4"5" bgcolor="#ccffcc"| Command...mmand codeCode ||bgcolor=#ccffcc| CMD05:0 ||colspan="3" bgcolor="#ff88ffeeAAff"| Bank Addr. 2:0 ||colspan="2" bgcolor="#ffffcc"| RowRo...
|-
! 0
|colspan=9 bgcolor=#ffffcc| Row...w (continued)Address 11:0 ||bgcolor=lightgreywhite| 0
|-
! 0
|bgcolorcolspan=lightgrey|"3" 0 ||bgcolor=lightgrey"white"| 0 ||bgcolor=lightgrey|0 0 ||colspan="7" bgcolor="#ccffff"| Column address 6:0
|}
 
* 9 bits of deviceDevice ID
* 6 bits of commandCommand Code
* 3 bits of bankBank address
* 10 or 11 bits of row address
* 5 or 4 bits spare for row or column expansion
Line 354:
The above are the JEDEC-standardized commands. Earlier chips did not support the dummy channel or pair prefetch, and use a different encoding for precharge.
 
A 13-bit address bus, as illustrated here, is suitable for a device up to 128&nbsp;Mbit{{binpre}}. It has two banks, each containing 8,192 rows and 8,192 columns. Thus, row addresses are 13 bits, segment addresses are two bits, and eight column address bits are required to select one byte from the 2,048 bits (256 bytes) in a segment.
 
== {{Anchor|SGRAM}}Synchronous Graphics RAM (SGRAM) ==
Line 364:
{{Main|GDDR SDRAM}}
 
Graphics [[double data rate]] SDRAM ([[GDDR SDRAM]]) is a type of specialized [[DDR SDRAM]] designed to be used as the main memory of [[graphics processing unit]]s (GPUs). GDDR SDRAM is distinct from commodity types of DDR SDRAM such as DDR3, although they share some core technologies. Their primary characteristics are higher clock frequencies for both the DRAM core and I/O interface, which provides greater memory bandwidth for GPUs. As of 20232025, there are eightnine successive generations of GDDR: [[GDDR2]], [[GDDR3]], [[GDDR4]], [[GDDR5]], [[GDDR5X]], [[GDDR6]], [[GDDR6X]], [[GDDR6W]], and [[GDDR6WGDDR7]].
 
GDDR was initially known as DDR SGRAM. It was commercially introduced as a 16{{nbsp}}[[Megabit|Mbit]]{{binpre}} memory chip by [[Samsung Electronics]] in 1998.<ref name="samsung98"/>
Line 378:
=== SDRAM ===
<section begin="SDRAM timeline"/>
{| class="wikitable sortable" style="text-align:center; white-space:nowrap;"
|+ Synchronous dynamic random-access memory (SDRAM)
|-
! style="line-height:110%"|Date of<br>intro-<br>duction
! Date of introduction
! Chip <br>name
! Capacity <br>([[bit]]s){{binpre|first}}
! SDRAM <br>type
! ManufacturerManufac-<br>turer(s)
! data-sort-type="number" |[[Semiconductor device fabrication|ProcessPro-<br>cess]]
! [[MOSFET|MOS-<br>FET]]
! data-sort-type="number" | Area<br>(mm<sup>2</sup>)
! {{Abbr|Ref|Reference(s)}}
|-
Line 396:
|[[SDR SDRAM|SDR]]
|[[Samsung Electronics|Samsung]]
|style="color:#AAAAAA"| ''?''
|{{?}}
|[[CMOS]]
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref name="KM48SL2000">{{cite web |title=KM48SL2000-7 Datasheet |url=https://www.datasheetarchive.com/KM48SL2000-7-datasheet.html |publisher=[[Samsung]] |access-date=19 June 2019 |date=August 1992}}</ref><ref name="electronic-design"/>
|-
Line 406:
|[[RDRAM]]
|[[Oki Electric Industry|Oki]]
|style="color:#AAAAAA"| ''?''
|{{?}}
|CMOS
|325
|325&nbsp;mm<sup>2</sup>
|<ref name="oki-rdram">{{cite web |title=MSM5718C50/MD5764802 |url=https://retrocdn.net/images/c/c3/Oki_Concurrent_RDRAM_datasheet.pdf |archive-url=https://web.archive.org/web/20190621151518/https://retrocdn.net/images/c/c3/Oki_Concurrent_RDRAM_datasheet.pdf |archive-date=2019-06-21 |url-status=live |publisher=[[Oki Electric Industry|Oki Semiconductor]] |date=February 1999 |access-date=21 June 2019}}</ref>
|-
Line 415:
|RDRAM
|[[NEC]]
|style="color:#AAAAAA"| ''?''
|{{?}}
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref>{{cite magazine|title=Ultra 64 Tech Specs|magazine=[[Next Generation (magazine)|Next Generation]]|issue=14 |publisher=[[Imagine Media]] |date=February 1996|page=40}}</ref>
|-
|style="color:#AAAAAA"| ''?''
|{{?}}
|1024 Mbit
|SDR
Line 426:
|[[180 nanometer|150&nbsp;nm]]
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref name="stol">{{cite web|url=http://maltiel-consulting.com/Semiconductor_technology_memory.html|title=Memory|website=STOL (Semiconductor Technology Online)|access-date=25 June 2019}}</ref>
|-
|1997
|style="color:#AAAAAA"| ''?''
|{{?}}
|1024 Mbit
|SDR
|[[Hyundai Electronics|Hyundai]]
|style="color:#AAAAAA"| ''?''
|{{?}}
|[[Silicon on insulator|SOI]]
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref name="hynix90s">{{cite web |title=History: 1990s |url=http://www.az5miao.com/history1990.html |access-date=4 April 2022 |website=az5miao}}</ref>
|<ref name="hynix90s"/>
|-
|1998
Line 444:
|RDRAM
|Oki
|style="color:#AAAAAA"| ''?''
|{{?}}
|CMOS
|325
|325&nbsp;mm<sup>2</sup>
|<ref name="oki-rdram"/>
|-
|{{sort|1998|March Mar&nbsp;1998}}
|Direct RDRAM
|72 Mbit
|RDRAM
|[[Rambus]]
|style="color:#AAAAAA"| ''?''
|{{?}}
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref>{{cite web |title=Direct RDRAM |url=https://retrocdn.net/images/6/68/Direct_RDRAM_datasheet.pdf |archive-url=https://web.archive.org/web/20190621151523/https://retrocdn.net/images/6/68/Direct_RDRAM_datasheet.pdf |archive-date=2019-06-21 |url-status=live |publisher=[[Rambus]] |date=12 March 1998 |access-date=21 June 2019}}</ref>
|-
|{{sort|1998|June Jun&nbsp;1998}}
|style="color:#AAAAAA"| ''?''
|{{?}}
|64 Mbit
|[[DDR SDRAM|DDR]]
|Samsung
|style="color:#AAAAAA"| ''?''
|{{?}}
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref name="samsung98">{{cite news |title=Samsung Electronics Comes Out with Super-Fast 16M DDR SGRAMs |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-comes-out-with-super-fast-16m-ddr-sgrams/ |access-date=23 June 2019 |work=[[Samsung Electronics]] |publisher=[[Samsung]] |date=17 September 1998}}</ref><ref name="samsung99">{{cite news |title=Samsung Electronics Develops First 128Mb SDRAM with DDR/SDR Manufacturing Option |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-develops-first-128mb-sdram-with-ddr-sdr-manufacturing-option/ |access-date=23 June 2019 |work=[[Samsung Electronics]] |publisher=[[Samsung]] |date=10 February 1999}}</ref><ref name="phys">{{cite news |title=Samsung Demonstrates World's First DDR 3 Memory Prototype |url=https://phys.org/news/2005-02-samsung-world-ddr-memory-prototype.html |access-date=23 June 2019 |work=[[Phys.org]] |date=17 February 2005 |language=en-us}}</ref>
|-
| rowspan="2" |1998
| rowspan="2" style="color:#AAAAAA"|{{ ''?}}''
|64 Mbit
|DDR
|Hyundai
|style="color:#AAAAAA"| ''?''
|{{?}}
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref name="hynix90s"/>
|-
Line 482:
|SDR
|Samsung
|style="color:#AAAAAA"| ''?''
|{{?}}
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref name="samsung-history">{{cite web |title=History |url=https://www.samsung.com/us/aboutsamsung/company/history/ |website=[[Samsung Electronics]] |publisher=[[Samsung]] |access-date=19 June 2019}}</ref><ref name="samsung99"/>
|-
| rowspan="2" |1999
| rowspan="2" style="color:#AAAAAA"|{{ ''?}}''
|128 Mbit
|DDR
|Samsung
|style="color:#AAAAAA"| ''?''
|{{?}}
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref name="samsung99"/>
|-
Line 502:
|[[130 nanometer|140 nm]]
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref name="stol"/>
|-
Line 512:
|[[180 nm]]
|CMOS
|279
|279&nbsp;mm<sup>2</sup>
|<ref name="sony2003">{{cite news |title=EMOTION ENGINE AND GRAPHICS SYNTHESIZER USED IN THE CORE OF PLAYSTATION BECOME ONE CHIP |url=https://www.sie.com/content/dam/corporate/en/corporate/release/pdf/030421be.pdf |archive-url=https://web.archive.org/web/20170227150247/https://www.sie.com/content/dam/corporate/en/corporate/release/pdf/030421be.pdf |archive-date=2017-02-27 |url-status=live |access-date=26 June 2019 |publisher=[[Sony]] |date=April 21, 2003}}</ref>
|-
| rowspan="2" |2001
| rowspan="2" style="color:#AAAAAA"|{{ ''?}}''
|288 Mbit
|RDRAM
|Hynix
|style="color:#AAAAAA"| ''?''
|{{?}}
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref name="hynix2000s">{{cite web |title=History: 2000s |url=http://www.az5miao.com/history2000.html |access-date=4 April 2022 |website=az5miao}}</ref>
|-
|style="color:#AAAAAA"| ''?''
|{{?}}
|[[DDR2 SDRAM|DDR2]]
|Samsung
|[[100 nm]]
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref name="phys"/><ref name="stol"/>
|-
|2002
|style="color:#AAAAAA"| ''?''
|{{?}}
|256 Mbit
|SDR
|Hynix
|style="color:#AAAAAA"| ''?''
|{{?}}
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref name="hynix2000s"/>
|-
Line 550:
|[[90 nm]]
|CMOS
|{{0}}86
|86&nbsp;mm<sup>2</sup>
|<ref name="sony2003"/>
|-
| rowspan="4" style="color:#AAAAAA"|{{ ''?}}''
|72 Mbit
|[[DDR3]]
Line 559:
|90&nbsp;nm
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref>{{cite news |title=Samsung Develops the Industry's Fastest DDR3 SRAM for High Performance EDP and Network Applications |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-develops-the-industrys-fastest-ddr3-sram-for-high-performance-edp-and-network-applications/ |access-date=25 June 2019 |work=[[Samsung Semiconductor]] |publisher=[[Samsung]] |date=29 January 2003}}</ref>
|-
Line 565:
| rowspan="2" |DDR2
|Hynix
|style="color:#AAAAAA"| ''?''
|{{?}}
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref name="hynix2000s"/>
|-
Line 573:
|[[110 nanometer|110 nm]]
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref>{{cite news |title=Elpida ships 2GB DDR2 modules |url=https://www.theinquirer.net/inquirer/news/1044210/elpida-ships-2gb-ddr2-modules |archive-url=https://web.archive.org/web/20190710115030/https://www.theinquirer.net/inquirer/news/1044210/elpida-ships-2gb-ddr2-modules |url-status=unfit |archive-date=July 10, 2019 |access-date=25 June 2019 |work=[[The Inquirer]] |date=4 November 2003}}</ref>
|-
Line 579:
|DDR2
|Hynix
|style="color:#AAAAAA"| ''?''
|{{?}}
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref name="hynix2000s"/>
|-
|2004
|style="color:#AAAAAA"| ''?''
|{{?}}
|2048 Mbit
|DDR2
Line 591:
|80&nbsp;nm
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref name="samsung2004">{{cite news |title=Samsung Shows Industry's First 2-Gigabit DDR2 SDRAM |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-shows-industrys-first-2-gigabit-ddr2-sdram/ |access-date=25 June 2019 |work=[[Samsung Semiconductor]] |publisher=[[Samsung]] |date=20 September 2004}}</ref>
|-
Line 601:
|[[65 nm]]
|CMOS
|{{0}}86
|86&nbsp;mm<sup>2</sup>
|<ref name="impress">{{cite web|url=https://pc.watch.impress.co.jp/docs/2003/0421/sony1.htm|title=ソニー、65nm対応の半導体設備を導入。3年間で2,000億円の投資|website=pc.watch.impress.co.jp|url-status=live|archive-url=https://web.archive.org/web/20160813020249/http://pc.watch.impress.co.jp/docs/2003/0421/sony1.htm|archive-date=2016-08-13}}</ref>
|-
Line 610:
|90&nbsp;nm
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref>ATI engineers by way of Beyond 3D's Dave Baumann</ref>
|-
|style="color:#AAAAAA"| ''?''
|{{?}}
|512 Mbit
|DDR3
Line 619:
|80&nbsp;nm
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref name="phys"/><ref name="samsung2000s">{{cite web |title=Our Proud Heritage from 2000 to 2009 |url=https://www.samsung.com/semiconductor/about-us/history-03/ |website=[[Samsung Semiconductor]] |publisher=[[Samsung]] |access-date=25 June 2019}}</ref>
|-
|2006
|style="color:#AAAAAA"| ''?''
|{{?}}
|1024 Mbit
|DDR2
Line 629:
|60&nbsp;nm
|rowspan="2" | CMOS
|rowspan="2" style="color:#AAAAAA"| {{''?}}''
|rowspan="2" | <ref name="hynix2000s"/>
|-
|2008
|style="color:#AAAAAA"| ''?''
|{{?}}
|style="color:#AAAAAA"| ''?''
|{{?}}
|[[LPDDR2]]
|Hynix
|style="color:#AAAAAA"| ''?''
|{{?}}
|-
|{{sort|2008|April Apr&nbsp;2008}}
|style="color:#AAAAAA"| ''?''
|{{?}}
|8192 Mbit
|DDR3
Line 646:
|50&nbsp;nm
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|rowspan="2" | <ref>{{cite news |title=Samsung 50nm 2GB DDR3 chips are industry's smallest |url=https://www.slashgear.com/samsung-50nm-2gb-ddr3-chips-are-industrys-smallest-2917676/ |access-date=25 June 2019 |work=SlashGear |date=29 September 2008}}</ref>
|-
|2008
|style="color:#AAAAAA"| ''?''
|{{?}}
|16384 Mbit
|DDR3
Line 656:
|50&nbsp;nm
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|-
| rowspan="2" |2009
| rowspan="2" style="color:#AAAAAA"|{{ ''?}}''
|style="color:#AAAAAA"| ''?''
|{{?}}
|DDR3
|Hynix
|[[45 nanometer|44 nm]]
|rowspan="2" | CMOS
|rowspan="2" style="color:#AAAAAA"| {{''?}}''
|rowspan="2" | <ref name="hynix2000s"/>
|-
Line 674:
|-
| rowspan="2" |2011
| rowspan="2" style="color:#AAAAAA"|{{ ''?}}''
|16384 Mbit
|DDR3
Line 680:
|40&nbsp;nm
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref name="hynix2010s">{{cite web |title=History: 2010s |url=http://www.az5miao.com/history2010.html |website=az5miao |access-date=4 April 2022}}</ref>
|-
Line 688:
|[[32 nanometer|30&nbsp;nm]]
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref name="hynix2010s"/>
|-
|2013
|style="color:#AAAAAA"| ''?''
|{{?}}
|style="color:#AAAAAA"| ''?''
|{{?}}
|[[LPDDR4]]
|Samsung
|[[20 nm]]
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref name="hynix2010s"/>
|-
|2014
|style="color:#AAAAAA"| ''?''
|{{?}}
|8192 Mbit
|LPDDR4
Line 708:
|20&nbsp;nm
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref>{{cite web |title=Our Proud Heritage from 2010 to Now |url=https://www.samsung.com/semiconductor/about-us/history-04/ |website=[[Samsung Semiconductor]] |publisher=[[Samsung]] |access-date=25 June 2019}}</ref>
|-
|2015
|style="color:#AAAAAA"| ''?''
|{{?}}
|12 Gbit
|LPDDR4
Line 718:
|20&nbsp;nm
|CMOS
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref name="samsung-history"/>
|-
| rowspan="2" |2018
| rowspan="2" style="color:#AAAAAA"|{{ ''?}}''
|8192 Mbit
|[[LPDDR#LP-DDR5|LPDDR5]]
Line 728:
|[[10 nm process|10 nm]]
|[[FinFET]]
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref>{{cite news |title=Samsung Electronics Announces Industry's First 8Gb LPDDR5 DRAM for 5G and AI-powered Mobile Applications |url=https://news.samsung.com/global/samsung-electronics-announces-industrys-first-8gb-lpddr5-dram-for-5g-and-ai-powered-mobile-applications |access-date=8 July 2019 |publisher=[[Samsung]] |date=July 17, 2018}}</ref>
|-
Line 736:
|10&nbsp;nm
|FinFET
|style="color:#AAAAAA"| ''?''
|{{?}}
|<ref>{{cite news |date=6 September 2018 |title=Samsung Unleashes a Roomy DDR4 256GB RAM |work=[[Tom's Hardware]] |url=https://www.tomshardware.co.uk/samsung-256gb-ddr4-ram,news-59123.html |url-status=dead |access-date=4 April 2022 |archive-url=https://web.archive.org/web/20190621205106if_/https://www.tomshardware.co.uk/samsung-256gb-ddr4-ram,news-59123.html |archive-date=June 21, 2019}}</ref>
|}
 
=== SGRAM and HBM ===
{| class="wikitable sortable" style="text-align:center"
|+ [[Synchronous graphics random-access memory]] (SGRAM) and [[High Bandwidth Memory]] (HBM)
|-
! Date of introduction
Line 801:
|{{?}}
|CMOS
|280&nbsp;mm<sup>2</sup>
|{{?}}
|<ref>{{cite news |title=Samsung Announces the World's First 222 MHz 32Mbit SGRAM for 3D Graphics and Networking Applications |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-announces-the-worlds-first-222-mhz-32mbit-sgram-for-3d-graphics-and-networking-application/ |access-date=10 July 2019 |work=[[Samsung Semiconductor]] |publisher=[[Samsung]] |date=12 July 1999}}</ref>
|-
Line 884:
|4096 Mbit
|SGRAM (GDDR3)
|rowspan="2" | [[SK Hynix]]
|rowspan="2" | {{?}}
|rowspan="2" | CMOS
|rowspan="2" | {{?}}
|rowspan="2" | <ref name="hynix2010s"/>
|-
|2013
|{{?}}
|{{?}}
|[[High Bandwidth Memory|HBM]]
|-
|{{sort|2016|March 2016}}
Line 903 ⟶ 898:
|CMOS
|140&nbsp;mm<sup>2</sup>
|<ref>{{cite news |last1=Shilov |first1=Anton |title=Micron Begins to Sample GDDR5X Memory, Unveils Specs of Chips |url=https://www.anandtech.com/show/10193/micron-begins-to-sample-gddr5x-memory |archive-url=https://web.archive.org/web/20160330094652/http://www.anandtech.com/show/10193/micron-begins-to-sample-gddr5x-memory |url-status=dead |archive-date=March 30, 2016 |access-date=16 July 2019 |work=[[AnandTech]] |date=March 29, 2016}}</ref>
|-
|{{sort|2018|January 2018}}
|K4ZAF325BM
|16 Gbit
|SGRAM ([[GDDR6]])
|Samsung
|[[10 nm process|10 nm]]
|[[FinFET]]
|225&nbsp;mm<sup>2</sup>
|<ref>{{cite news |title=Samsung Electronics Starts Producing Industry's First 16-Gigabit GDDR6 for Advanced Graphics Systems |url=https://news.samsung.com/global/samsung-electronics-starts-producing-industrys-first-16-gigabit-gddr6-for-advanced-graphics-systems |access-date=15 July 2019 |publisher=[[Samsung]] |date=January 18, 2018}}</ref><ref name='tr_gddr6'>{{cite news|last1=Killian|first1=Zak|title=Samsung fires up its foundries for mass production of GDDR6 memory|url=https://techreport.com/news/33129/samsung-fires-up-its-foundries-for-mass-production-of-gddr6-memory|access-date=18 January 2018|publisher=Tech Report|date=18 January 2018}}</ref><ref>{{cite news |title=Samsung Begins Producing The Fastest GDDR6 Memory In The World |url=https://wccftech.com/samsung-gddr6-16gb-18gbps-mass-production-official/ |access-date=16 July 2019 |work=Wccftech |date=18 January 2018}}</ref>
|} <section end="SDRAM timeline"/>
 
=== HBM ===
{| class="wikitable sortable" style="text-align:center"
|+ [[High Bandwidth Memory]] (HBM)
|-
! Date of introduction
! Chip name
! Capacity ([[bit]]s){{binpre}}
! SDRAM type
! Manufacturer(s)
! data-sort-type="number" |[[Semiconductor device fabrication|Process]]
! [[MOSFET]]
! data-sort-type="number" | Area
! {{Abbr|Ref|Reference(s)}}
|-
|2013
|{{?}}
|{{?}}
|[[High Bandwidth Memory|HBM]]
|[[SK Hynix]]
|{{?}}
|CMOS
|{{?}}
|<ref name="hynix2010s" />
|-
|{{sort|2016|June 2016}}
Line 910 ⟶ 940:
|[[HBM2]]
|Samsung
|[[20&nbsp; nm]]
|CMOS
|{{?}}
|<ref name="Shilov2017">{{cite news |last1=Shilov |first1=Anton |date=July 19, 2017 |title=Samsung Increases Production Volumes of 8 GB HBM2 Chips Due to Growing Demand |url=https://www.anandtech.com/show/11643/samsung-increases-8gb-hbm2-production-volume |archive-url=https://web.archive.org/web/20170720000946/http://anandtech.com/show/11643/samsung-increases-8gb-hbm2-production-volume |url-status=dead |archive-date=July 20, 2017 |access-date=29 June 2019 |work=[[AnandTech]] |date=July 19, 2017}}</ref><ref>{{cite web |title=HBM |url=https://samsungsemiconductor-us.com/hbm/ |access-date=16 July 2019 |website=[[Samsung Semiconductor]] |publisher=[[Samsung]] |access-date=16 July 2019}}</ref>
|-
|2017
Line 923 ⟶ 953:
|CMOS
|{{?}}
|<ref name="Shilov2017" />
|-}
|{{sort|2018|January 2018}}
|K4ZAF325BM
|16 Gbit
|SGRAM ([[GDDR6]])
|Samsung
|[[10 nm process|10 nm]]
|[[FinFET]]
|225&nbsp;mm<sup>2</sup>
|<ref>{{cite news |title=Samsung Electronics Starts Producing Industry's First 16-Gigabit GDDR6 for Advanced Graphics Systems |url=https://news.samsung.com/global/samsung-electronics-starts-producing-industrys-first-16-gigabit-gddr6-for-advanced-graphics-systems |access-date=15 July 2019 |publisher=[[Samsung]] |date=January 18, 2018}}</ref><ref name='tr_gddr6'>{{cite news|last1=Killian|first1=Zak|title=Samsung fires up its foundries for mass production of GDDR6 memory|url=https://techreport.com/news/33129/samsung-fires-up-its-foundries-for-mass-production-of-gddr6-memory|access-date=18 January 2018|publisher=Tech Report|date=18 January 2018}}</ref><ref>{{cite news |title=Samsung Begins Producing The Fastest GDDR6 Memory In The World |url=https://wccftech.com/samsung-gddr6-16gb-18gbps-mass-production-official/ |access-date=16 July 2019 |work=Wccftech |date=18 January 2018}}</ref>
|} <section end="SDRAM timeline"/>
 
== See also ==
* [[GDDR]] (graphics DDR) and its subtypes [[GDDR2]], [[GDDR3]], [[GDDR4]], [[GDDR5]], [[GDDR6]] and [[GDDR7]]
* [[List of device bandwidths]]
* [[Serial presence detect]] -– EEPROM with timing data on SDRAM modules
* [http://taututorial.yolasite.com/ SDRAM Tutorial] -– Flash website built by Tel-Aviv University students
* A concise but thorough review of SDRAM architecture/terminology and command timing dependencies in [http://drum.lib.umd.edu/bitstream/1903/11269/1/Gross_umd_0117N_11844.pdf High-Performance DRAM System Design Constraints and Considerations], a master thesis from the University of Maryland.
 
Line 947 ⟶ 966:
 
== External links ==
* [https://web.archive.org/web/20121016082506/http://www.anandtech.com/show/3851/ Everything you always wanted to know about SDRAM (memory), but were afraid to ask], August 2010, [[AnandTech]]
* [http://www.hardwaresecrets.com/understanding-ram-timings/ Understanding RAM Timings], May 2011, Hardware Secrets
* [https://web.archive.org/web/20030803094457/http://developer.intel.com/technology/memory/pc133sdram/spec/sdram133.pdf PC SDRAM Specification, Rev 1.7]
* [https://web.archive.org/web/20030429115837/http://developer.intel.com/technology/memory/pc133sdram/spec/PC133sodm1_0c1.pdf 133MHz133&nbsp;MHz PC133 SDRAM SO-DIMM Specification]
* [https://web.archive.org/web/20030803113813/http://developer.intel.com/technology/memory/pc133sdram/spec/Spdsd12b.pdf PC SDRAM Serial Presence Detect (SPD) Specification, Rev 1.2B]
 
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