Synchronous dynamic random-access memory: Difference between revisions

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{{Memory types}}

[[File:SDRAM_memory_module.jpg|thumb|SDRAM memory module]]

'''Synchronous dynamic random-access memory''' ('''synchronous dynamic RAM''' or '''SDRAM''') is any [[Dynamic RAMrandom-access memory|DRAM]] where the operation of its external pin interface is coordinated by an externally supplied [[clock signal]].

DRAM [[integrated circuit]]s (ICs) produced from the early 1970s to the early 1990s used an ''asynchronous'' interface, in which input control signals have a direct effect on internal functions delayed only by the trip across its semiconductor pathways. SDRAM has a ''synchronous'' interface, whereby changes on control inputs are recognised after a rising edge of its clock input. In SDRAM families standardized by [[JEDEC]], the clock signal controls the stepping of an internal [[finite-state machine]] that responds to incoming commands. These commands can be pipelined to improve performance, with previously started operations completing while new commands are received. The memory is divided into several equally sized but independent sections called ''[[Memory bank|bank]]s'', allowing the device to operate on a memory access command in each bank simultaneously and speed up access in an [[Interleaved memory|interleaved]] fashion. This allows SDRAMs to achieve greater concurrency and higher data transfer rates than asynchronous DRAMs could.

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[[Image:SDR SDRAM-1.jpg|thumb|Eight [[Hyundai Electronics|Hyundai]] SDRAM ICs on a PC100 [[DIMM]] package]]

The earliest DRAMs were often synchronized with the CPU clock (clocked) and were used with early microprocessors. In the mid-1970s, DRAMs moved to the asynchronous design, but in the 1990s returned to synchronous operation.<ref>{{cite book | author=P. Darche | title=Microprocessor: Prolegomenes -– Calculation and Storage Functions -– Calculation Models and Computer | year=2020 | page=59 | publisher=John Wiley & Sons | isbn=9781786305633 | url=https://books.google.com/books?id=rLC9zQEACAAJ}}</ref><ref>{{cite book |author1=B. Jacob |author2=S. W. Ng |author3=D. T. Wang | title=Memory Systems: Cache, DRAM, Disk | year=2008 | publisher=Morgan Kaufmann | page=324 | isbn=9780080553849 | url=https://books.google.com/books?id=SrP3aWed-esC}}</ref> In the late 1980s [[IBM]] had built DRAMs using a [[double data rate|dual-edge clocking]] feature and presented their results at the International Solid-State Circuits Convention in 1990. However, it was standard [[DRAM]], not SDRAM.<ref>{{cite book |first1=B. |last1=Jacob |first2=S. W. |last2=Ng |first3=D. T. |last3=Wang | title=Memory Systems: Cache, DRAM, Disk | year=2008 | publisher=Morgan Kaufmann | page=333 | isbn=9780080553849 | url=https://books.google.com/books?id=SrP3aWed-esC}}</ref><ref>{{cite journal |first1=H. L. |last1=Kalter |first2=C. H. |last2=Stapper |first3=J. E. |last3=Barth |first4=J. |last4=Dilorenzo |first5=C. E. |last5=Drake |first6=J. A. |last6=Fifield |first7=G. A. |last7=Kelley |first8=S. C. |last8=Lewis |first9=W. B. |last9=van der Hoeven |first10=J. A. |last10=Jankosky | title=A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC | year=1990 | journal=IEEE Journal of Solid-State Circuits | volume=25 | issue=5| page=1118 | doi=10.1109/4.62132 | bibcode=1990IJSSC..25.1118K }}</ref>

InThe thefirst late 1980s [[IBM]] invented DDRcommercial SDRAM, they built a [[Double data rate|dual-edge clocking]] RAM and presented their results atwas the International Solid-State Circuits Convention in 1990.<ref>{{cite book |last1=Jacob |first1=B. |url=https://books.google.com/books?id=SrP3aWed-esC |title=Memory Systems: Cache, DRAM, Disk |last2=Ng |first2=S. W. |last3=Wang |first3=D. T. |publisher=Morgan Kaufmann |year=2008 |isbn=9780080553849 |page=333}}</ref><ref>{{cite journal |last1=Kalter |first1=H. L. |last2=Stapper |first2=C. H. |last3=Barth |first3=J. E. |last4=Dilorenzo |first4=J. |last5=Drake |first5=C. E. |last6=Fifield |first6=J. A. |last7=Kelley |first7=G. A. |last8=Lewis |first8=S. C. |last9=van der Hoeven |first9=W. B. |last10=Jankosky |first10=J. A. |year=1990 |title=A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC |journal=IEEE Journal of Solid-State Circuits |volume=25 |issue=5 |page=1118 |bibcode=1990IJSSC..25.1118K |doi=10.1109/4.62132}}</ref> In 1998, [[Samsung]] released aKM48SL2000 [[doublememory data ratechip]] SDRAM, knownwhich ashad [[DDRa SDRAM]],capacity chipof (6416{{nbsp}}[[Megabit|Mbit]]) followed soon after by [[Hyundai Electronics]] (now [[SK Hynix]]) the same year and mass-produced in 1993.<ref name="electronic-design">{{cite journal |date=1993 |title=Electronic Design |url=https://books.google.com/books?id=QmpJAQAAIAAJ |journal=[[Electronic Design]] |publisher=Hayden Publishing Company |volume=41 |issue=15–21 |quote=The first commercial synchronous DRAM, the Samsung 16-Mbit KM48SL2000, employs a single-bank architecture that lets system designers easily transition from asynchronous to synchronous systems.}}</ref> It was manufactured by [[Samsung Electronics]] using a [[CMOS]] (complementary [[metal–oxide–semiconductor]]) [[fabrication process]] in 1992,<ref name="KM48SL2000"/> and mass-produced in 1993.<ref name="electronic-design"/> By 2000, SDRAM had replaced virtually all other types of [[DRAM]] in modern computers, because of its greater performance.

SDRAM latency is not inherently lower (faster access times) than asynchronous DRAM. Indeed, early SDRAM was somewhat slower than contemporaneous [[burst EDO DRAM]] due to the additional logic. The benefits of SDRAM's internal buffering come from its ability to interleave operations to multiple banks of memory, thereby increasing effective [[Bandwidth (computing)|bandwidth]].

[[Double data rate]] SDRAM, known as [[DDR SDRAM]], was first demonstrated by Samsung in 1997.<ref name="techpowerup">{{cite web |title=Samsung 30 nm Green PC3-12800 Low Profile 1.35 V DDR3 Review |url=https://www.techpowerup.com/review/samsung-mv-3v4g3/ |website=TechPowerUp |access-date=25 June 2019 |date= March 8, 2012}}</ref> Samsung released the first commercial DDR SDRAM chip (64{{nbsp}}Mbit{{binpre}}) in June 1998,<ref name="samsung99"/><ref name="samsung98"/><ref name="phys"/> followed soon after by [[Hyundai Electronics]] (now [[SK Hynix]]) the same year.<ref name="hynix90s"/>

Today, virtually all SDRAM is manufactured in compliance with standards established by [[JEDEC]], an electronics industry association that adopts [[open standards]] to facilitate interoperability of electronic components. JEDEC formally adopted its first SDRAM standard in 1993 and subsequently adopted other SDRAM standards, including those for [[DDR SDRAM|DDR]], [[DDR2 SDRAM|DDR2]] and [[DDR3 SDRAM]].

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== Timing ==

There are several limits on DRAM performance. Most noted is the read cycle time, the time between successive read operations to an open row. This time decreased from 1015&nbsp;ns for 10066&nbsp;MHz SDRAM (1&nbsp;MHz = 10<mathsup>10^{6}</mathsup>&nbsp;Hz) to 5&nbsp;ns for DDR-400, but remained relatively unchanged through DDR2-800 and DDR3-1600 generations. However, by operating the interface circuitry at increasingly higher multiples of the fundamental read rate, the achievable bandwidth has increased rapidly.

Another limit is the [[CAS latency]], the time between supplying a column address and receiving the corresponding data. Again, this has remained relatively constant at 10–15 ns through the last few generations of DDR SDRAM.

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In operation, CAS latency is a specific number of clock cycles programmed into the SDRAM's mode register and expected by the DRAM controller. Any value may be programmed, but the SDRAM will not operate correctly if it is too low. At higher clock rates, the useful CAS latency in clock cycles naturally increases. 10–15&nbsp;ns is 2–3 cycles (CL2–3) of the 200&nbsp;MHz clock of DDR-400 SDRAM, CL4-6 for DDR2-800, and CL8-12 for DDR3-1600. Slower clock cycles will naturally allow lower numbers of CAS latency cycles.

SDRAM modules have their own timing specifications, which may be slower than those of the chips on the module. When 100&nbsp;MHz SDRAM chips first appeared, some manufacturers sold "100&nbsp;MHz" modules that could not reliably operate at that clock rate. In response, Intel published the PC100 standard, which outlines requirements and guidelines for producing a memory module that can operate reliably at 100&nbsp;MHz. This standard was widely influential, and the term "PC100" quickly became a common identifier for 100&nbsp;MHz SDRAM modules, and modules are now commonly designated with "PC"-prefixed numbers (PC66, PC100 or PC133 -– although the actual meaning of the numbers has changed).

== Control signals ==

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* M8, M7: Operating mode. Reserved, and must be 00.

* M6, M5, M4: CAS latency. Generally only 010 (CL2) and 011 (CL3) are legal. Specifies the number of cycles between a read command and data output from the chip. The chip has a fundamental limit on this value in nanoseconds; during initialization, the memory controller must use its knowledge of the clock frequency to translate that limit into cycles.

* M3: Burst type. 0 -– requests sequential burst ordering, while 1 requests interleaved burst ordering.

* M2, M1, M0: Burst length. Values of 000, 001, 010 and 011 specify a burst size of 1, 2, 4 or 8 words, respectively. Each read (and write, if M9 is 0) will perform that many accesses, unless interrupted by a burst stop or other command. A value of 111 specifies a full-row burst. The burst will continue until interrupted. Full-row bursts are only permitted with the sequential burst type.

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! scope="row" | SDRAM

| {{Unbulleted list

| {{Nowrap|V{{Sub|cc}} {{=}} 3.3&#8239nbsp;V}}

| Signal: [[Transistor–transistor logic#Sub-types|LVTTL]]

}}

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! scope="row" | [[DDR SDRAM|DDR1]]

| {{Unbulleted list

| Access is ≥&#8239nbsp;2 words

| [[Double data rate|Double clocked]]

| {{Nowrap|V{{Sub|cc}} {{=}} 2.5&#8239nbsp;V}}

| {{Nowrap|2.5&#8239nbsp;−&#8239nbsp;7.5&#8239nbsp;ns}} per cycle

| Signal: [[Stub Series Terminated Logic|SSTL_2]] (2.5&#8239nbsp;V)<ref name="edn-dramconsumer">{{cite web|title=The outlook for DRAMs in consumer electronics|url=https://www.edn.com/the-outlook-for-drams-in-consumer-electronics/|last=Graham |first=Allan |publisher=AspenCore Media |website=EDN|date=2007-01-12 |access-date=2021-04-13}}</ref>

}}

|-

! scope="row" | [[DDR2 SDRAM|DDR2]]

| Access is ≥&#8239nbsp;4 words<br/> "Burst terminate" removed<br/> 4 units used in parallel<br/> {{Nowrap|1.25&#8239nbsp;−&#8239nbsp;5ns}} per cycle<br/> Internal operations are<br>&nbsp;at 1/2 the clock rate.<br/> Signal: [[Stub Series Terminated Logic|SSTL_18]] (1.8&#8239nbsp;V)<ref name="edn-dramconsumer"/>

|-

! scope="row" | [[DDR3 SDRAM|DDR3]]

| Access is ≥&#8239nbsp;8 words<br/> Signal: [[Stub Series Terminated Logic|SSTL_15]] (1.5&#8239nbsp;V)<ref name="edn-dramconsumer"/><br/> Much longer CAS latencies

|-

! scope="row" | [[DDR4 SDRAM|DDR4]]

| {{Nowrap|V{{Sub|cc}} ≤&#8239nbsp;1.2&#8239nbsp;V}} point-to-point<br>(single module per channel)

|}

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Again, with every doubling, the downside is the increased [[Latency (engineering)|latency]]. As with all DDR SDRAM generations, commands are still restricted to one clock edge and command latencies are given in terms of clock cycles, which are half the speed of the usually quoted transfer rate (a [[CAS latency]] of 8 with DDR3-800 is 8/(400&nbsp;MHz) = 20 ns, exactly the same latency of CAS2 on PC100 SDR SDRAM).

DDR3 memory chips are being made commercially,<ref>{{cite web|url=http://www.simmtester.com/page/news/showpubnews.asp?num=145|title=What is DDR memory?}}</ref> and computer systems using them were available from the second half of 2007,<ref>{{cite news|url=http://www.tomshardware.com/2007/06/05/pipe_dreams_six_p35-ddr3_motherboards_compared/|title=Pipe Dreams: Six P35-DDR3 Motherboards Compared |date=June 5, 2007 |author=Thomas Soderstrom |newspaper=Tom's Hardware}}</ref> with significant usage from 2008 onwards.<ref>{{cite web|url=http://news.softpedia.com/news/AMD-to-Adopt-DDR3-in-Three-Years-13486.shtml|title=AMD to Adopt DDR3 in Three Years|date=28 November 2005}}</ref> Initial clock rates were 400 and 533&nbsp;MHz, which are described as DDR3-800 and DDR3-1066 (PC3-6400 and PC3-8500 modules), but 667 and 800&nbsp;MHz, described as DDR3-1333 and DDR3-1600 (PC3-10600 and PC3-12800 modules) are now common.<ref>{{cite web|url=http://www.anandtech.com/printarticle.aspx?i=3045|archive-url=https://archive.today/20120719141605/http://www.anandtech.com/printarticle.aspx?i=3045|url-status=dead|archive-date=July 19, 2012|title=Super Talent & TEAM: DDR3-1600 Is Here! |date=July 20, 2007 |author=Wesly Fink |publisher=Anandtech}}</ref> Performance up to DDR3-2800 (PC3 22400 modules) are available.<ref>{{cite web |url=http://hothardware.com/News/GSKILL-Announces-DDR3-Memory-Kit-For-Ivy-Bridge/ |title=G.SKILL Announces DDR3 Memory Kit For Ivy Bridge |date=24 April 2012 |author=Jennifer Johnson}}</ref>

=== DDR4 ===

{{Main|DDR4 SDRAM}}

DDR4 SDRAM is the successor to [[DDR3 SDRAM]]. It was revealed at the [[Intel Developer Forum]] in San Francisco in 2008, and was due to be released to market during 2011. The timing varied considerably during its development -– it was originally expected to be released in 2012,<ref>[http://intel.wingateweb.com/US08/published/sessions/MASS006/SF08_MASS006_100s.pdf DDR4 PDF page 23]</ref> and later (during 2010) expected to be released in 2015,<ref>{{cite web|url=http://www.semiaccurate.com/2010/08/16/ddr4-not-expected-until-2015/|title=DDR4 not expected until 2015|work=semiaccurate.com|date=16 August 2010}}</ref> before samples were announced in early 2011 and manufacturers began to announce that commercial production and release to market was anticipated in 2012. DDR4 reached mass market adoption around 2015, which is comparable with the approximately five years taken for DDR3 to achieve mass market transition over DDR2.

The DDR4 chips run at 1.2&nbsp;[[Volt|V]] or less,<ref>{{cite web|url=http://www.pcpro.co.uk/news/220257/idf-ddr3-wont-catch-up-with-ddr2-during-2009.html|title=IDF: "DDR3 won't catch up with DDR2 during 2009"|work=Alphr}}</ref><ref>{{cite web|url=http://www.heise-online.co.uk/news/IDF-DDR4-the-successor-to-DDR3-memory--/111367|title=heise online -– IT-News, Nachrichten und Hintergründe|work=heise online}}</ref> compared to the 1.5&nbsp;V of DDR3 chips, and have in excess of 2 billion [[data transfer]]s per second. They were expected to be introduced at frequency rates of 2133&nbsp;MHz, estimated to rise to a potential 4266&nbsp;MHz<ref>{{cite web |url=http://www.xbitlabs.com/news/memory/display/20100816124343_Next_Generation_DDR4_Memory_to_Reach_4_266GHz_Report.html |title=Next-Generation DDR4 Memory to Reach 4.266GHz -– Report |date=August 16, 2010 |publisher=Xbitlabs.com |access-date=2011-01-03 |url-status=dead |archive-url=https://web.archive.org/web/20101219085440/http://www.xbitlabs.com/news/memory/display/20100816124343_Next_Generation_DDR4_Memory_to_Reach_4_266GHz_Report.html |archive-date=December 19, 2010 }}</ref> and lowered voltage of 1.05&nbsp;V<ref>{{cite news|url=http://www.hardware-infos.com/news.php?news=2332|title=IDF: DDR4 memory targeted for 2012|publisher=hardware-infos.com|language=de|access-date=2009-06-16|archive-url=https://web.archive.org/web/20090713025046/http://www.hardware-infos.com/news.php?news=2332|archive-date=2009-07-13|url-status=dead}}</ref> by 2013.

DDR4 did ''not'' double the internal prefetch width again, but uses the same 8''n'' prefetch as DDR3.<ref name="jedec_ddr3_ddr4">{{cite press release |url=http://www.jedec.org/news/pressreleases/jedec-announces-key-attributes-upcoming-ddr4-standard |title=JEDEC Announces Key Attributes of Upcoming DDR4 Standard |publisher=[[JEDEC]] |date=2011-08-22 |access-date=2011-01-06}}</ref> Thus, it will be necessary to interleave reads from several banks to keep the data bus busy.

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{{Main|DDR5 SDRAM}}

In March 2017, JEDEC announced a DDR5 standard is under development,<ref>{{cite press release |title=JEDEC DDR5 & NVDIMM-P Standards Under Development |url=https://www.jedec.org/news/pressreleases/jedec-ddr5-nvdimm-p-standards-under-development |date=30 March 2017 |publisher=[[JEDEC]]}}</ref> but provided no details except for the goals of doubling the bandwidth of DDR4, reducing power consumption, and publishing the standard in 2018. The standard was released on 14 July 2020.<ref name="anandtech-ddr5">{{cite web|url=https://www.anandtech.com/show/15912/ddr5-specification-released-setting-the-stage-for-ddr56400-and-beyond|archive-url=https://web.archive.org/web/20200714225042/https://www.anandtech.com/show/15912/ddr5-specification-released-setting-the-stage-for-ddr56400-and-beyond|url-status=dead|archive-date=July 14, 2020|title=DDR5 Memory Specification Released: Setting the Stage for DDR5-6400 And Beyond|last=Smith|first=Ryan|date=2020-07-14|website=AnandTech|access-date=2020-07-15}}</ref>

== Failed successors ==

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=== Synchronous-link DRAM (SLDRAM) ===

SLDRAM boasted higher performance and competed against RDRAM. It was developed during the late 1990s by the SLDRAM Consortium. The SLDRAM Consortium consisted of about 20 major DRAM and computer industry manufacturers. (The SLDRAM Consortium became incorporated as SLDRAM Inc. and then changed its name to Advanced Memory International, Inc.) SLDRAM was an [[open standard]] and did not require licensing fees. The specifications called for a 64-bit bus running at a 200, 300 or 400&nbsp;MHz clock frequency. This is achieved by all signals being on the same line and thereby avoiding the synchronization time of multiple lines. Like [[DDR SDRAM]], SLDRAM uses a double-pumped bus, giving it an effective speed of 400,<ref>{{Citation |url=http://www.tomshardware.com/reviews/ram-guide,89-15.html |title=RAM Guide: SLDRAM |author=Dean Kent |publisher=Tom's Hardware |date=1998-10-24 |access-date=2011-01-01}}</ref> 600,<ref>{{Citation |url=http://icwic.cn/icwic/data/pdf/cd/cd011/12452.pdf |title=HYSL8M18D600A 600 Mb/s/pin 8M x 18 SLDRAM |type=data sheet |author=Hyundai Electronics |date=1997-12-20 |access-date=2011-12-27 |archive-url=https://web.archive.org/web/20120426081302/http://icwic.cn/icwic/data/pdf/cd/cd011/12452.pdf |archive-date=2012-04-26 |url-status=dead }}</ref> or 800&nbsp;[[MT/s]]. (1&#8239nbsp;MT/s&#8239nbsp;=&#8239nbsp;1000² transfers per second)

SLDRAM used an 11-bit command bus (10 command bits CA9:0 plus one start-of-command FLAG line) to transmit 40-bit command packets on 4 consecutive edges of a differential command clock (CCLK/CCLK#). Unlike SDRAM, there were no per-chip select signals; each chip was assigned an ID when reset, and the command contained the ID of the chip that should process it. Data was transferred in 4- or 8-word bursts across an 18-bit (per chip) data bus, using one of two differential data clocks (DCLK0/DCLK0# and DCLK1/DCLK1#). Unlike standard SDRAM, the clock was generated by the data source (the SLDRAM chip in the case of a read operation) and transmitted in the same direction as the data, greatly reducing data skew. To avoid the need for a pause when the source of the DCLK changes, each command specified which DCLK pair it would use.<ref>{{Citation |url=http://icwic.cn/icwic/data/pdf/cd/cd011/12407.pdf |pages=32–33 |title=SLD4M18DR400 400 Mb/s/pin 4M x 18 SLDRAM |type=data sheet |author=SLDRAM Inc. |date=1998-07-09 |access-date=2011-12-27 |archive-url=https://web.archive.org/web/20120426081159/http://icwic.cn/icwic/data/pdf/cd/cd011/12407.pdf |archive-date=2012-04-26 |url-status=dead }}</ref>

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|-

! 0

|colspan="3" bgcolor="white"| 0&emsp; 0&emsp; 0 ||colspan="7" bgcolor="#ccffff"| Column address 6:0

|}

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! data-sort-type="number" |[[Semiconductor device fabrication|Pro-<br>cess]]

! [[MOSFET|MOS-<br>FET]]

! data-sort-type="number" | Area<br>(mm²²)

! {{Abbr|Ref|Reference(s)}}

|-

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|<ref name="oki-rdram"/>

|-

|{{sort|1998|Mar&#8239nbsp;1998}}

|Direct RDRAM

|72 Mbit

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|<ref>{{cite web |title=Direct RDRAM |url=https://retrocdn.net/images/6/68/Direct_RDRAM_datasheet.pdf |archive-url=https://web.archive.org/web/20190621151523/https://retrocdn.net/images/6/68/Direct_RDRAM_datasheet.pdf |archive-date=2019-06-21 |url-status=live |publisher=[[Rambus]] |date=12 March 1998 |access-date=21 June 2019}}</ref>

|-

|{{sort|1998|Jun&#8239nbsp;1998}}

|style="color:#AAAAAA"| ''?''

|64 Mbit

Line 637 ⟶ 639:

|style="color:#AAAAAA"| ''?''

|-

|{{sort|2008|Apr&#8239nbsp;2008}}

|style="color:#AAAAAA"| ''?''

|8192 Mbit

Line 738 ⟶ 740:

|}

=== SGRAM and HBM ===

{| class="wikitable sortable" style="text-align:center"

|+ [[Synchronous graphics random-access memory]] (SGRAM) and [[High Bandwidth Memory]] (HBM)

|-

! Date of introduction

Line 882 ⟶ 884:

|4096 Mbit

|SGRAM (GDDR3)

|rowspan="2" | [[SK Hynix]]

|rowspan="2" | {{?}}

|rowspan="2" | CMOS

|rowspan="2" | {{?}}

|rowspan="2" | <ref name="hynix2010s"/>

|-

|2013

|{{?}}

|{{?}}

|[[High Bandwidth Memory|HBM]]

|-

|{{sort|2016|March 2016}}

Line 901 ⟶ 898:

|CMOS

|140&nbsp;mm²

|<ref>{{cite news |last1=Shilov |first1=Anton |title=Micron Begins to Sample GDDR5X Memory, Unveils Specs of Chips |url=https://www.anandtech.com/show/10193/micron-begins-to-sample-gddr5x-memory |archive-url=https://web.archive.org/web/20160330094652/http://www.anandtech.com/show/10193/micron-begins-to-sample-gddr5x-memory |url-status=dead |archive-date=March 30, 2016 |access-date=16 July 2019 |work=[[AnandTech]] |date=March 29, 2016}}</ref>

|-

|{{sort|2018|January 2018}}

|K4ZAF325BM

|16 Gbit

|SGRAM ([[GDDR6]])

|Samsung

|[[10 nm process|10 nm]]

|[[FinFET]]

|225&nbsp;mm²

|<ref>{{cite news |title=Samsung Electronics Starts Producing Industry's First 16-Gigabit GDDR6 for Advanced Graphics Systems |url=https://news.samsung.com/global/samsung-electronics-starts-producing-industrys-first-16-gigabit-gddr6-for-advanced-graphics-systems |access-date=15 July 2019 |publisher=[[Samsung]] |date=January 18, 2018}}</ref><ref name='tr_gddr6'>{{cite news|last1=Killian|first1=Zak|title=Samsung fires up its foundries for mass production of GDDR6 memory|url=https://techreport.com/news/33129/samsung-fires-up-its-foundries-for-mass-production-of-gddr6-memory|access-date=18 January 2018|publisher=Tech Report|date=18 January 2018}}</ref><ref>{{cite news |title=Samsung Begins Producing The Fastest GDDR6 Memory In The World |url=https://wccftech.com/samsung-gddr6-16gb-18gbps-mass-production-official/ |access-date=16 July 2019 |work=Wccftech |date=18 January 2018}}</ref>

|} <section end="SDRAM timeline"/>

=== HBM ===

{| class="wikitable sortable" style="text-align:center"

|+ [[High Bandwidth Memory]] (HBM)

|-

! Date of introduction

! Chip name

! Capacity ([[bit]]s){{binpre}}

! SDRAM type

! Manufacturer(s)

! data-sort-type="number" |[[Semiconductor device fabrication|Process]]

! [[MOSFET]]

! data-sort-type="number" | Area

! {{Abbr|Ref|Reference(s)}}

|-

|2013

|{{?}}

|{{?}}

|[[High Bandwidth Memory|HBM]]

|[[SK Hynix]]

|{{?}}

|CMOS

|{{?}}

|<ref name="hynix2010s" />

|-

|{{sort|2016|June 2016}}

Line 908 ⟶ 940:

|[[HBM2]]

|Samsung

|[[20&nbsp; nm]]

|CMOS

|{{?}}

|<ref name="Shilov2017">{{cite news |last1=Shilov |first1=Anton |date=July 19, 2017 |title=Samsung Increases Production Volumes of 8 GB HBM2 Chips Due to Growing Demand |url=https://www.anandtech.com/show/11643/samsung-increases-8gb-hbm2-production-volume |archive-url=https://web.archive.org/web/20170720000946/http://anandtech.com/show/11643/samsung-increases-8gb-hbm2-production-volume |url-status=dead |archive-date=July 20, 2017 |access-date=29 June 2019 |work=[[AnandTech]] |date=July 19, 2017}}</ref><ref>{{cite web |title=HBM |url=https://samsungsemiconductor-us.com/hbm/ |access-date=16 July 2019 |website=[[Samsung Semiconductor]] |publisher=[[Samsung]] |access-date=16 July 2019}}</ref>

|-

|2017

Line 921 ⟶ 953:

|CMOS

|{{?}}

|<ref name="Shilov2017" />

|-}

|{{sort|2018|January 2018}}

|K4ZAF325BM

|16 Gbit

|SGRAM ([[GDDR6]])

|Samsung

|[[10 nm process|10 nm]]

|[[FinFET]]

|225&nbsp;mm²

|<ref>{{cite news |title=Samsung Electronics Starts Producing Industry's First 16-Gigabit GDDR6 for Advanced Graphics Systems |url=https://news.samsung.com/global/samsung-electronics-starts-producing-industrys-first-16-gigabit-gddr6-for-advanced-graphics-systems |access-date=15 July 2019 |publisher=[[Samsung]] |date=January 18, 2018}}</ref><ref name='tr_gddr6'>{{cite news|last1=Killian|first1=Zak|title=Samsung fires up its foundries for mass production of GDDR6 memory|url=https://techreport.com/news/33129/samsung-fires-up-its-foundries-for-mass-production-of-gddr6-memory|access-date=18 January 2018|publisher=Tech Report|date=18 January 2018}}</ref><ref>{{cite news |title=Samsung Begins Producing The Fastest GDDR6 Memory In The World |url=https://wccftech.com/samsung-gddr6-16gb-18gbps-mass-production-official/ |access-date=16 July 2019 |work=Wccftech |date=18 January 2018}}</ref>

|} <section end="SDRAM timeline"/>

== See also ==

* [[GDDR]] (graphics DDR) and its subtypes [[GDDR2]], [[GDDR3]], [[GDDR4]], [[GDDR5]], [[GDDR6]] and [[GDDR7]]

* [[List of device bandwidths]]

* [[Serial presence detect]] -– EEPROM with timing data on SDRAM modules

* [http://taututorial.yolasite.com/ SDRAM Tutorial] -– Flash website built by Tel-Aviv University students

* A concise but thorough review of SDRAM architecture/terminology and command timing dependencies in [http://drum.lib.umd.edu/bitstream/1903/11269/1/Gross_umd_0117N_11844.pdf High-Performance DRAM System Design Constraints and Considerations], a master thesis from the University of Maryland.

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== External links ==

* [https://web.archive.org/web/20121016082506/http://www.anandtech.com/show/3851/ Everything you always wanted to know about SDRAM (memory), but were afraid to ask], August 2010, [[AnandTech]]

* [http://www.hardwaresecrets.com/understanding-ram-timings/ Understanding RAM Timings], May 2011, Hardware Secrets

* [https://web.archive.org/web/20030803094457/http://developer.intel.com/technology/memory/pc133sdram/spec/sdram133.pdf PC SDRAM Specification, Rev 1.7]