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[[Image:SDR SDRAM-1.jpg|thumb|Eight [[Hyundai Electronics|Hyundai]] SDRAM ICs on a PC100 [[DIMM]] package]]
The earliest DRAMs were often synchronized with the CPU clock (clocked) and were used with early microprocessors. In the mid-1970s, DRAMs moved to the asynchronous design, but in the 1990s returned to synchronous operation.<ref>{{cite book | author=P. Darche | title=Microprocessor: Prolegomenes
SDRAM latency is not inherently lower (faster access times) than asynchronous DRAM. Indeed, early SDRAM was somewhat slower than contemporaneous [[burst EDO DRAM]] due to the additional logic. The benefits of SDRAM's internal buffering come from its ability to interleave operations to multiple banks of memory, thereby increasing effective [[Bandwidth (computing)|bandwidth]].
[[Double data rate]] SDRAM, known as [[DDR SDRAM]], was first demonstrated by Samsung in 1997.<ref name="techpowerup">{{cite web |title=Samsung 30 nm Green PC3-12800 Low Profile 1.35 V DDR3 Review |url=https://www.techpowerup.com/review/samsung-mv-3v4g3/ |website=TechPowerUp |access-date=25 June 2019 |date= March 8, 2012}}</ref> Samsung released the first commercial DDR SDRAM chip (64{{nbsp}}Mbit{{binpre}}) in June 1998,<ref name="samsung99"/><ref name="samsung98"/><ref name="phys"/> followed soon after by [[Hyundai Electronics]] (now [[SK Hynix]]) the same year.<ref name="hynix90s"/>
Today, virtually all SDRAM is manufactured in compliance with standards established by [[JEDEC]], an electronics industry association that adopts [[open standards]] to facilitate interoperability of electronic components. JEDEC formally adopted its first SDRAM standard in 1993 and subsequently adopted other SDRAM standards, including those for [[DDR SDRAM|DDR]], [[DDR2 SDRAM|DDR2]] and [[DDR3 SDRAM]].
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In operation, CAS latency is a specific number of clock cycles programmed into the SDRAM's mode register and expected by the DRAM controller. Any value may be programmed, but the SDRAM will not operate correctly if it is too low. At higher clock rates, the useful CAS latency in clock cycles naturally increases. 10–15 ns is 2–3 cycles (CL2–3) of the 200 MHz clock of DDR-400 SDRAM, CL4-6 for DDR2-800, and CL8-12 for DDR3-1600. Slower clock cycles will naturally allow lower numbers of CAS latency cycles.
SDRAM modules have their own timing specifications, which may be slower than those of the chips on the module. When 100 MHz SDRAM chips first appeared, some manufacturers sold "100 MHz" modules that could not reliably operate at that clock rate. In response, Intel published the PC100 standard, which outlines requirements and guidelines for producing a memory module that can operate reliably at 100 MHz. This standard was widely influential, and the term "PC100" quickly became a common identifier for 100 MHz SDRAM modules, and modules are now commonly designated with "PC"-prefixed numbers (PC66, PC100 or PC133
== Control signals ==
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* M8, M7: Operating mode. Reserved, and must be 00.
* M6, M5, M4: CAS latency. Generally only 010 (CL2) and 011 (CL3) are legal. Specifies the number of cycles between a read command and data output from the chip. The chip has a fundamental limit on this value in nanoseconds; during initialization, the memory controller must use its knowledge of the clock frequency to translate that limit into cycles.
* M3: Burst type. 0
* M2, M1, M0: Burst length. Values of 000, 001, 010 and 011 specify a burst size of 1, 2, 4 or 8 words, respectively. Each read (and write, if M9 is 0) will perform that many accesses, unless interrupted by a burst stop or other command. A value of 111 specifies a full-row burst. The burst will continue until interrupted. Full-row bursts are only permitted with the sequential burst type.
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Again, with every doubling, the downside is the increased [[Latency (engineering)|latency]]. As with all DDR SDRAM generations, commands are still restricted to one clock edge and command latencies are given in terms of clock cycles, which are half the speed of the usually quoted transfer rate (a [[CAS latency]] of 8 with DDR3-800 is 8/(400 MHz) = 20 ns, exactly the same latency of CAS2 on PC100 SDR SDRAM).
DDR3 memory chips are being made commercially,<ref>{{cite web|url=http://www.simmtester.com/page/news/showpubnews.asp?num=145|title=What is DDR memory?}}</ref> and computer systems using them were available from the second half of 2007,<ref>{{cite news|url=http://www.tomshardware.com/2007/06/05/pipe_dreams_six_p35-ddr3_motherboards_compared/|title=Pipe Dreams: Six P35-DDR3 Motherboards Compared |date=June 5, 2007 |author=Thomas Soderstrom |newspaper=Tom's Hardware}}</ref> with significant usage from 2008 onwards.<ref>{{cite web|url=http://news.softpedia.com/news/AMD-to-Adopt-DDR3-in-Three-Years-13486.shtml|title=AMD to Adopt DDR3 in Three Years|date=28 November 2005}}</ref> Initial clock rates were 400 and 533 MHz, which are described as DDR3-800 and DDR3-1066 (PC3-6400 and PC3-8500 modules), but 667 and 800 MHz, described as DDR3-1333 and DDR3-1600 (PC3-10600 and PC3-12800 modules) are now common.<ref>{{cite web|url=http://www.anandtech.com/printarticle.aspx?i=3045|archive-url=https://archive.today/20120719141605/http://www.anandtech.com/printarticle.aspx?i=3045|url-status=dead|archive-date=July 19, 2012|title=Super Talent & TEAM: DDR3-1600 Is Here! |date=July 20, 2007 |author=Wesly Fink |publisher=Anandtech}}</ref> Performance up to DDR3-2800 (PC3 22400 modules) are available.<ref>{{cite web |url=http://hothardware.com/News/GSKILL-Announces-DDR3-Memory-Kit-For-Ivy-Bridge/ |title=G.SKILL Announces DDR3 Memory Kit For Ivy Bridge |date=24 April 2012 |author=Jennifer Johnson}}</ref>
=== DDR4 ===
{{Main|DDR4 SDRAM}}
DDR4 SDRAM is the successor to [[DDR3 SDRAM]]. It was revealed at the [[Intel Developer Forum]] in San Francisco in 2008, and was due to be released to market during 2011. The timing varied considerably during its development
The DDR4 chips run at 1.2 [[Volt|V]] or less,<ref>{{cite web|url=http://www.pcpro.co.uk/news/220257/idf-ddr3-wont-catch-up-with-ddr2-during-2009.html|title=IDF: "DDR3 won't catch up with DDR2 during 2009"|work=Alphr}}</ref><ref>{{cite web|url=http://www.heise-online.co.uk/news/IDF-DDR4-the-successor-to-DDR3-memory--/111367|title=heise online
DDR4 did ''not'' double the internal prefetch width again, but uses the same 8''n'' prefetch as DDR3.<ref name="jedec_ddr3_ddr4">{{cite press release |url=http://www.jedec.org/news/pressreleases/jedec-announces-key-attributes-upcoming-ddr4-standard |title=JEDEC Announces Key Attributes of Upcoming DDR4 Standard |publisher=[[JEDEC]] |date=2011-08-22 |access-date=2011-01-06}}</ref> Thus, it will be necessary to interleave reads from several banks to keep the data bus busy.
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{{Main|DDR5 SDRAM}}
In March 2017, JEDEC announced a DDR5 standard is under development,<ref>{{cite press release |title=JEDEC DDR5 & NVDIMM-P Standards Under Development |url=https://www.jedec.org/news/pressreleases/jedec-ddr5-nvdimm-p-standards-under-development |date=30 March 2017 |publisher=[[JEDEC]]}}</ref> but provided no details except for the goals of doubling the bandwidth of DDR4, reducing power consumption, and publishing the standard in 2018. The standard was released on 14 July 2020.<ref name="anandtech-ddr5">{{cite web|url=https://www.anandtech.com/show/15912/ddr5-specification-released-setting-the-stage-for-ddr56400-and-beyond|archive-url=https://web.archive.org/web/20200714225042/https://www.anandtech.com/show/15912/ddr5-specification-released-setting-the-stage-for-ddr56400-and-beyond|url-status=dead|archive-date=July 14, 2020|title=DDR5 Memory Specification Released: Setting the Stage for DDR5-6400 And Beyond|last=Smith|first=Ryan|date=2020-07-14|website=AnandTech|access-date=2020-07-15}}</ref>
== Failed successors ==
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|CMOS
|140 mm<sup>2</sup>
|<ref>{{cite news |last1=Shilov |first1=Anton |title=Micron Begins to Sample GDDR5X Memory, Unveils Specs of Chips |url=https://www.anandtech.com/show/10193/micron-begins-to-sample-gddr5x-memory |archive-url=https://web.archive.org/web/20160330094652/http://www.anandtech.com/show/10193/micron-begins-to-sample-gddr5x-memory |url-status=dead |archive-date=March 30, 2016 |access-date=16 July 2019 |work=[[AnandTech]] |date=March 29, 2016}}</ref>
|-
|{{sort|2018|January 2018}}
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|CMOS
|{{?}}
|<ref name="Shilov2017">{{cite news |last1=Shilov |first1=Anton |date=July 19, 2017 |title=Samsung Increases Production Volumes of 8 GB HBM2 Chips Due to Growing Demand |url=https://www.anandtech.com/show/11643/samsung-increases-8gb-hbm2-production-volume |archive-url=https://web.archive.org/web/20170720000946/http://anandtech.com/show/11643/samsung-increases-8gb-hbm2-production-volume |url-status=dead |archive-date=July 20, 2017 |access-date=29 June 2019 |work=[[AnandTech]]}}</ref><ref>{{cite web |title=HBM |url=https://samsungsemiconductor-us.com/hbm/ |access-date=16 July 2019 |website=[[Samsung Semiconductor]] |publisher=[[Samsung]]}}</ref>
|-
|2017
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* [[GDDR]] (graphics DDR) and its subtypes [[GDDR2]], [[GDDR3]], [[GDDR4]], [[GDDR5]], [[GDDR6]] and [[GDDR7]]
* [[List of device bandwidths]]
* [[Serial presence detect]]
* [http://taututorial.yolasite.com/ SDRAM Tutorial]
* A concise but thorough review of SDRAM architecture/terminology and command timing dependencies in [http://drum.lib.umd.edu/bitstream/1903/11269/1/Gross_umd_0117N_11844.pdf High-Performance DRAM System Design Constraints and Considerations], a master thesis from the University of Maryland.
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== External links ==
* [https://web.archive.org/web/20121016082506/http://www.anandtech.com/show/3851
* [http://www.hardwaresecrets.com/understanding-ram-timings/ Understanding RAM Timings], May 2011, Hardware Secrets
* [https://web.archive.org/web/20030803094457/http://developer.intel.com/technology/memory/pc133sdram/spec/sdram133.pdf PC SDRAM Specification, Rev 1.7]
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