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{{Short description|Equal sharing of all resources by multiple identical processors}}
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[[File:SMP - Symmetric Multiprocessor System.svg|thumb|upright=2|Diagram of a symmetric multiprocessing system]]
'''Symmetric multiprocessing''' or '''shared-memory multiprocessing'''<ref>{{cite book |last1=Patterson |first1=David |last2=Hennessy |first2=John |author-link1=David Patterson (computer scientist) |author-link2=John L. Hennessy |date=2018 |title=Computer Organisation and Design: The Hardware/Software Interface |___location=Cambridge, United States |publisher=Morgan Kaufmann |page=509 |isbn=978-0-12-812275-4|edition=RISC-V }}</ref> ('''SMP''') involves a [[multiprocessor]] computer hardware and software architecture where two or more identical processors are connected to a single, shared [[main memory]], have full access to all input and output devices, and are controlled by a single operating system instance that treats all processors equally, reserving none for special purposes. Most multiprocessor systems today use an SMP architecture. In the case of [[multi-core processor]]s, the SMP architecture applies to the cores, treating them as separate processors.
Professor John D. Kubiatowicz considers traditionally SMP systems to contain processors without caches.<ref>{{cite conference|url=https://parlab.eecs.berkeley.edu/2013bootcampagenda|conference=2013 Short Course on Parallel Programming|author=John Kubiatowicz|title=Introduction to Parallel Architectures and Pthreads}}</ref> Culler and Pal-Singh in their 1998 book "Parallel Computer Architecture: A Hardware/Software Approach" mention: "The term SMP is widely used but causes a bit of confusion. [...] The more precise description of what is intended by SMP is a shared memory multiprocessor where the cost of accessing a memory ___location is the same for all processors; that is, it has uniform access costs when the access actually is to memory. If the ___location is cached, the access will be faster, but cache access times and memory access times are the same on all processors."<ref>{{cite book|isbn=978-
SMP systems are ''[[multiprocessing#Processor coupling|tightly coupled multiprocessor]] systems'' with a pool of homogeneous processors running independently of each other. Each processor, executing different programs and working on different sets of data, has the capability of sharing common resources (memory, I/O device, interrupt system and so on) that are connected using a [[system bus]] or a [[crossbar switch|crossbar]].
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Processors may be interconnected using buses, [[crossbar switch]]es or on-chip mesh networks. The bottleneck in the scalability of SMP using buses or crossbar switches is the bandwidth and power consumption of the interconnect among the various processors, the memory, and the disk arrays. Mesh architectures avoid these bottlenecks, and provide nearly linear scalability to much higher processor counts at the sacrifice of programmability:
<blockquote>Serious programming challenges remain with this kind of architecture because it requires two distinct modes of programming
SMP systems allow any processor to work on any task no matter where the data for that task is located in memory, provided that each task in the system is not in execution on two or more processors at the same time. With proper [[operating system]] support, SMP systems can easily move tasks between processors to balance the workload efficiently.
==History==
The earliest production system with multiple identical processors was the Burroughs [[B5000]], which was functional around 1961. However at run-time this was [[Asymmetric multiprocessing#Burroughs B5000 and B5500|asymmetric]], with one processor restricted to application programs while the other processor mainly handled the operating system and hardware interrupts. The Burroughs D825 first implemented SMP in 1962.<ref>{{cite web|url=http://ei.cs.vt.edu/~history/Parallel.html|title=The History of the Development of Parallel Computing|author=Gregory V. Wilson|date=October 1994}}</ref><ref>{{cite web|url=http://ed-thelen.org/comp-hist/BRL64-b.html#BURROUGHS-D825|title=A Fourth Survey of Domestic Electronic Digital Computing Systems|author=Martin H. Weik|publisher=[[Ballistic Research Laboratories]], [[Aberdeen Proving Grounds]]|at=Burroughs D825|date=January 1964}}</ref>
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| version = Fourth Edition
| date = September 1968
| url = http://www.bitsavers.org/pdf/ibm/360/
| publisher = IBM
| title = IBM System/360 Model 67 Functional Characteristics
| id = GA27-2719-2
| url = http://www.bitsavers.org/pdf/ibm/360/
| version = Third Edition
| date = February 1972}}</ref> The operating systems that ran on these machines were [[OS/360]] M65MP<ref>[http://doi.acm.org/10.1145/800186.810634 M65MP: An Experiment in OS/360 multiprocessing]</ref> and [[TSS/360]]. Other software developed at universities, notably the [[Michigan Terminal System]] (MTS), used both CPUs. Both processors could access data channels and initiate I/O. In OS/360 M65MP, peripherals could generally be attached to either processor since the operating system kernel ran on both processors (though with a "big lock" around the I/O handler).<ref>{{cite book |url=http://bitsavers.org/pdf/ibm/360/os/R21.7_Apr73/plm/GY28-6616-9_OS_IO_Superv_PLM_R21.7_Apr73.pdf |title=Program Logic Manual, OS I/O Supervisor Logic, Release 21 (R21.7) |publisher=IBM |id=GY28-6616-9 |edition=Tenth |date=April 1973}}</ref> The MTS supervisor (UMMPS) has the ability to run on both CPUs of the IBM System/360 model
Other mainframes that supported SMP included the [[UNIVAC 1100/2200 series#1108|UNIVAC 1108 II]], released in 1965, which supported up to three CPUs, and the [[GE-600 series|GE-635 and GE-645]],<ref>{{cite book|url=http://www.bitsavers.org/pdf/ge/GE-6xx/CPB-371A_GE-635_System_Man_Jul64.pdf|title=GE-635 System Manual|date=July 1964|publisher=[[General Electric]]}}</ref><ref>{{cite book|url=http://www.bitsavers.org/pdf/ge/GE-645/GE-645_SystemMan_Jan68.pdf|title=GE-645 System Manual|date=January 1968|publisher=General Electric}}</ref> although [[General Comprehensive Operating System|GECOS]] on multiprocessor GE-635 systems ran in a master-slave asymmetric fashion, unlike [[Multics]] on multiprocessor GE-645 systems, which ran in a symmetric fashion.<ref>{{cite newsgroup|url=https://groups.google.com/d/msg/alt.folklore.computers/v-hkdKaPTXc/MX7UI3DgOokJ|title=Fear of Multiprocessing?|author=Richard Shetron|date=May 5, 1998|newsgroup=alt.folklore.computers|message-id=354e95a9.0@news.wizvax.net}}</ref>
Starting with its version 7.0 (1972), [[Digital Equipment Corporation]]'s operating system [[TOPS-10]] implemented the SMP feature, the earliest system running SMP was the [[PDP-10|DECSystem 1077]] dual KI10 processor system.<ref>[http://www.ultimate.com/phil/pdp10/10periphs DEC 1077 and SMP]</ref> Later KL10 system could aggregate up to 8 CPUs in a SMP manner. In contrast, DECs first multi-processor [[VAX]] system, the VAX-11/782, was asymmetric,<ref>[http://www.bitsavers.org/pdf/dec/vax/EG-21731-18_VAX_Product_Sales_Guide_Apr82.pdf VAX Product Sales Guide, pages 1-23 and 1-24]: the VAX-11/782 is described as an asymmetric multiprocessing system in 1982</ref> but later VAX multiprocessor systems were SMP.<ref>[http://www.bitsavers.org/pdf/dec/vax/8800/EK-8840H-UG-001_88xx_System_Hardware_Users_Guide_Mar88.pdf VAX 8820/8830/8840 System Hardware User's Guide]: by 1988 the VAX operating system was SMP</ref>
Early commercial Unix SMP implementations included the [[Sequent Computer Systems]] Balance 8000 (released in 1984) and Balance 21000 (released in 1986).<ref>{{Cite book |last1 = Hockney |first1 = R.W. |last2 = Jesshope |first2 = C.R. |title = Parallel Computers 2: Architecture, Programming and Algorithms |publisher = Taylor & Francis |year = 1988 |
Earlier non-commercial multiprocessing UNIX ports existed, including a port named MUNIX created at the [[Naval Postgraduate School]] by 1975.<ref>{{Cite web|url=https://core.ac.uk/download/pdf/36714194.pdf|title=MUNIX, A Multiprocessing Version Of UNIX|last=Hawley|first=John Alfred|date=June 1975|website=core.ac.uk|access-date=11 November 2018}}</ref>
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Multithreaded programs can also be used in time-sharing and server systems that support multithreading, allowing them to make more use of multiple processors.
== Advantages/
In current SMP systems, all of the processors are tightly coupled inside the same box with a bus or switch; on earlier SMP systems, a single CPU took an entire cabinet. Some of the components that are shared are global memory, disks, and I/O devices. Only one copy of an OS runs on all the processors, and the OS must be designed to take advantage of this architecture. Some of the basic advantages involves cost-effective ways to increase throughput. To solve different problems and tasks, SMP applies multiple processors to that one problem, known as [[parallel programming]].
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== Performance ==
When more than one program executes at the same time, an SMP system has considerably better performance than a
▲When more than one program executes at the same time, an SMP system has considerably better performance than a uni-processor, because different programs can run on different CPUs simultaneously. Similarly, [[Asymmetric multiprocessing]] (AMP) usually allows only one processor to run a program or task at a time. For example, AMP can be used in assigning specific tasks to CPU based to priority and importance of task completion. AMP was created well before SMP in terms of handling multiple CPUs, which explains the lack of performance based on the example provided.
In cases where an SMP environment processes many jobs, administrators often experience a loss of hardware efficiency. Software programs have been developed to schedule jobs and other functions of the computer so that the processor utilization reaches its maximum potential. Good software packages can achieve this maximum potential by scheduling each CPU separately, as well as being able to integrate multiple SMP machines and clusters.
Access to RAM is serialized; this and [[cache coherency]] issues
== Alternatives ==
[[Image:Shared memory.svg|right|350px|thumb|Diagram of a typical SMP system. Three processors are connected to the same memory module through a [[system bus]] or [[crossbar switch]]. ]]
SMP uses a single shared [[system bus]] that represents one of the earliest styles of multiprocessor machine architectures, typically used for building smaller computers with up to 8 processors.
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== Variable SMP ==
Variable Symmetric Multiprocessing (vSMP) is a specific mobile use case technology initiated by NVIDIA. This technology includes an extra fifth core in a quad-core device, called the Companion core, built specifically for executing tasks at a lower frequency during mobile active standby mode, video playback, and music playback.
Project Kal-El ([[Tegra 3]]),<ref name="AutoMQ-4" /> patented by NVIDIA, was the first SoC (System on Chip) to implement this new vSMP technology. This technology
== See also ==
* [[Asymmetric multiprocessing]]
* [[Binary Modular Dataflow Machine]]
* [[Cellular multiprocessing]]
* [[Locale (computer hardware)]]
* [[Massively parallel]]
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== References ==
{{Reflist|refs=
<ref name="AutoMQ-1">{{cite journal |title= Trends in Multi-core DSP Platforms |
<ref name="AutoMQ-4">[http://www.nvidia.com/content/pdf/tegra_white_papers/tegra-whitepaper-0911b.pdf Variable SMP – A Multi-Core CPU Architecture for Low Power and High Performance. NVIDIA. 2011.]</ref>
}}
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== External links ==
* [http://ei.cs.vt.edu/~history/Parallel.html History of Multi-Processing]
* [https://web.archive.org/web/20120120160334/http://www.ibm.com/developerworks/library/l-linux-smp/ Linux and Multiprocessing]
* [https://www.amd.com/us-en/Processors/ProductInformation/0,,30_118,00.html AMD]
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