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=== Bits ===
[[Computer architecture]]s are often described as ''n''-[[bit]] architectures. In the first {{frac|3|4}} of the 20th century, ''n'' is often [[12-bit computing|12]], [[18-bit computing|18]], [[24-bit computing|24]], 30, [[36-bit computing|36]], [[48-bit computing|48]] or [[60-bit computing|60]]. In the last {{frac|1|3}} of the 20th century, ''n'' is often 8, 16, or 32, and in the 21st century, ''n'' is often 16, 32 or 64, but other sizes have been used (including 6, [[Elliott 803|39]], [[128-bit computing|128]]). This is actually a simplification as computer architecture often has a few more or less "natural" data sizes in the [[instruction set]], but the hardware implementation of these may be very different. Many instruction set architectures have instructions that, on some implementations of that instruction set architecture, operate on half and/or twice the size of the processor's major internal datapaths. Examples of this are the [[Z80]], [[MC68000]], and the [[IBM System/360]]. On these types of implementations, a twice as wide operation typically also takes around twice as many clock cycles (which is not the case on high performance implementations). On the 68000, for instance, this means 8 instead of 4 clock ticks, and this particular chip may be described as a [[32-bit computing|32-bit]] architecture with a [[16-bit computing|16-bit]] implementation. The IBM System/360 instruction set architecture is 32-bit, but several models of the System/360 series, such as the [[IBM System/360 Model 30]], have smaller internal data paths, while others, such as the [[360/195]], have larger internal data paths. The external databus width is not used to determine the width of the architecture; the [[NS320xx|NS32008, NS32016 and NS32032]] were basically the same 32-bit chip with different external data buses. IBM's [[PowerPC_600#PowerPC_604|PowerPC 604]] has a 64-bit bus but only 32-bit registers. Early 32-bit microprocessors often had a 24-bit address, as did the System/360 processors. Initial versions of [[SuperH]] had a fixed-length 16-bit instructions in spite of having a 32-bit architecture, while later versions were 32-bit.
=== Digits ===
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;autoincrement/autodecrement
:A register used for indexing, or a pointer word used by indirect addressing, is incremented or decremented by 1, an operand size or an explicit delta
Vector processors have offered [[Vector_processor#Vector_processor_features|additional modes]] unique to element-based operations.
==== Number of operands ====
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! {{verth|[[Endianness]]}}
! Extensions
! [[Open-source hardware|Open]]
! Royalty<br />free
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| [[ARM architecture#64/32-bit architecture|Arm64/A64]]
| 64
| v8.9-A/v9.4-A,<br/><ref>{{Cite web |title=Arm A-Profile Architecture Developments 2022 - Architectures and Processors blog - Arm Community blogs - Arm Community |url=https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-2022 |access-date=2022-12-09 |website=community.arm.com |date=29 September 2022 |language=en}}</ref> Armv8-R<br/><ref>{{cite news |last=Frumusanu |first=Andrei |date=September 3, 2020 |url=https://www.anandtech.com/show/16056/arm-announces-cortexr82-first-64bit-real-time-processor |archive-url=https://web.archive.org/web/20200903134024/https://www.anandtech.com/show/16056/arm-announces-cortexr82-first-64bit-real-time-processor |url-status=dead |archive-date=September 3, 2020 |title=ARM Announced Cortex-R82: First 64-bit Real Time Processor |website=[[AnandTech]]}}</ref>
| 2011<br/><ref>{{cite web |url= https://www.computerworld.com/article/1536136/arm-goes-64-bit-with-new-armv8-chip-architecture.html |title= ARM goes 64-bit with new ARMv8 chip architecture |website=[[Computerworld]] |date= 27 October 2011 |access-date= 8 May 2024}}</ref>
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| Bi
| [[AltiVec]], APU, [[AltiVec#VSX|VSX]], [[Cell (microprocessor)|Cell]], Floating-point, Matrix Multiply Assist
| Licensed by [[OpenPOWER_Foundation|OPF]] <!-- Commercial use requires Licensing. exemptions for GPGAs. see EULA-->
| Only if Licensed<ref>[https://openpowerfoundation.org/final-draft-of-the-power-isa-eula-released/ Final draft of Power ISA EULA]</ref>
|-
| [[RISC-V]]
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