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{{short description|Technique used to increase the number of structures a microchip may contain}}
{{jargon|date=December 2022}}
'''Multiple patterning''' (or '''multi-patterning''') is a class of technologies for manufacturing [[integrated
[[File:Different_multipatterning_techniques.png|thumb|right|300px|'''Different techniques for multiple patterning'''<br>''Top:'' Splitting of features into groups (3 shown here), each patterned by a different mask<br>''Center:'' Use of a spacer to generate additional separate features in the gaps<br>''Bottom:'' Use of an opposite polarity feature to cut (small break) pre-existing features]]▼
▲[[File:Different_multipatterning_techniques.png|thumb|right|300px|'''Different techniques for multiple patterning'''<br/>''Top:'' Splitting of features into groups (3 shown here), each patterned by a different mask<br/>''Center:'' Use of a spacer to generate additional separate features in the gaps<br/>''Bottom:'' Use of an opposite polarity feature to cut (small break) pre-existing features]]
Even with single exposure having sufficient resolution, extra masks have been implemented for better patterning quality such as by [[Intel]] for line-cutting at its 45nm node<ref>[http://download.intel.com/pressroom/kits/advancedtech/pdfs/VLSI_45nm_HiKMG-presentation.pdf Intel 45nm HKMG]</ref> or [[TSMC]] at its 28nm node.<ref>[https://support1.cadence.com/public/docs/content/11673890.html TSMC 28nm cutpoly]</ref> Even for [[electron-beam lithography]], single exposure appears insufficient at ~10 nm half-pitch, hence requiring double patterning.<ref>{{cite journal|last1=Chao|first1=Weilun|last2=Kim|first2=Jihoon|last3=Anderson|first3=Erik H.|last4=Fischer|first4=Peter|last5=Rekawa|first5=Senajith|last6=Attwood|first6=David T.|title=Double patterning HSQ processes of zone plates for 10 nm diffraction limited performance|date=2009-01-09|url=http://www.osti.gov/scitech/servlets/purl/959418-4ItigR/}}</ref><ref>{{cite journal|last1=Duan|first1=Huigao|last2=Winston|first2=Donald|last3=Yang|first3=Joel K. W.|last4=Cord|first4=Bryan M.|last5=Manfrinato|first5=Vitor R.|last6=Berggren|first6=Karl K.|title=Sub-10-nm half-pitch electron-beam lithography by using poly(methyl methacrylate) as a negative resist|journal=Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena|date=November 2010|volume=28|issue=6|pages=C6C58–C6C62|doi=10.1116/1.3501353|bibcode=2010JVSTB..28C..58D |url=http://www.rle.mit.edu/qnn/documents/duan-5-2010-80.pdf|archive-url=https://web.archive.org/web/20120119131529/http://www.rle.mit.edu/qnn/documents/duan-5-2010-80.pdf|archive-date=2012-01-19|hdl=1721.1/73447|hdl-access=free}}</ref>▼
▲Even with single exposure having sufficient resolution, extra masks have been implemented for better patterning quality such as by [[Intel]] for line-cutting at its 45nm node<ref>[http://download.intel.com/pressroom/kits/advancedtech/pdfs/VLSI_45nm_HiKMG-presentation.pdf Intel 45nm HKMG]</ref> or [[TSMC]] at its 28nm node.<ref>[https://support1.cadence.com/public/docs/content/11673890.html TSMC 28nm cutpoly]</ref> Even for [[electron-beam lithography]], single exposure appears insufficient at ~10 nm half-pitch, hence requiring double patterning.<ref>{{cite
Double patterning lithography was first demonstrated in 1983 by D. C. Flanders and N. N. Efremow.<ref>{{cite journal |author1=D. C. Flanders |author2=N. N. Efremow | title=Generation of <50 nm period gratings using edge defined techniques | year=1983 | pages=1105–1108 | publisher=J. Vac. Sci. Technol. B}}</ref> Since then several double patterning techniques have been developed such as self alignment double patterning (SADP) and a litho-only approach to double patterning.<ref>{{cite journal |author1=Chris Bencher |author2=Yongmei Chen |author3=Huixiong Dai |author4=Warren Montgomery |author5=Lior Huli | title=22nm half-pitch patterning by CVD spacer self alignment double patterning (SADP) | journal=Optical Microlithography XXI | year=2008 | volume=6924 | pages=69244E | publisher=Optical Microlithography XXI; 69244E| doi=10.1117/12.772953 | bibcode=2008SPIE.6924E..4EB | s2cid=121968664 }}</ref><ref>{{cite journal |author1=A. Vanleenhove |author2=D. Van Steenwinckel | editor1-first=Donis G | editor1-last=Flagello | title=A litho-only approach to double patterning | journal=Society of Photo-Optical Instrumentation Engineers (Spie) Conference Series | series=Optical Microlithography XX | year=2007 | volume=6520 | pages=65202F | publisher=Optical Microlithography XX; 65202F| doi=10.1117/12.713914 | bibcode=2007SPIE.6520E..2FV | s2cid=119829809 }}</ref> ▼
▲Double patterning lithography was first demonstrated in 1983 by D. C. Flanders and N. N. Efremow.<ref>{{cite journal |author1=D. C. Flanders |author2=N. N. Efremow | title=Generation of <50 nm period gratings using edge defined techniques | year=1983 | pages=1105–1108 |
Pitch double-patterning was pioneered by [[Gurtej Sandhu|Gurtej Singh Sandhu]] of [[Micron Technology]] during the 2000s, leading to the development of [[32 nanometer|30-nm]] class [[NAND flash]] memory. Multi-patterning has since been widely adopted by NAND flash and [[random-access memory]] manufacturers worldwide.<ref name="ieee">{{cite web |title=IEEE Andrew S. Grove Award Recipients |url=https://www.ieee.org/about/awards/bios/grove-recipients.html |website=[[IEEE Andrew S. Grove Award]] |publisher=[[Institute of Electrical and Electronics Engineers]] |accessdate=4 July 2019}}</ref><ref>{{cite web |title=Micron Named Among Top 100 Global Innovators for Sixth Straight Year |url=https://www.micron.com/about/blog/2018/february/micron-makes-list-of-top-100-innovators |publisher=[[Micron Technology]] |accessdate=5 July 2019 |date=2018-02-15}}</ref>▼
▲Pitch double-patterning was pioneered by [[Gurtej Sandhu|Gurtej Singh Sandhu]] of [[Micron Technology]] during the 2000s, leading to the development of [[32 nanometer|30-nm]] class [[NAND flash]] memory. Multi-patterning has since been widely adopted by NAND flash and [[random-access memory]] manufacturers worldwide.<ref name="ieee">{{cite web |title=IEEE Andrew S. Grove Award Recipients |url=https://www.ieee.org/about/awards/bios/grove-recipients.html |archive-url=https://web.archive.org/web/20180909112404/https://www.ieee.org/about/awards/bios/grove-recipients.html |url-status=dead |archive-date=September 9, 2018 |website=[[IEEE Andrew S. Grove Award]] |publisher=[[Institute of Electrical and Electronics Engineers]] |accessdate=4 July 2019}}</ref><ref>{{cite web |title=Micron Named Among Top 100 Global Innovators for Sixth Straight Year |url=https://www.micron.com/about/blog/2018/february/micron-makes-list-of-top-100-innovators |publisher=[[Micron Technology]] |accessdate=5 July 2019 |date=2018-02-15}}</ref>
==Situations requiring multiple patterning==
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[[File:EUV_Stochastic_Limits.png|thumb|left|300px|'''Stochastic defects limit EUV resolution.''' Stochastic defects are more serious for tighter pitches; at 36 nm pitch defect rate does not drop below ~1e-9. Contact patterns have severe defectivity at larger dimensions.]]
The most obvious case requiring multiple patterning is when the feature pitch is below the resolution limit of the optical projection system. For a system with [[numerical aperture]] NA and wavelength λ, any pitch below 0.5 λ/NA would not be resolvable in a single wafer exposure. The resolution limit may also originate from stochastic effects, as in the case of [[Extreme_ultraviolet_lithography|EUV]].
Consequently, 20 nm linewidth still requires EUV double patterning, due to larger defectivity at larger pitches.<ref>
===Two-dimensional pattern rounding===
[[File:2D_dense_pattern_rounding.png|thumb|left|200px|'''Two-dimensional pattern rounding.''' Two-dimensional dense patterns formed from few interfering beams are always severely rounded.]]
It is well-established that dense two-dimensional patterns, which are formed from the interference of two or three beams along one direction, as in quadrupole or QUASAR illumination, are subject to significant rounding, particularly at bends and corners.<ref>
====Line tip vs. linewidth tradeoff====
The rounding of line tips naturally leads to a tradeoff between shrinking the line width (i.e., the width of the line tip) and shrinking the gap between opposite facing tips. As the line width shrinks, the tip radius shrinks. When the line tip is already less than the [[point spread function]] (k<sub>1</sub>~0.6–0.7),
the line tip naturally pulls back,<ref>C. A. Mack, Proc. SPIE 4226, 83 (2000).</ref> increasing the gap between opposite facing tips. The point spread function likewise limits the resolvable distance between the centers of the line tips (modeled as circles). This leads in turn to a tradeoff between reducing cell width and reducing cell height. The tradeoff is avoided by adding a cut/trim mask (see discussion below).<ref>
===Different parts of layout requiring different illuminations===
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[[Image:Trench doubling.svg|left|thumb| '''Double Expose, Double Etch (trenches):''' Photoresist coating over first pattern; etching adjacent to previous features; Photoresist removal]]
[[File:Pitch splitting.png|thumb|right|150px|'''Double patterning by pitch splitting.''' Double patterning by pitch splitting involves assigning adjacent features to two different masks, indicated by the different colors. It remains the simplest multiple patterning approach practiced today, and adds less cost than EUV.]]
[[File:EUV triple patterning vs DUV quadruple patterning.png|thumb|left|Some bidirectional metal layouts will force more than double patterning for either EUV or DUV if the minimum space between metal is too small.]]
[[File:Stitch Double Patterning.png|right|thumb|Sometimes, it is necessary to "stitch" two separately printed features into a single feature.]]
The earliest form of multiple patterning involved simply dividing a pattern into two or three parts, each of which may be processed conventionally, with the entire pattern combined at the end in the final layer. This is sometimes called ''pitch splitting'', since two features separated by one pitch cannot be imaged, so only skipped features can be imaged at once. It is also named more directly as "LELE" (Litho-Etch-Litho-Etch). This approach has been used for the 20 nm and 14 nm nodes. The additional cost of extra exposures was tolerated since only a few critical layers would need them. A more serious concern was the effect of feature-to-feature positioning errors (overlay). Consequently, the self-aligned sidewall imaging approach (described below) has succeeded this approach.
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This is best described by considering a process example. A first exposure of photoresist is transferred to an underlying hardmask layer. After the photoresist is removed following the hardmask pattern transfer, a second layer of photoresist is coated onto the sample and this layer undergoes a second exposure, imaging features in between the features patterned in the hardmask layer. The surface pattern is made up of photoresist features edged between mask features, which can be transferred into the final layer underneath. This allows a doubling of feature density.
For advanced nodes, both EUV and DUV may require splitting bidirectional layouts into more than two parts, resulting in triple and quadruple patterning, respectively.<ref>[https://www.youtube.com/watch?v=qiCOpeQJZPM DUV or EUV multipatterning for advanced node bidirectional metal layouts]</ref>
Sometimes, it is necessary to "stitch" two separately printed features into a single feature.<ref>S-Min Kim et al., Proc. SPIE 6520, 65200H (2007).</ref><ref>Y. Kohira et al., Proc. SPIE 9053, 90530T (2014).</ref><ref>[https://www.linkedin.com/pulse/application-specific-lithography-sense-amplifier-driver-chen-wnfuc/ Application-Specific Lithography: Sense Amplifier and Sub-Wordline Driver Metal Patterning in DRAM]</ref>▼
▲Sometimes, it is necessary to "stitch" two separately printed features into a single feature.<ref>S-Min Kim et al., Proc. SPIE 6520, 65200H (2007).</ref><ref>Y. Kohira et al., Proc. SPIE 9053, 90530T (2014).</ref><ref>[https://www.linkedin.com/pulse/application-specific-lithography-sense-amplifier-driver-chen-wnfuc/ Application-Specific Lithography: Sense Amplifier and Sub-Wordline Driver Metal Patterning in DRAM]</ref> This form of double patterning was used down to ~15nm DRAM and possibly beyond.<ref>[https://chentfred.substack.com/p/stitched-multi-patterning-for-minimum Stitched Multi-Patterning for Minimum Pitch Metal in DRAM Periphery]</ref>
A variation on this approach which eliminates the first hardmask etch is ''resist freezing'',<ref>{{cite web|title=Scaling-driven nanoelectronics - Resists|url=http://www2.imec.be:80/be_en/research/scaling-driven-nanoelectronics/lithography/resists.html|archive-url=https://web.archive.org/web/20100323021819/http://www2.imec.be/be_en/research/scaling-driven-nanoelectronics/lithography/resists.html|archive-date=2010-03-23|url-status=dead}}</ref> which allows a second resist coating over the first developed resist layer. JSR has demonstrated 32 nm lines and spaces using this method,<ref>{{cite web|last1=LaPedus|first1=Mark|title=JSR demos 'freezing material' for 22-nm production|url=http://www.eetimes.com/document.asp?doc_id=1168180|archive-url=https://web.archive.org/web/20140715005922/http://www.eetimes.com/document.asp?doc_id=1168180|archive-date=2014-07-15|date=March 13, 2008}}</ref> where the freezing is accomplished by surface hardening of the first resist layer.
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SAQP has advantages in two-dimensional 28 nm pitch routing (followed by two selective etch cut/trim steps), compared to EUV, due to the illumination limitations of the latter.<ref>[https://www.linkedin.com/pulse/application-specific-lithography-28-nm-pitch-routing-frederick-chen Application-Specific Lithography - 28 nm Pitch Two-Dimensional Routing]</ref>
==Multi-Spacer Pitch Reduction==
Iterations of deposition followed by etching or controlled etchback of multilayers can result in substantial pitch reduction beyond SAQP.<ref>[https://chentfred.substack.com/p/variable-cell-height-track-pitch Variable Cell Height Track Pitch Scaling Beyond Lithography]</ref> The number of layers determines the degree of pitch reduction.
==Directed self-assembly (DSA)==
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The line edge roughness in block copolymer patterns is strongly dependent on the interface tension between the two phases, which in turn, depends on the Flory "chi" (χ) parameter.<ref>[https://www.nist.gov/pml/div683/conference/upload/wu_2011.pdf NIST 2011 report on LER in PS-b-PMMA DSA]</ref> A higher value of χ is preferred for reduced roughness; the interfacial width between domains is equal to 2a(6χ)<sup>−1/2</sup>, where a is the statistical polymer chain length.<ref>A. N. Semenov, Macromolecules 26, 6617 (1993).</ref> Moreover, χN > 10.5 is required for sufficient phase segregation, where N is the degree of polymerization (number of monomer repeats in the chain). On the other hand, the half-pitch is equal to 2(3/π<sup>2</sup>)<sup>1/3</sup>aN<sup>2/3</sup>χ<sup>1/6</sup>. The fluctuations of the pattern widths are actually only weakly (square root) dependent on the logarithm of the half-pitch, so they become more significant relative to smaller half-pitches.
DSA has not yet been implemented in manufacturing, due to defect concerns, where a feature does not appear as expected by the guided self-assembly.<ref>A. Gharbi et al., Proc. SPIE 9777, 97770T (2016).</ref> However, there has been some progress in understanding ways to reduce defectivity for sub-10 nm half-pitch line patterns.<ref>[https://chentfred.substack.com/p/sub-10-nm-half-pitch-density-multiplication Sub-10 nm Half-Pitch Density Multiplication by Directed Self-Assembly]</ref>
At IWAPS 2024, Fudan University showed large-area, defect-free arrays using a quadruple-hole patterning technique based on DSA, which potentially significantly reduces the number of masks used in multipatterning.<ref>[https://www.linkedin.com/pulse/chinas-multipatterning-breakthrough-quadruple-hole-patterning-chen-9iskc/ China’s Multipatterning Breakthrough? Quadruple Hole Patterning by Directed Self-Assembly on a Staggered Via Grid]</ref><ref>Z. Wu et al., Proc. SPIE 13423, 134231O (2024).</ref>
==Other multi-patterning techniques==
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==EUV multiple patterning possibilities==
[[File:2D_Layout_Decomposition.png|thumb|left|200px|'''EUV layout splitting due to different illuminations.''' This layout consists of vertical and horizontal lines requiring two different illuminations optimized for each, since the horizontal layout includes wider lines and spaces. Consequently, the layout needs to be split, even for EUV lithography. Furthermore, additional cut exposures are preferred for the gaps between line tips (circled).]]
Although [[Extreme ultraviolet lithography|EUV]] has been projected to be the [[next-generation lithography]] of choice, it could still require more than one lithographic exposure, due to the foreseen need to first print a series of lines and then cut them; a single EUV exposure pattern has difficulty with line end-to-end spacing control.<ref name=setten/> In addition, the line end placement is significantly impacted by photon shot noise.
The existing 0.33 NA EUV tools are challenged below 16 nm half-pitch resolution.<ref name=asmlbeol>T-B. Chiou ''et al.'', Proc. SPIE 9781, 978107 (2016).</ref> Tip-to-tip gaps are problematic for 16 nm dimensions.<ref>T. H-Bao ''et al.'', Proc. SPIE 9781, 978102 (2016).</ref> Consequently, EUV 2D patterning is limited to >32 nm pitch.<ref name=asmlbeol /> Recent studies of optimizing the EUV mask features and the illumination shape simultaneously have indicated that different patterns in the same metal layer could require different illuminations.<ref name=ychen>Y. Chen et al., J. Vac. Sci. Tech. B35, 06G601 (2017).</ref><ref>M. Crouse ''et al.'', Proc. SPIE 10148, 101480H (2017).</ref><ref>W. Gillijns ''et al.'', Proc. SPIE 10143, 1014314 (2017).</ref><ref>T. Last ''et al.'', Proc. SPIE 10143, 1014311 (2017).</ref><ref>S. Hsu ''et al.'', Proc. SPIE 9422, 94221I (2015).</ref> On the other hand, a single exposure only offers a single illumination.
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{| class="wikitable"
|-
! Patterning Method !! Normalized Wafer Cost<ref>{{cite book | doi=10.1117/12.2219321 | chapter=Self-aligned quadruple patterning integration using spacer on spacer pitch splitting at the resist level for sub-32nm pitch applications | title=Advanced Etch Technology for Nanopatterning V | date=2016 | editor-last1=Lin | editor-last2=Engelmann | editor-first1=Qinghuang | editor-first2=Sebastian U. | last1=Raley | first1=Angélique | last2=Thibaut | first2=Sophie | last3=Mohanty | first3=Nihar | last4=Subhadeep | first4=Kal | last5=Nakamura | first5=Satoru | last6=Ko | first6=Akiteru | last7=O'Meara | first7=David | last8=Tapily | first8=Kandabara | last9=Consiglio | first9=Steve | last10=Biolsi | first10=Peter | volume=9782 | pages=97820F }}</ref>
|-
| 193i SE || 1
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| EUV SADP || 6
|}
Compared to 193i SADP, EUV SADP cost is dominated by the EUV tool exposure, while the 193i SAQP cost difference is from the added depositions and etches. The processing cost and yield loss at a lithographic tool is expected to be highest in the whole integrated process flow due to the need to move the wafer to specific locations at high speed. EUV further suffers from the shot noise limit, which forces the dose to increase going for successive nodes.<ref>F. T. Chen ''et al.'', Proc. SPIE vol. 8326, 82362L (2012).</ref> On the other hand, depositions and etches process entire wafers at once, without the need for wafer stage motion in the process chamber. In fact, multiple layers may be added under the resist layer for anti-reflection or etch hard-mask purposes, just for conventional single exposure.
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| SADP/SAQP || 1st Self-Aligned Block Mask || 2nd Self-Aligned Block Mask
|-
| SADP/SAQP || Cut grid<ref name=cutgrid>M. C. Smayling et al., Proc. SPIE 8683, 868305 (2013).</ref><ref name=mpgrid>[https://www.linkedin.com/pulse/multipatterning-reduction-gridded-cuts-vias-frederick-chen-boojc Multipatterning Reduction with Gridded Cuts and Vias]</ref><ref name=smp>[https://www.youtube.com/watch?v=29mrRwHYiww Simplifying Multipattering with Gridded Cuts and Vias]</ref><ref name=gams>[https://chentfred.substack.com/p/exploring-grid-assisted-multipatterning Exploring Grid-Assisted Multipatterning Scenarios for 10A-14A Nodes]</ref> || Cut selection pattern<ref name=cutgrid/><ref name=mpgrid/><ref name=smp/><ref name=gams/>
|-
| EUV exposure || 1st Self-Aligned Block Mask || 2nd Self-Aligned Block Mask
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|-
|}
[[File:
For line patterning, SADP/SAQP could have the advantage over the EUV exposure, due to cost and maturity of the former approach and stochastic missing or bridging feature issues of the latter.<ref>P. Bisschop and E. Hendrickx, Proc. SPIE 10583, 105831K (2018).</ref> For grid ___location patterning, a single DUV exposure following grid formation also has the cost and maturity advantages (e.g., immersion lithography may not even be necessary for the spacer patterning in some cases) and no stochastic concerns associated with EUV. Grid ___location selection has an advantage over direct point cutting because the latter is sensitive to overlay and stochastic edge placement errors, which may distort the line ends.<ref name=euvlimits/><ref name=euv2012/> Vias located at staggered grid locations are also expected for routing and patterning convenience.<ref>P. Woltgens et al., Proc. SPIE 12051, 120510I (2022).</ref><ref>[https://www.youtube.com/watch?v=gUsZypJEY9c Staggered Vias Better Routing Than In-Line Vias]</ref>
[[File:SALELE at a glance.png|thumb|300px|right|'''SALELE (Self-aligned Litho-Etch-Litho-Etch.''' Plan view of SALELE process steps, taken together.]]
Self-aligned litho-etch-litho-etch (SALELE) is a hybrid SADP/LELE technique whose implementation has started in 7nm<ref>Q. Lin, Proc. SPIE 11327, 113270X (2020).</ref> and continued use in 5nm.<ref>[https://www.linkedin.com/pulse/salele-double-patterning-7nm-5nm-nodes-frederick-chen SALELE double patterning for 7nm and 5nm nodes]</ref>
===Multipatterning productivity improvements===
Since 2017, several publications have indicated ways to improve multipatterning productivity. Self-aligned blocking allows blocking or cutting patterns to cross adjacent lines.<ref>F. Lazzarino et al., Proc. SPIE 10149, 1014908 (2017)</ref> Cut redistribution allows distances between cuts to be adjusted to minimize the number of cut masks.<ref>Z. Xiao et al., Proc. SPIE 8880, 888017 (2013).</ref><ref>[https://www.linkedin.com/pulse/self-aligned-block-redistribution-expansion-improving-frederick-chen-rgnwc/ Self-Aligned Block Redistribution and Expansion for Improving Multipatterning Productivity]</ref> These techniques may also be combined with self-aligned vias, described earlier.<ref>J-H. Franke et al., Proc. SPIE 10145, 1014529 (2017).</ref>
The use of a via grid defined by intersecting diagonal lines can simplify patterning of both metal and via layers.<ref>[https://www.youtube.com/watch?v=KANhWaM9u_U 2nm Routing and Patterning Simplification with Diagonal Via Grid]</ref><ref>[https://chentfred.substack.com/p/routing-and-patterning-simplification Routing and Patterning Simplification with a Diagonal Via Grid]</ref>
==Industrial adoption==
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Self-aligned quadruple patterning (SAQP) is already the established process to be used for patterning fins for [[7 nm]] and [[5 nm]] [[FinFET]]s.<ref>[http://spie.org/newsroom/6378-self-aligned-quadruple-patterning-to-meet-requirements-for-fins-with-high-density SAQP for FinFETs]</ref> With SAQP, each patterning step gives a critical dimension uniformity (CDU) value in the sub-nanometer range (3 sigma). Among the logic/foundry manufacturers, only Intel is applying SAQP to the metal layers, as of 2017.<ref name=intel14nm>[https://newsroom.intel.com/newsroom/wp-content/uploads/sites/11/2017/03/Ruth-Brain-2017-Manufacturing.pdf Intel 14 nm Leadership]</ref>
Aggressive multipatterning with DUV only may be applied to 5nm.<ref>Q. Wu et al., CSTIC 2023.</ref><ref name=4func>[https://www.youtube.com/watch?v=sgTLAkNwYGc 4 Functions of DUV Masks for 5nm/3nm BEOL Patterning]</ref>
In 2023, [[SiCarrier]] patented a method of achieving 5nm design rules without EUV, effectively achieving the same result as with SAQP.<ref name=sicarrier>[https://chentfred.substack.com/p/sicarriers-saqp-class-patterning SiCarrier's SAQP-Class Patterning Technique: a Potential Domestic Solution for China's 5nm and Beyond]</ref>
===3nm node===
Aggressive multipatterning with DUV may be applied to even 3nm.<ref>[https://www.linkedin.com/pulse/extension-duv-multipatterning-toward-3nm-frederick-chen Extension of DUV Multipatterning Toward 3nm]</ref> Due to the increased expense of EUV multipatterning, DUV multipatterning does not have a cost disadvantage anymore. Aggressive mask reduction can essentially eliminate the mask number difference between DUV and EUV for BEOL patterning.<ref>[https://www.linkedin.com/pulse/beol-mask-reduction-using-spacer-defined-vias-cuts-frederick-chen-zxdhc BEOL Mask Reduction Using Spacer-Defined Vias and Cuts]</ref><ref name=4func/><ref name=sicarrier/>
===DRAM===
Like NAND Flash, DRAM has also made regular use of multiple patterning. Even though the active areas form a two-dimensional array, one cut mask is sufficient for 20 nm.<ref>Y-S. Kang et al., J. Micro/Nanolith. MEMS MOEMS vol. 15(2), 021403 (2016).</ref> Furthermore, the cut mask may be simultaneously used for patterning the periphery, and thus would not count as an extra mask.<ref>U.S. Patent 7253118.</ref> When the active area long pitch is ~3.5 x the short pitch, the breaks in the active area form a hexagonal array, which is amenable to the triangular lattice spacer patterning mentioned above. Samsung has already started manufacturing the 18 nm DRAM.<ref>[http://www.techinsights.com/about-techinsights/overview/blog/samsung-18-nm-dram-cell-integration-qpt-and-higher-uniformed-capacitor-high-k-dielectrics/ Samsung 18 nm DRAM]</ref> Multiple exposures may be used for the periphery metal routing of DRAM, but this is also unnecessary, as a triple spacer approach offers 1/5 pitch reduction.<ref>[https://www.youtube.com/watch?v=gbwQ0dqyYU8 Triple Spacer Patterning for DRAM Periphery Metal]</ref>
Crossed self-aligned quadruple patterning is used for patterning the capacitor arrays in state-of-the-art DRAM, as of 2025.<ref>[https://chentfred.substack.com/p/crossed-self-aligned-multipatterning Crossed Self-Aligned Multipatterning For Sub-40 nm Pitch Grids: A Process On Record For DRAM]</ref><ref>Md. S. Rahman et al., Proc. SPIE 13427, 134270G (2025).</ref>
===NAND flash===
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Hence, multiple patterning for EUV at wider design rules is presently a practical consideration for both yield and throughput reasons.
In 2025, it was revealed that random 36 nm via patterns required EUV double patterning to avoid excessive doses,<ref>C. Zahlten, Proc. SPIE 13424, 134240Z (2025).</ref><ref>[https://www.youtube.com/watch?v=CWrDaUvTxIE Stochastic EUV Exposure of 36 nm Via]</ref> yet DUV double patterning would have been sufficient.<ref>[https://frederickchen.substack.com/p/high-na-hard-sell-euv-multipatterning High-NA Hard Sell: EUV Multipatterning Practices Revealed, Depth of Focus Not Mentioned]</ref>
==References==
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[[Category:Lithography (microfabrication)]]
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