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{{short description|Technique used to increase the number of structures a microchip may contain}}
{{jargon|date=December 2022}}
'''Multiple patterning''' (or '''multi-patterning''') is a class of technologies for manufacturing [[integrated
[[File:Different_multipatterning_techniques.png|thumb|right|300px|'''Different techniques for multiple patterning'''<br/>''Top:'' Splitting of features into groups (3 shown here), each patterned by a different mask<br/>''Center:'' Use of a spacer to generate additional separate features in the gaps<br/>''Bottom:'' Use of an opposite polarity feature to cut (small break) pre-existing features]]
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[[Image:Trench doubling.svg|left|thumb| '''Double Expose, Double Etch (trenches):''' Photoresist coating over first pattern; etching adjacent to previous features; Photoresist removal]]
[[File:Pitch splitting.png|thumb|right|150px|'''Double patterning by pitch splitting.''' Double patterning by pitch splitting involves assigning adjacent features to two different masks, indicated by the different colors. It remains the simplest multiple patterning approach practiced today, and adds less cost than EUV.]]
[[File:EUV triple patterning vs DUV quadruple patterning.png|thumb|left|Some bidirectional metal layouts will force more than double patterning for either EUV or DUV if the minimum space between metal is too small.]]
[[File:Stitch Double Patterning.png|right|thumb|Sometimes, it is necessary to "stitch" two separately printed features into a single feature.]]
The earliest form of multiple patterning involved simply dividing a pattern into two or three parts, each of which may be processed conventionally, with the entire pattern combined at the end in the final layer. This is sometimes called ''pitch splitting'', since two features separated by one pitch cannot be imaged, so only skipped features can be imaged at once. It is also named more directly as "LELE" (Litho-Etch-Litho-Etch). This approach has been used for the 20 nm and 14 nm nodes. The additional cost of extra exposures was tolerated since only a few critical layers would need them. A more serious concern was the effect of feature-to-feature positioning errors (overlay). Consequently, the self-aligned sidewall imaging approach (described below) has succeeded this approach.
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This is best described by considering a process example. A first exposure of photoresist is transferred to an underlying hardmask layer. After the photoresist is removed following the hardmask pattern transfer, a second layer of photoresist is coated onto the sample and this layer undergoes a second exposure, imaging features in between the features patterned in the hardmask layer. The surface pattern is made up of photoresist features edged between mask features, which can be transferred into the final layer underneath. This allows a doubling of feature density.
For advanced nodes, both EUV and DUV may require splitting bidirectional layouts into more than two parts, resulting in triple and quadruple patterning, respectively.<ref>[https://www.youtube.com/watch?v=qiCOpeQJZPM DUV or EUV multipatterning for advanced node bidirectional metal layouts]</ref>
Sometimes, it is necessary to "stitch" two separately printed features into a single feature.<ref>S-Min Kim et al., Proc. SPIE 6520, 65200H (2007).</ref><ref>Y. Kohira et al., Proc. SPIE 9053, 90530T (2014).</ref><ref>[https://www.linkedin.com/pulse/application-specific-lithography-sense-amplifier-driver-chen-wnfuc/ Application-Specific Lithography: Sense Amplifier and Sub-Wordline Driver Metal Patterning in DRAM]</ref>▼
▲Sometimes, it is necessary to "stitch" two separately printed features into a single feature.<ref>S-Min Kim et al., Proc. SPIE 6520, 65200H (2007).</ref><ref>Y. Kohira et al., Proc. SPIE 9053, 90530T (2014).</ref><ref>[https://www.linkedin.com/pulse/application-specific-lithography-sense-amplifier-driver-chen-wnfuc/ Application-Specific Lithography: Sense Amplifier and Sub-Wordline Driver Metal Patterning in DRAM]</ref> This form of double patterning was used down to ~15nm DRAM and possibly beyond.<ref>[https://chentfred.substack.com/p/stitched-multi-patterning-for-minimum Stitched Multi-Patterning for Minimum Pitch Metal in DRAM Periphery]</ref>
A variation on this approach which eliminates the first hardmask etch is ''resist freezing'',<ref>{{cite web|title=Scaling-driven nanoelectronics - Resists|url=http://www2.imec.be:80/be_en/research/scaling-driven-nanoelectronics/lithography/resists.html|archive-url=https://web.archive.org/web/20100323021819/http://www2.imec.be/be_en/research/scaling-driven-nanoelectronics/lithography/resists.html|archive-date=2010-03-23|url-status=dead}}</ref> which allows a second resist coating over the first developed resist layer. JSR has demonstrated 32 nm lines and spaces using this method,<ref>{{cite web|last1=LaPedus|first1=Mark|title=JSR demos 'freezing material' for 22-nm production|url=http://www.eetimes.com/document.asp?doc_id=1168180|archive-url=https://web.archive.org/web/20140715005922/http://www.eetimes.com/document.asp?doc_id=1168180|archive-date=2014-07-15|date=March 13, 2008}}</ref> where the freezing is accomplished by surface hardening of the first resist layer.
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==Multi-Spacer Pitch Reduction==
Iterations of deposition followed by etching or controlled etchback of multilayers can result in substantial pitch reduction beyond SAQP.<ref>[https://chentfred.substack.com/p/variable-cell-height-track-pitch Variable Cell Height Track Pitch Scaling Beyond Lithography
==Directed self-assembly (DSA)==
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The line edge roughness in block copolymer patterns is strongly dependent on the interface tension between the two phases, which in turn, depends on the Flory "chi" (χ) parameter.<ref>[https://www.nist.gov/pml/div683/conference/upload/wu_2011.pdf NIST 2011 report on LER in PS-b-PMMA DSA]</ref> A higher value of χ is preferred for reduced roughness; the interfacial width between domains is equal to 2a(6χ)<sup>−1/2</sup>, where a is the statistical polymer chain length.<ref>A. N. Semenov, Macromolecules 26, 6617 (1993).</ref> Moreover, χN > 10.5 is required for sufficient phase segregation, where N is the degree of polymerization (number of monomer repeats in the chain). On the other hand, the half-pitch is equal to 2(3/π<sup>2</sup>)<sup>1/3</sup>aN<sup>2/3</sup>χ<sup>1/6</sup>. The fluctuations of the pattern widths are actually only weakly (square root) dependent on the logarithm of the half-pitch, so they become more significant relative to smaller half-pitches.
DSA has not yet been implemented in manufacturing, due to defect concerns, where a feature does not appear as expected by the guided self-assembly.<ref>A. Gharbi et al., Proc. SPIE 9777, 97770T (2016).</ref> However, there has been some progress in understanding ways to reduce defectivity for sub-10 nm half-pitch line patterns.<ref>[https://chentfred.substack.com/p/sub-10-nm-half-pitch-density-multiplication Sub-10 nm Half-Pitch Density Multiplication by Directed Self-Assembly]</ref>
At IWAPS 2024, Fudan University showed large-area, defect-free arrays using a quadruple-hole patterning technique based on DSA, which potentially significantly reduces the number of masks used in multipatterning.<ref>[https://www.linkedin.com/pulse/chinas-multipatterning-breakthrough-quadruple-hole-patterning-chen-9iskc/ China’s Multipatterning Breakthrough? Quadruple Hole Patterning by Directed Self-Assembly on a Staggered Via Grid]</ref><ref>Z. Wu et al., Proc. SPIE 13423, 134231O (2024).</ref>
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===Multipatterning productivity improvements===
Since 2017, several publications have indicated ways to improve multipatterning productivity. Self-aligned blocking allows blocking or cutting patterns to cross adjacent lines.<ref>F. Lazzarino et al., Proc. SPIE 10149, 1014908 (2017)</ref> Cut redistribution allows distances between cuts to be adjusted to minimize the number of cut masks.<ref>Z. Xiao et al., Proc. SPIE 8880, 888017 (2013).</ref><ref>[https://www.linkedin.com/pulse/self-aligned-block-redistribution-expansion-improving-frederick-chen-rgnwc/ Self-Aligned Block Redistribution and Expansion for Improving Multipatterning Productivity]</ref> These techniques may also be combined with self-aligned vias, described earlier.<ref>J-H. Franke et al., Proc. SPIE 10145, 1014529 (2017).</ref>
The use of a via grid defined by intersecting diagonal lines can simplify patterning of both metal and via layers.<ref>[https://www.youtube.com/watch?v=KANhWaM9u_U 2nm Routing and Patterning Simplification with Diagonal Via Grid]</ref><ref>[https://chentfred.substack.com/p/routing-and-patterning-simplification Routing and Patterning Simplification with a Diagonal Via Grid]</ref>
==Industrial adoption==
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Self-aligned quadruple patterning (SAQP) is already the established process to be used for patterning fins for [[7 nm]] and [[5 nm]] [[FinFET]]s.<ref>[http://spie.org/newsroom/6378-self-aligned-quadruple-patterning-to-meet-requirements-for-fins-with-high-density SAQP for FinFETs]</ref> With SAQP, each patterning step gives a critical dimension uniformity (CDU) value in the sub-nanometer range (3 sigma). Among the logic/foundry manufacturers, only Intel is applying SAQP to the metal layers, as of 2017.<ref name=intel14nm>[https://newsroom.intel.com/newsroom/wp-content/uploads/sites/11/2017/03/Ruth-Brain-2017-Manufacturing.pdf Intel 14 nm Leadership]</ref>
Aggressive multipatterning with DUV only may be applied to 5nm.<ref>Q. Wu et al., CSTIC 2023.</ref><ref name=4func>[https://www.youtube.com/watch?v=sgTLAkNwYGc 4 Functions of DUV Masks for 5nm/3nm BEOL Patterning]</ref>
In 2023, [[SiCarrier]] patented a method of achieving 5nm design rules without EUV, effectively achieving the same result as with SAQP.<ref name=sicarrier>[https://chentfred.substack.com/p/sicarriers-saqp-class-patterning SiCarrier's SAQP-Class Patterning Technique: a Potential Domestic Solution for China's 5nm and Beyond]</ref>
===3nm node===
Aggressive multipatterning with DUV may be applied to even 3nm.<ref>[https://www.linkedin.com/pulse/extension-duv-multipatterning-toward-3nm-frederick-chen Extension of DUV Multipatterning Toward 3nm]</ref> Due to the increased expense of EUV multipatterning, DUV multipatterning does not have a cost disadvantage anymore. Aggressive mask reduction can essentially eliminate the mask number difference between DUV and EUV for BEOL patterning.<ref>[https://www.linkedin.com/pulse/beol-mask-reduction-using-spacer-defined-vias-cuts-frederick-chen-zxdhc BEOL Mask Reduction Using Spacer-Defined Vias and Cuts]</ref><ref name=4func/><ref name=sicarrier/>
===DRAM===
Like NAND Flash, DRAM has also made regular use of multiple patterning. Even though the active areas form a two-dimensional array, one cut mask is sufficient for 20 nm.<ref>Y-S. Kang et al., J. Micro/Nanolith. MEMS MOEMS vol. 15(2), 021403 (2016).</ref> Furthermore, the cut mask may be simultaneously used for patterning the periphery, and thus would not count as an extra mask.<ref>U.S. Patent 7253118.</ref> When the active area long pitch is ~3.5 x the short pitch, the breaks in the active area form a hexagonal array, which is amenable to the triangular lattice spacer patterning mentioned above. Samsung has already started manufacturing the 18 nm DRAM.<ref>[http://www.techinsights.com/about-techinsights/overview/blog/samsung-18-nm-dram-cell-integration-qpt-and-higher-uniformed-capacitor-high-k-dielectrics/ Samsung 18 nm DRAM]</ref> Multiple exposures may be used for the periphery metal routing of DRAM, but this is also unnecessary, as a triple spacer approach offers 1/5 pitch reduction.<ref>[https://www.youtube.com/watch?v=gbwQ0dqyYU8 Triple Spacer Patterning for DRAM Periphery Metal]</ref>
Crossed self-aligned quadruple patterning is used for patterning the capacitor arrays in state-of-the-art DRAM, as of 2025.<ref>[https://chentfred.substack.com/p/crossed-self-aligned-multipatterning Crossed Self-Aligned Multipatterning For Sub-40 nm Pitch Grids: A Process On Record For DRAM]</ref><ref>Md. S. Rahman et al., Proc. SPIE 13427, 134270G (2025).</ref>
===NAND flash===
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Hence, multiple patterning for EUV at wider design rules is presently a practical consideration for both yield and throughput reasons.
In 2025, it was revealed that random 36 nm via patterns required EUV double patterning to avoid excessive doses,<ref>C. Zahlten, Proc. SPIE 13424, 134240Z (2025).</ref><ref>[https://www.youtube.com/watch?v=CWrDaUvTxIE Stochastic EUV Exposure of 36 nm Via]</ref> yet DUV double patterning would have been sufficient.<ref>[https://frederickchen.substack.com/p/high-na-hard-sell-euv-multipatterning High-NA Hard Sell: EUV Multipatterning Practices Revealed, Depth of Focus Not Mentioned]</ref>
==References==
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[[Category:Lithography (microfabrication)]]
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