Multiple patterning: Difference between revisions

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{{short description|Technique used to increase the number of structures a microchip may contain}}

{{jargon|date=December 2022}}

'''Multiple patterning''' (or '''multi-patterning''') is a class of technologies for manufacturing [[integrated circuitscircuit]]s (ICs), developed for [[photolithography]] to enhance the feature density. It is expected to be necessary for the 10 nm and 7 nm node semiconductor processes and beyond. The premise is that a single lithographic exposure may not be enough to provide sufficient resolution. Hence additional exposures would be needed, or else positioning patterns using etched feature sidewalls (using spacers) would be necessary.

[[File:Different_multipatterning_techniques.png|thumb|right|300px|'''Different techniques for multiple patterning'''<br/>''Top:'' Splitting of features into groups (3 shown here), each patterned by a different mask<br/>''Center:'' Use of a spacer to generate additional separate features in the gaps<br/>''Bottom:'' Use of an opposite polarity feature to cut (small break) pre-existing features]]

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[[Image:Trench doubling.svg|left|thumb| '''Double Expose, Double Etch (trenches):''' Photoresist coating over first pattern; etching adjacent to previous features; Photoresist removal]]

[[File:Pitch splitting.png|thumb|right|150px|'''Double patterning by pitch splitting.''' Double patterning by pitch splitting involves assigning adjacent features to two different masks, indicated by the different colors. It remains the simplest multiple patterning approach practiced today, and adds less cost than EUV.]]

[[File:EUV triple patterning vs DUV quadruple patterning.png|thumb|left|Some bidirectional metal layouts will force more than double patterning for either EUV or DUV if the minimum space between metal is too small.]]

[[File:Stitch Double Patterning.png|right|thumb|Sometimes, it is necessary to "stitch" two separately printed features into a single feature.]]

The earliest form of multiple patterning involved simply dividing a pattern into two or three parts, each of which may be processed conventionally, with the entire pattern combined at the end in the final layer. This is sometimes called ''pitch splitting'', since two features separated by one pitch cannot be imaged, so only skipped features can be imaged at once. It is also named more directly as "LELE" (Litho-Etch-Litho-Etch). This approach has been used for the 20&nbsp;nm and 14&nbsp;nm nodes. The additional cost of extra exposures was tolerated since only a few critical layers would need them. A more serious concern was the effect of feature-to-feature positioning errors (overlay). Consequently, the self-aligned sidewall imaging approach (described below) has succeeded this approach.

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The line edge roughness in block copolymer patterns is strongly dependent on the interface tension between the two phases, which in turn, depends on the Flory "chi" (χ) parameter.<ref>[https://www.nist.gov/pml/div683/conference/upload/wu_2011.pdf NIST 2011 report on LER in PS-b-PMMA DSA]</ref> A higher value of χ is preferred for reduced roughness; the interfacial width between domains is equal to 2a(6χ)^−1/2, where a is the statistical polymer chain length.<ref>A. N. Semenov, Macromolecules 26, 6617 (1993).</ref> Moreover, χN > 10.5 is required for sufficient phase segregation, where N is the degree of polymerization (number of monomer repeats in the chain). On the other hand, the half-pitch is equal to 2(3/π²)^1/3aN^2/3χ^1/6. The fluctuations of the pattern widths are actually only weakly (square root) dependent on the logarithm of the half-pitch, so they become more significant relative to smaller half-pitches.

DSA has not yet been implemented in manufacturing, due to defect concerns, where a feature does not appear as expected by the guided self-assembly.<ref>A. Gharbi et al., Proc. SPIE 9777, 97770T (2016).</ref> However, there has been some progress in understanding ways to reduce defectivity for sub-10 nm half-pitch line patterns.<ref>[https://chentfred.substack.com/p/sub-10-nm-half-pitch-density-multiplication Sub-10 nm Half-Pitch Density Multiplication by Directed Self-Assembly]</ref>

At IWAPS 2024, Fudan University showed large-area, defect-free arrays using a quadruple-hole patterning technique based on DSA, which potentially significantly reduces the number of masks used in multipatterning.<ref>[https://www.linkedin.com/pulse/chinas-multipatterning-breakthrough-quadruple-hole-patterning-chen-9iskc/ China’s Multipatterning Breakthrough? Quadruple Hole Patterning by Directed Self-Assembly on a Staggered Via Grid]</ref><ref>Z. Wu et al., Proc. SPIE 13423, 134231O (2024).</ref>

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===DRAM===

Like NAND Flash, DRAM has also made regular use of multiple patterning. Even though the active areas form a two-dimensional array, one cut mask is sufficient for 20 nm.<ref>Y-S. Kang et al., J. Micro/Nanolith. MEMS MOEMS vol. 15(2), 021403 (2016).</ref> Furthermore, the cut mask may be simultaneously used for patterning the periphery, and thus would not count as an extra mask.<ref>U.S. Patent 7253118.</ref> When the active area long pitch is ~3.5 x the short pitch, the breaks in the active area form a hexagonal array, which is amenable to the triangular lattice spacer patterning mentioned above. Samsung has already started manufacturing the 18 nm DRAM.<ref>[http://www.techinsights.com/about-techinsights/overview/blog/samsung-18-nm-dram-cell-integration-qpt-and-higher-uniformed-capacitor-high-k-dielectrics/ Samsung 18 nm DRAM]</ref> Multiple exposures may be used for the periphery metal routing of DRAM, but this is also unnecessary, as a triple spacer approach offers 1/5 pitch reduction.<ref>[https://www.youtube.com/watch?v=gbwQ0dqyYU8 Triple Spacer Patterning for DRAM Periphery Metal]</ref>

Crossed self-aligned quadruple patterning is used for patterning the capacitor arrays in state-of-the-art DRAM, as of 2025.<ref>[https://chentfred.substack.com/p/crossed-self-aligned-multipatterning Crossed Self-Aligned Multipatterning For Sub-40 nm Pitch Grids: A Process On Record For DRAM]</ref><ref>Md. S. Rahman et al., Proc. SPIE 13427, 134270G (2025).</ref>

===NAND flash===

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Hence, multiple patterning for EUV at wider design rules is presently a practical consideration for both yield and throughput reasons.

In 2025, it was revealed that random 36 nm via patterns required EUV double patterning to avoid excessive doses,<ref>C. Zahlten, Proc. SPIE 13424, 134240Z (2025).</ref><ref>[https://www.youtube.com/watch?v=CWrDaUvTxIE Stochastic EUV Exposure of 36 nm Via]</ref> yet DUV double patterning would have been sufficient.<ref>[https://frederickchen.substack.com/p/high-na-hard-sell-euv-multipatterning High-NA Hard Sell: EUV Multipatterning Practices Revealed, Depth of Focus Not Mentioned]</ref>

==References==

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[[Category:Lithography (microfabrication)]]

[[Category:Indian inventions]]