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{{No inline|date=November 2024}}{{Machine code}}
An '''opcode table''' is a visual representation of all [[opcode]]s in an instruction set. It is arranged such that each axis of the table represents an upper or lower [[nibble]], which combined form the full byte of the opcode.
 
An '''opcode table''' (also called an '''opcode matrix''') is a visual representation of all [[opcode]]s in an instruction set. It is arranged such that each axis of the table represents an upper or lower [[nibble]], which combined form the full byte of the opcode. Additional opcode tables can exist for additional instructions created using an [[opcode prefix]].
==External Links==
 
* [http://clrhome.org/table/ A Z80 instruction set opcode table]
==Table values==
The structure and arrangement of an opcode table appears as follows:
{| class="wikitable" style="text-align: center;"
!
! scope="column" | 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E || F
|-
! scope="row" | 0
| 00 || 01 || 02 || 03 || 04 || 05 || 06 || 07 || 08 || 09 || 0A || 0B || 0C || 0D || 0E || 0F
|-
! scope="row" | 1
| 10 || 11 || 12 || 13 || 14 || 15 || 16 || 17 || 18 || 19 || 1A || 1B || 1C || 1D || 1E || 1F
|-
! scope="row" | 2
| 20 || 21 || 22 || 23 || 24 || 25 || 26 || 27 || 28 || 29 || 2A || 2B || 2C || 2D || 2E || 2F
|-
! scope="row" | 3
| 30 || 31 || 32 || 33 || 34 || 35 || 36 || 37 || 38 || 39 || 3A || 3B || 3C || 3D || 3E || 3F
|-
! scope="row" | 4
| 40 || 41 || 42 || 43 || 44 || 45 || 46 || 47 || 48 || 49 || 4A || 4B || 4C || 4D || 4E || 4F
|-
! scope="row" | 5
| 50 || 51 || 52 || 53 || 54 || 55 || 56 || 57 || 58 || 59 || 5A || 5B || 5C || 5D || 5E || 5F
|-
! scope="row" | 6
| 60 || 61 || 62 || 63 || 64 || 65 || 66 || 67 || 68 || 69 || 6A || 6B || 6C || 6D || 6E || 6F
|-
! scope="row" | 7
| 70 || 71 || 72 || 73 || 74 || 75 || 76 || 77 || 78 || 79 || 7A || 7B || 7C || 7D || 7E || 7F
|-
! scope="row" | 8
| 80 || 81 || 82 || 83 || 84 || 85 || 86 || 87 || 88 || 89 || 8A || 8B || 8C || 8D || 8E || 8F
|-
! scope="row" | 9
| 90 || 91 || 92 || 93 || 94 || 95 || 96 || 97 || 98 || 99 || 9A || 9B || 9C || 9D || 9E || 9F
|-
! scope="row" | A
| A0 || A1 || A2 || A3 || A4 || A5 || A6 || A7 || A8 || A9 || AA || AB || AC || AD || AE || AF
|-
! scope="row" | B
| B0 || B1 || B2 || B3 || B4 || B5 || B6 || B7 || B8 || B9 || BA || BB || BC || BD || BE || BF
|-
! scope="row" | C
| C0 || C1 || C2 || C3 || C4 || C5 || C6 || C7 || C8 || C9 || CA || CB || CC || CD || CE || CF
|-
! scope="row" | D
| D0 || D1 || D2 || D3 || D4 || D5 || D6 || D7 || D8 || D9 || DA || DB || DC || DD || DE || DF
|-
! scope="row" | E
| E0 || E1 || E2 || E3 || E4 || E5 || E6 || E7 || E8 || E9 || EA || EB || EC || ED || EE || EF
|-
! scope="row" | F
| F0 || F1 || F2 || F3 || F4 || F5 || F6 || F7 || F8 || F9 || FA || FB || FC || FD || FE || FF
|}
 
Each cell from 00-FF contains information about the operation such as the equivalent assembly instruction corresponding to the opcode, parameters, and CPU cycle counts.
 
==Example opcode table==
This is the opcode table for the [[MOS Technology 6502]] microprocessor from 1975. The 6502 uses 8-bit opcodes. Of the 256 possible opcodes available using an 8-bit pattern, the original 6502 uses only 151 of them, organized into 56 instructions with (possibly) multiple [[addressing mode]]s.<ref name=ii>{{cite web |url=http://nparker.llx.com/a2/opcodes.html |title=The 6502/65C02/65C816 Instruction Set Decoded |first=Neil |last=Parker |website=Neil Parker's Apple II page |access-date=2019-07-16 |archive-date=2019-07-16 |archive-url=https://web.archive.org/web/20190716023057/http://nparker.llx.com/a2/opcodes.html |url-status=live}}</ref> Because not all 256 opcodes are used, some opcode spaces are blank and the low nibble columns 3, 7, B, and F are missing from the table.
 
{| class="wikitable"
!colspan=13| Opcode matrix for the 6502 instruction set
|-
|colspan=13| Addressing modes: {{font color||#e0e0e0|'''''A'''''}} – accumulator, {{font color||#99ff99|'''''#'''''}} – immediate, {{font color||#ffe0e0|'''''zpg'''''}} – zero page, {{font color||#e0ffff|'''''abs'''''}} – absolute, {{font color||#ffc299|'''''ind'''''}} – indirect, '''''X''''' – indexed by X register, '''''Y''''' – indexed by Y register, {{font color||#ffffe0|'''''rel'''''}} – relative
|-
!rowspan=2| High nibble ||colspan=12| Low nibble
|-
! 0|| 1|| 2|| 4|| 5|| 6|| 8|| 9|| A|| C|| D|| E
|-
! 0
| bgcolor=#e0e0e0|BRK
| bgcolor=#ffc299|ORA (''ind'',X)
|
|
| bgcolor=#ffe0e0|ORA ''zpg''
| bgcolor=#ffe0e0|ASL ''zpg''
| bgcolor=#e0e0e0|PHP
| bgcolor=#99ff99|ORA #
| bgcolor=#e0e0e0|ASL A
|
| bgcolor=#e0ffff|ORA ''abs''
| bgcolor=#e0ffff|ASL ''abs''
|-
! 1
| bgcolor=#ffffe0|BPL ''rel''
| bgcolor=#ffc299|ORA (''ind''),Y
|
|
| bgcolor=#ffe0e0|ORA ''zpg'',X
| bgcolor=#ffe0e0|ASL ''zpg'',X
| bgcolor=#e0e0e0|CLC
| bgcolor=#e0ffff|ORA ''abs'',Y
|
|
| bgcolor=#e0ffff|ORA ''abs'',X
| bgcolor=#e0ffff|ASL ''abs'',X
|-
! 2
| bgcolor=#e0ffff|JSR ''abs''
| bgcolor=#ffc299|AND (''ind'',X)
|
| bgcolor=#ffe0e0|BIT ''zpg''
| bgcolor=#ffe0e0|AND ''zpg''
| bgcolor=#ffe0e0|ROL ''zpg''
| bgcolor=#e0e0e0|PLP
| bgcolor=#99ff99|AND #
| bgcolor=#e0e0e0|ROL A
| bgcolor=#e0ffff|BIT ''abs''
| bgcolor=#e0ffff|AND ''abs''
| bgcolor=#e0ffff|ROL ''abs''
|-
! 3
| bgcolor=#ffffe0|BMI ''rel''
| bgcolor=#ffc299|AND (''ind''),Y
|
|
| bgcolor=#ffe0e0|AND ''zpg'',X
| bgcolor=#ffe0e0|ROL ''zpg'',X
| bgcolor=#e0e0e0|SEC
| bgcolor=#e0ffff|AND ''abs'',Y
|
|
| bgcolor=#e0ffff|AND ''abs'',X
| bgcolor=#e0ffff|ROL ''abs'',X
|-
! 4
| bgcolor=#e0e0e0|RTI
| bgcolor=#ffc299|EOR (''ind'',X)
|
|
| bgcolor=#ffe0e0|EOR ''zpg''
| bgcolor=#ffe0e0|LSR ''zpg''
| bgcolor=#e0e0e0|PHA
| bgcolor=#99ff99|EOR #
| bgcolor=#e0e0e0|LSR A
| bgcolor=#e0ffff|JMP ''abs''
| bgcolor=#e0ffff|EOR ''abs''
| bgcolor=#e0ffff|LSR ''abs''
|-
! 5
| bgcolor=#ffffe0|BVC ''rel''
| bgcolor=#ffc299|EOR (''ind''),Y
|
|
| bgcolor=#ffe0e0|EOR ''zpg'',X
| bgcolor=#ffe0e0|LSR ''zpg'',X
| bgcolor=#e0e0e0|CLI
| bgcolor=#e0ffff|EOR ''abs'',Y
|
|
| bgcolor=#e0ffff|EOR ''abs'',X
| bgcolor=#e0ffff|LSR ''abs'',X
|-
! 6
| bgcolor=#e0e0e0|RTS
| bgcolor=#ffc299|ADC (''ind'',X)
|
|
| bgcolor=#ffe0e0|ADC ''zpg''
| bgcolor=#ffe0e0|ROR ''zpg''
| bgcolor=#e0e0e0|PLA
| bgcolor=#99ff99|ADC #
| bgcolor=#e0e0e0|ROR A
| bgcolor=#ffc299|JMP (''ind'')
| bgcolor=#e0ffff|ADC ''abs''
| bgcolor=#e0ffff|ROR ''abs''
|-
! 7
| bgcolor=#ffffe0|BVS ''rel''
| bgcolor=#ffc299|ADC (''ind''),Y
|
|
| bgcolor=#ffe0e0|ADC ''zpg'',X
| bgcolor=#ffe0e0|ROR ''zpg'',X
| bgcolor=#e0e0e0|SEI
| bgcolor=#e0ffff|ADC ''abs'',Y
|
|
| bgcolor=#e0ffff|ADC ''abs'',X
| bgcolor=#e0ffff|ROR ''abs'',X
|-
! 8
|
| bgcolor=#ffc299|STA (''ind'',X)
|
| bgcolor=#ffe0e0|STY ''zpg''
| bgcolor=#ffe0e0|STA ''zpg''
| bgcolor=#ffe0e0|STX ''zpg''
| bgcolor=#e0e0e0|DEY
|
| bgcolor=#e0e0e0|TXA
| bgcolor=#e0ffff|STY ''abs''
| bgcolor=#e0ffff|STA ''abs''
| bgcolor=#e0ffff|STX ''abs''
|-
! 9
| bgcolor=#ffffe0|BCC ''rel''
| bgcolor=#ffc299|STA (''ind''),Y
|
| bgcolor=#ffe0e0|STY ''zpg'',X
| bgcolor=#ffe0e0|STA ''zpg'',X
| bgcolor=#ffe0e0|STX ''zpg'',Y
| bgcolor=#e0e0e0|TYA
| bgcolor=#e0ffff|STA ''abs'',Y
| bgcolor=#e0e0e0|TXS
|
| bgcolor=#e0ffff|STA ''abs'',X
|
|-
! A
| bgcolor=#99ff99|LDY #
| bgcolor=#ffc299|LDA (''ind'',X)
| bgcolor=#99ff99|LDX #
| bgcolor=#ffe0e0|LDY ''zpg''
| bgcolor=#ffe0e0|LDA ''zpg''
| bgcolor=#ffe0e0|LDX ''zpg''
| bgcolor=#e0e0e0|TAY
| bgcolor=#99ff99|LDA #
| bgcolor=#e0e0e0|TAX
| bgcolor=#e0ffff|LDY ''abs''
| bgcolor=#e0ffff|LDA ''abs''
| bgcolor=#e0ffff|LDX ''abs''
|-
! B
| bgcolor=#ffffe0|BCS ''rel''
| bgcolor=#ffc299|LDA (''ind''),Y
|
| bgcolor=#ffe0e0|LDY ''zpg'',X
| bgcolor=#ffe0e0|LDA ''zpg'',X
| bgcolor=#ffe0e0|LDX ''zpg'',Y
| bgcolor=#e0e0e0|CLV
| bgcolor=#e0ffff|LDA ''abs'',Y
| bgcolor=#e0e0e0|TSX
| bgcolor=#e0ffff|LDY ''abs'',X
| bgcolor=#e0ffff|LDA ''abs'',X
| bgcolor=#e0ffff|LDX ''abs'',Y
|-
! C
| bgcolor=#99ff99|CPY #
| bgcolor=#ffc299|CMP (''ind'',X)
|
| bgcolor=#ffe0e0|CPY ''zpg''
| bgcolor=#ffe0e0|CMP ''zpg''
| bgcolor=#ffe0e0|DEC ''zpg''
| bgcolor=#e0e0e0|INY
| bgcolor=#99ff99|CMP #
| bgcolor=#e0e0e0|DEX
| bgcolor=#e0ffff|CPY ''abs''
| bgcolor=#e0ffff|CMP ''abs''
| bgcolor=#e0ffff|DEC ''abs''
|-
! D
| bgcolor=#ffffe0|BNE ''rel''
| bgcolor=#ffc299|CMP (''ind''),Y
|
|
| bgcolor=#ffe0e0|CMP ''zpg'',X
| bgcolor=#ffe0e0|DEC ''zpg'',X
| bgcolor=#e0e0e0| CLD
| bgcolor=#e0ffff|CMP ''abs'',Y
|
|
| bgcolor=#e0ffff|CMP ''abs'',X
| bgcolor=#e0ffff|DEC ''abs'',X
|-
! E
| bgcolor=#99ff99|CPX #
| bgcolor=#ffc299|SBC (''ind'',X)
|
| bgcolor=#ffe0e0|CPX ''zpg''
| bgcolor=#ffe0e0|SBC ''zpg''
| bgcolor=#ffe0e0|INC ''zpg''
| bgcolor=#e0e0e0|INX
| bgcolor=#99ff99|SBC #
| bgcolor=#e0e0e0|NOP
| bgcolor=#e0ffff|CPX ''abs''
| bgcolor=#e0ffff|SBC ''abs''
| bgcolor=#e0ffff|INC ''abs''
|-
! F
| bgcolor=#ffffe0|BEQ ''rel''
| bgcolor=#ffc299|SBC (''ind''),Y
|
|
| bgcolor=#ffe0e0|SBC ''zpg'',X
| bgcolor=#ffe0e0|INC ''zpg'',X
| bgcolor=#e0e0e0|SED
| bgcolor=#e0ffff|SBC ''abs'',Y
|
|
| bgcolor=#e0ffff|SBC ''abs'',X
| bgcolor=#e0ffff|INC ''abs'',X
|-
|}
 
== References ==
{{Reflist}}
 
==External links==
* [http://www.pastraiser.com/cpu/gameboy/gameboy_opcodes.html Game Boy LR35902 opcode table]
* [http://clrhome.org/table/ Z80 opcode table]
* [http://www.sparksandflames.com/files/x86InstructionChart.html Intel x86 opcode table]
* [http://www.oxyron.de/html/opcodes02.html 6502/6510/8500/8502 opcode table]
 
[[Category:Machine code]]
Retrieved from "https://en.wikipedia.org/wiki/Opcode_table"