Wikipedia

Opcode table: Difference between revisions

Browse history interactively
← Previous edit
Content deleted Content added
VisualWikitext
No edit summary
 
(13 intermediate revisions by 11 users not shown)
Line 1:
{{unreferencedNo inline|date=MayNovember 2024}}{{Machine 2018code}}
 
An '''opcode table''' (also called an '''opcode matrix''') is a visual representation of all [[opcode]]s in an instruction set. It is arranged such that each axis of the table represents an upper or lower [[nibble]], which combined form the full byte of the opcode. Additional opcode tables can exist for additional instructions created using an [[opcode prefix]].
{{Machine code}}
 
An '''opcode table''' (also called an '''opcode matrix''') is a visual representation of all [[opcode]]s in an instruction set. It is arranged such that each axis of the table represents an upper or lower [[nibble]], which combined form the full byte of the opcode. Additional opcode tables can exist for additional instructions created using a [[opcode prefix]].
 
==Table values==
Line 60 ⟶ 58:
|}
 
Each cell from 00-FF contains information about the operation such as the equivalent assembly instruction corresponding to the opcode, parameters, and CPU cycle counts.
 
==Example opcode table==
This is the opcode table for the [[MOS Technology 6502]] microprocessor from 1975. The 6502 uses 8-bit opcodes. Of the 256 possible opcodes available using an 8-bit pattern, the original 6502 uses only 151 of them, organized into 56 instructions with (possibly) multiple [[addressing mode]]s.<ref name=ii>{{cite web |url=http://nparker.llx.com/a2/opcodes.html |title=The 6502/65C02/65C816 Instruction Set Decoded |first=Neil |last=Parker |website=Neil Parker's Apple II page |access-date=2019-07-16 |archive-date=2019-07-16 |archive-url=https://web.archive.org/web/20190716023057/http://nparker.llx.com/a2/opcodes.html |url-status=live}}</ref> Because not all 256 opcodes are used, some opcode spaces are blank and the low nibble columns 3, 7, B, and F are missing from the table.
 
{| class="wikitable"
!colspan=13| Opcode matrix for the 6502 instruction set
|-
|colspan=13| Addressing modes: {{font color||#e0e0e0|'''''A'''''}} – accumulator, {{font color||#99ff99|'''''#'''''}} – immediate, {{font color||#ffe0e0|'''''zpg'''''}} – zero page, {{font color||#e0ffff|'''''abs'''''}} – absolute, {{font color||#ffc299|'''''ind'''''}} – indirect, '''''X''''' – indexed by X register, '''''Y''''' – indexed by Y register, {{font color||#ffffe0|'''''rel'''''}} – relative
|-
!rowspan=2| High nibble ||colspan=12| Low nibble
|-
! 0|| 1|| 2|| 4|| 5|| 6|| 8|| 9|| A|| C|| D|| E
|-
! 0
| bgcolor=#e0e0e0|BRK
| bgcolor=#ffc299|ORA (''ind'',X)
|
|
| bgcolor=#ffe0e0|ORA ''zpg''
| bgcolor=#ffe0e0|ASL ''zpg''
| bgcolor=#e0e0e0|PHP
| bgcolor=#99ff99|ORA #
| bgcolor=#e0e0e0|ASL A
|
| bgcolor=#e0ffff|ORA ''abs''
| bgcolor=#e0ffff|ASL ''abs''
|-
! 1
| bgcolor=#ffffe0|BPL ''rel''
| bgcolor=#ffc299|ORA (''ind''),Y
|
|
| bgcolor=#ffe0e0|ORA ''zpg'',X
| bgcolor=#ffe0e0|ASL ''zpg'',X
| bgcolor=#e0e0e0|CLC
| bgcolor=#e0ffff|ORA ''abs'',Y
|
|
| bgcolor=#e0ffff|ORA ''abs'',X
| bgcolor=#e0ffff|ASL ''abs'',X
|-
! 2
| bgcolor=#e0ffff|JSR ''abs''
| bgcolor=#ffc299|AND (''ind'',X)
|
| bgcolor=#ffe0e0|BIT ''zpg''
| bgcolor=#ffe0e0|AND ''zpg''
| bgcolor=#ffe0e0|ROL ''zpg''
| bgcolor=#e0e0e0|PLP
| bgcolor=#99ff99|AND #
| bgcolor=#e0e0e0|ROL A
| bgcolor=#e0ffff|BIT ''abs''
| bgcolor=#e0ffff|AND ''abs''
| bgcolor=#e0ffff|ROL ''abs''
|-
! 3
| bgcolor=#ffffe0|BMI ''rel''
| bgcolor=#ffc299|AND (''ind''),Y
|
|
| bgcolor=#ffe0e0|AND ''zpg'',X
| bgcolor=#ffe0e0|ROL ''zpg'',X
| bgcolor=#e0e0e0|SEC
| bgcolor=#e0ffff|AND ''abs'',Y
|
|
| bgcolor=#e0ffff|AND ''abs'',X
| bgcolor=#e0ffff|ROL ''abs'',X
|-
! 4
| bgcolor=#e0e0e0|RTI
| bgcolor=#ffc299|EOR (''ind'',X)
|
|
| bgcolor=#ffe0e0|EOR ''zpg''
| bgcolor=#ffe0e0|LSR ''zpg''
| bgcolor=#e0e0e0|PHA
| bgcolor=#99ff99|EOR #
| bgcolor=#e0e0e0|LSR A
| bgcolor=#e0ffff|JMP ''abs''
| bgcolor=#e0ffff|EOR ''abs''
| bgcolor=#e0ffff|LSR ''abs''
|-
! 5
| bgcolor=#ffffe0|BVC ''rel''
| bgcolor=#ffc299|EOR (''ind''),Y
|
|
| bgcolor=#ffe0e0|EOR ''zpg'',X
| bgcolor=#ffe0e0|LSR ''zpg'',X
| bgcolor=#e0e0e0|CLI
| bgcolor=#e0ffff|EOR ''abs'',Y
|
|
| bgcolor=#e0ffff|EOR ''abs'',X
| bgcolor=#e0ffff|LSR ''abs'',X
|-
! 6
| bgcolor=#e0e0e0|RTS
| bgcolor=#ffc299|ADC (''ind'',X)
|
|
| bgcolor=#ffe0e0|ADC ''zpg''
| bgcolor=#ffe0e0|ROR ''zpg''
| bgcolor=#e0e0e0|PLA
| bgcolor=#99ff99|ADC #
| bgcolor=#e0e0e0|ROR A
| bgcolor=#ffc299|JMP (''ind'')
| bgcolor=#e0ffff|ADC ''abs''
| bgcolor=#e0ffff|ROR ''abs''
|-
! 7
| bgcolor=#ffffe0|BVS ''rel''
| bgcolor=#ffc299|ADC (''ind''),Y
|
|
| bgcolor=#ffe0e0|ADC ''zpg'',X
| bgcolor=#ffe0e0|ROR ''zpg'',X
| bgcolor=#e0e0e0|SEI
| bgcolor=#e0ffff|ADC ''abs'',Y
|
|
| bgcolor=#e0ffff|ADC ''abs'',X
| bgcolor=#e0ffff|ROR ''abs'',X
|-
! 8
|
| bgcolor=#ffc299|STA (''ind'',X)
|
| bgcolor=#ffe0e0|STY ''zpg''
| bgcolor=#ffe0e0|STA ''zpg''
| bgcolor=#ffe0e0|STX ''zpg''
| bgcolor=#e0e0e0|DEY
|
| bgcolor=#e0e0e0|TXA
| bgcolor=#e0ffff|STY ''abs''
| bgcolor=#e0ffff|STA ''abs''
| bgcolor=#e0ffff|STX ''abs''
|-
! 9
| bgcolor=#ffffe0|BCC ''rel''
| bgcolor=#ffc299|STA (''ind''),Y
|
| bgcolor=#ffe0e0|STY ''zpg'',X
| bgcolor=#ffe0e0|STA ''zpg'',X
| bgcolor=#ffe0e0|STX ''zpg'',Y
| bgcolor=#e0e0e0|TYA
| bgcolor=#e0ffff|STA ''abs'',Y
| bgcolor=#e0e0e0|TXS
|
| bgcolor=#e0ffff|STA ''abs'',X
|
|-
! A
| bgcolor=#99ff99|LDY #
| bgcolor=#ffc299|LDA (''ind'',X)
| bgcolor=#99ff99|LDX #
| bgcolor=#ffe0e0|LDY ''zpg''
| bgcolor=#ffe0e0|LDA ''zpg''
| bgcolor=#ffe0e0|LDX ''zpg''
| bgcolor=#e0e0e0|TAY
| bgcolor=#99ff99|LDA #
| bgcolor=#e0e0e0|TAX
| bgcolor=#e0ffff|LDY ''abs''
| bgcolor=#e0ffff|LDA ''abs''
| bgcolor=#e0ffff|LDX ''abs''
|-
! B
| bgcolor=#ffffe0|BCS ''rel''
| bgcolor=#ffc299|LDA (''ind''),Y
|
| bgcolor=#ffe0e0|LDY ''zpg'',X
| bgcolor=#ffe0e0|LDA ''zpg'',X
| bgcolor=#ffe0e0|LDX ''zpg'',Y
| bgcolor=#e0e0e0|CLV
| bgcolor=#e0ffff|LDA ''abs'',Y
| bgcolor=#e0e0e0|TSX
| bgcolor=#e0ffff|LDY ''abs'',X
| bgcolor=#e0ffff|LDA ''abs'',X
| bgcolor=#e0ffff|LDX ''abs'',Y
|-
! C
| bgcolor=#99ff99|CPY #
| bgcolor=#ffc299|CMP (''ind'',X)
|
| bgcolor=#ffe0e0|CPY ''zpg''
| bgcolor=#ffe0e0|CMP ''zpg''
| bgcolor=#ffe0e0|DEC ''zpg''
| bgcolor=#e0e0e0|INY
| bgcolor=#99ff99|CMP #
| bgcolor=#e0e0e0|DEX
| bgcolor=#e0ffff|CPY ''abs''
| bgcolor=#e0ffff|CMP ''abs''
| bgcolor=#e0ffff|DEC ''abs''
|-
! D
| bgcolor=#ffffe0|BNE ''rel''
| bgcolor=#ffc299|CMP (''ind''),Y
|
|
| bgcolor=#ffe0e0|CMP ''zpg'',X
| bgcolor=#ffe0e0|DEC ''zpg'',X
| bgcolor=#e0e0e0| CLD
| bgcolor=#e0ffff|CMP ''abs'',Y
|
|
| bgcolor=#e0ffff|CMP ''abs'',X
| bgcolor=#e0ffff|DEC ''abs'',X
|-
! E
| bgcolor=#99ff99|CPX #
| bgcolor=#ffc299|SBC (''ind'',X)
|
| bgcolor=#ffe0e0|CPX ''zpg''
| bgcolor=#ffe0e0|SBC ''zpg''
| bgcolor=#ffe0e0|INC ''zpg''
| bgcolor=#e0e0e0|INX
| bgcolor=#99ff99|SBC #
| bgcolor=#e0e0e0|NOP
| bgcolor=#e0ffff|CPX ''abs''
| bgcolor=#e0ffff|SBC ''abs''
| bgcolor=#e0ffff|INC ''abs''
|-
! F
| bgcolor=#ffffe0|BEQ ''rel''
| bgcolor=#ffc299|SBC (''ind''),Y
|
|
| bgcolor=#ffe0e0|SBC ''zpg'',X
| bgcolor=#ffe0e0|INC ''zpg'',X
| bgcolor=#e0e0e0|SED
| bgcolor=#e0ffff|SBC ''abs'',Y
|
|
| bgcolor=#e0ffff|SBC ''abs'',X
| bgcolor=#e0ffff|INC ''abs'',X
|-
|}
 
== References ==
{{Reflist}}
 
==External links==
* [http://www.pastraiser.com/cpu/gameboy/gameboy_opcodes.html GameBoyGame Boy LR35902 opcode table]
* [http://clrhome.org/table/ Z80 opcode table]
* [http://www.sparksandflames.com/files/x86InstructionChart.html Intel x86 opcode table]
Retrieved from "https://en.wikipedia.org/wiki/Opcode_table"