Reconfigurable computing: Difference between revisions

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{{Short description|computerComputer architecture that can be reprogrammed}}

{{Use American English|date = April 2019}}

{{Short description|computer architecture that can be reprogrammed}}

{{Technical|date=May 2009}}

'''Reconfigurable computing''' is a [[computer architecture]] combining some of the flexibility of software with the high performance of hardware by processing with very flexible high speed computinghardware fabricsplatforms like [[FPGA|field-programmable gate array]]s (FPGAs). The principal difference when compared to using ordinary [[microprocessor]]s is the ability to makeadd substantialcustom changescomputational toblocks theusing [[datapath]] itself in addition to the control flowFPGAs. On the other hand, the main difference from custom hardware, i.e. [[application-specific integrated circuit]]s (ASICs) is the possibility to adapt the hardware during runtime by "loading" a new circuit on the reconfigurable fabric, thus providing new computational blocks without the need to [[Semiconductor device fabrication|manufacture]] and add new [[Integrated circuit|chips]] to the existing system.

==History==

The concept of reconfigurable computing has existed since the 1960s, when [[Gerald Estrin]]'s paper proposed the concept of a computer made of a standard processor and an array of "reconfigurable" hardware.<ref name="Estrin2002">{{cite journal | last1 = Estrin | first1 = G | year = 2002 | title = Reconfigurable computer origins: the UCLA fixed-plus-variable (F+V) structure computer | url = | journal = IEEE Ann. Hist. Comput. | volume = 24 | issue = 4| pages = 3–9 | doi = 10.1109/MAHC.2002.1114865 | s2cid = 7923912 }}</ref><ref>

Estrin, G., "Organization of Computer Systems—The Fixed Plus Variable Structure Computer",

''Proc. Western Joint Computer Conf.'', Western Joint Computer Conference, New York, 1960, pp. 33–40.</ref> The main processor would control the behavior of the reconfigurable hardware. The latter would then be tailored to perform a specific task, such as [[image processing]] or [[pattern matching]], as quickly as a dedicated piece of hardware. Once the task was done, the hardware could be adjusted to do some other task. This resulted in a hybrid computer structure combining the flexibility of software with the speed of hardware.

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''Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines''

(FCCM '97, April 16–18, 1997), pp. 24–33.

</ref> Elixent, NGEN,<ref>{{Cite journal|lastlast1=McCaskill|firstfirst1=John S.|last2=Chorongiewski|first2=Harald|last3=Mekelburg|first3=Karsten|last4=Tangen|first4=Uwe|last5=Gemm|first5=Udo|date=1994-09-01|title=NGEN — Configurable computer hardware to simulate long-time self-organization of biopolymers|journal=Berichte der Bunsengesellschaft für Physikalische Chemie|language=en|volume=98|issue=9|pagespage=1114|doi=10.1002/bbpc.19940980906|issn=0005-9021}}</ref> Polyp,<ref>{{Cite book|title=Evolvable systems : from biology to hardware : second International Conference, ICES 98, Lausanne, Switzerland, September 23-25, 1998 : proceedings|date=1998|publisher=Springer|others=Sipper, Moshe., Mange, Daniel, 1940-, Pérez-Uribe, Andrés., International Conference on Evolvable Systems (2nd : 1998 : Lausanne, Switzerland)|isbn=978-35406495403-540-64954-0|___location=Berlin|oclc=39655211}}</ref> MereGen,<ref name=":1">{{Cite book|title=Coupling of biological and electronic systems : proceedings of the 2nd Caesarium, Bonn, November 1-3, 2000|date=2002|publisher=Springer|others=Hoffmann, K.-H. (Karl-Heinz)|isbn=978-35404369973-540-43699-7|___location=Berlin|oclc=49750250}}</ref> PACT XPP, Silicon Hive, Montium, Pleiades, Morphosys, and PiCoGA.<ref>Campi, F.; Toma, M.; Lodi, A.; Cappelli, A.; Canegallo, R.; Guerrieri, R., "A VLIW processor with reconfigurable instruction set for embedded applications", Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International, vol., no., pp. 250–491 vol. 1, 2003</ref> Such designs were feasible due to the constant progress of silicon technology that let complex designs be implemented on one chip. Some of these massively parallel reconfigurable computers were built primarily for special subdomains such as molecular evolution, neural or image processing. The world's first commercial reconfigurable computer, the Algotronix CHS2X4, was completed in 1991. It was not a commercial success, but was promising enough that [[Xilinx]] (the inventor of the [[FPGA|Field-Programmable Gate Array]], FPGA) bought the technology and hired the Algotronix staff.<ref>[http://www.algotronix.com/people/tom/album.html Algotronix History]</ref> Later machines enabled first demonstrations of scientific principles, such as the spontaneous spatial self-organisation of genetic coding with MereGen.<ref>{{Cite journal|lastlast1=Füchslin|firstfirst1=Rudolf M.|last2=McCaskill|first2=John S.|date=2001-07-31|title=Evolutionary self-organization of cell-free genetic coding|journal=Proceedings of the National Academy of Sciences|language=en|volume=98|issue=16|pages=9185–9190|doi=10.1073/pnas.151253198|issn=0027-8424|pmc=55395|pmid=11470896|bibcode=2001PNAS...98.9185F|doi-access=free}}</ref>

==Theories==

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===Tredennick's Classification===

{|class="wikitable" | align="right"

|+ ''Table 1: Nick Tredennick’sTredennick's Paradigm Classification Scheme''

|-

|bgcolor="#BBBBFF" colspan="2" | '''Early Historic Computers:'''

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| [[Flowware]] (data streams)

|}

The fundamental model of the reconfigurable computing machine paradigm, the data-stream-based [[anti machine]] is well illustrated by the differences to other machine paradigms that were introduced earlier, as shown by [[Nick Tredennick]]'s following classification scheme of computing paradigms (see "Table 1: Nick Tredennick’sTredennick's Paradigm Classification Scheme").<ref>N. Tredennick: The Case for Reconfigurable Computing; Microprocessor Report, Vol. 10 No. 10, 5 August 1996, pp 25–27.</ref>

===Hartenstein's Xputer===

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This heterogeneous systems technique is used in computing research and especially in [[supercomputing]].<ref name="Voros2009">N. Voros, R. Nikolaos, A. Rosti, M. Hübner (editors): Dynamic System Reconfiguration in Heterogeneous Platforms - The MORPHEUS Approach; Springer Verlag, 2009</ref>

A 2008 paper reported speed-up factors of more than 4 orders of magnitude and energy saving factors by up to almost 4 orders of magnitude.<ref name="Tarek2008">{{cite journal |title= The promise of high-performance reconfigurable computing |authorsauthor= Tarek El-Ghazawi |journal= IEEE Computer |volume= 41 |number=2 |pages= 69–76 |date= February 2008 |doi= 10.1109/MC.2008.65 |display-authors=etal|citeseerx= 10.1.1.208.4031 |s2cid= 14469864 }}</ref>

Some supercomputer firms offer heterogeneous processing blocks including FPGAs as accelerators.{{citation needed |date= August 2011}}

One research area is the twin-paradigm programming tool flow productivity obtained for such heterogeneous systems.<ref name="Esam2009">{{cite journal |author1= Esam El-Araby |author2= Ivan Gonzalez |author3= Tarek El-Ghazawi |title= Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing |journal= ACM Transactions on Reconfigurable Technology and Systems |volume= 1 |number= 4 |date= January 2009 |doi= 10.1145/1462586.1462590 |pages=1–23|s2cid= 10270587 }}</ref>

The US [[National Science Foundation]] has a center for high-performance reconfigurable computing (CHREC).<ref>{{cite web |title= NSF center for High-performance Reconfigurable Computing |work= official web site |url= http://www.chrec.org/ |accessdateaccess-date= August 19, 2011 }}</ref>

In April 2011 the fourth Many-core and Reconfigurable Supercomputing Conference was held in Europe.<ref>{{cite web |title=Many-Core and Reconfigurable Supercomputing Conference |year=2011 |work=official web site |url=http://www.mrsc2011.eu/ |archive-url=https://web.archive.org/web/20101012042408/http://www.mrsc2011.eu/ |url-status=dead |archive-date=October 12, 2010 |accessdateaccess-date=August 19, 2011 }}</ref>

Commercial high-performance reconfigurable computing systems are beginning to emerge with the announcement of [[IBM]] integrating FPGAs with its [[IBM POWERPower microprocessors|POWER]] processor.<ref>

{{cite web

| url = http://www.hpcwire.com/off-the-wire/altera-ibm-unveil-fpga-accelerated-power-systems/

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|publisher= HPCwire

|date= 2014-11-17

|accessdateaccess-date = 2014-12-14}}

</ref>

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[[Electronic hardware]], like [[software]], can be designed modularly, by creating subcomponents and then higher-level components to instantiate them. In many cases it is useful to be able to swap out one or several of these subcomponents while the FPGA is still operating.

Normally, reconfiguring an FPGA requires it to be held in reset while an external controller reloads a design onto it. Partial reconfiguration allows for critical parts of the design to continue operating while a controller either on the FPGA or off of it loads a partial design into a reconfigurable module. Partial reconfiguration also can be used to save space for multiple designs by only storing the partial designs that change between designs.<ref>{{cite journal |first1=Damian |last1=Wanta |first2=Waldemar T. |last2=Smolik |first3=Jacek |last3=Kryszyn |first4=Przemysław |last4=Wróblewski |first5=Mateusz |last5=Midura |title=A Run-Time Reconfiguration Method for an FPGA-Based Electrical Capacitance Tomography System |volume=11 |issue=4 |year=2022 |journal=Electronics |page=545 |doi=10.3390/electronics11040545|doi-access=free }}</ref>

A common example for when partial reconfiguration would be useful is the case of a communication device. If the device is controlling multiple connections, some of which require [[encryption]], it would be useful to be able to load different encryption cores without bringing the whole controller down.

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Partial reconfiguration is not supported on all FPGAs. A special software flow with emphasis on modular design is required. Typically the design modules are built along well defined boundaries inside the FPGA that require the design to be specially mapped to the internal hardware.

From the functionality of the design, partial reconfiguration can be divided into two groups:<ref>{{Cite book | last1 = Wiśniewski | first1 = Remigiusz | title = Synthesis of compositional microprogram control units for programmable devices | year = 2009 | publisher = University of Zielona Góra | ___location = Zielona Góra | isbn = 978-83-7481-293-1 | pagespage = 153 }}</ref>

* ''dynamic partial reconfiguration'', also known as an active partial reconfiguration - permits to change the part of the device while the rest of an FPGA is still running;

* ''static partial reconfiguration'' - the device is not active during the reconfiguration process. While the partial data is sent into the FPGA, the rest of the device is stopped (in the shutdown mode) and brought up after the configuration is completed.

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===Computer emulation ===

[[File:FPGARetrocomputing.jpg|An FPGA board is being used to recreate the Vector-06C computer.|thumb]]

With the advent of affordable FPGA boards, students' and hobbyists' projects seek to recreate [[vintage computerscomputer]]s or implement more novel architectures.<ref name="apple">{{cite web|url=https://www.cs.columbia.edu/~sedwards/apple2fpga/|title=Apple2 FPGA|accessdateaccess-date=6 Sep 2012

}}</ref><ref name="risc">{{cite web|url=http://www.inf.ethz.ch/personal/wirth/Articles/Miscellaneous/RISC.pdf |title=The Design of a RISC Architecture and its Implementation with an FPGA |author=Niklaus Wirth |accessdateaccess-date=6 Sep 2012 }}{{dead link|date=June 2016|bot=medic}}{{cbignore|bot=medic}}</ref><ref name="soc">{{cite web|author=Jan Gray

|url=http://www.fpgacpu.org/papers/soc-gr0040-paper.pdf|title=Designing a Simple FPGA-Optimized RISC CPU and System-on-a-Chip|accessdateaccess-date=6 Sep 2012

}}</ref> Such projects are built with reconfigurable hardware (FPGAs), and some devices support emulation of multiple vintage computers using a single reconfigurable hardware ([[C-One]]).

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=== Mitrionics ===

[[Mitrionics]] has developed a SDK that enables software written using a [[single assignment]] language to be compiled and executed on FPGA-based computers. The Mitrion-C software language and Mitrion processor enable software developers to write and execute applications on FPGA-based computers in the same manner as with other computing technologies, such as graphical processing units (“GPUs”"GPUs"), cell-based processors, parallel processing units (“PPUs”"PPUs"), multi-core CPUs, and traditional single-core CPU clusters. (out of business)

=== National Instruments ===

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=== Intel ===

[[Intel]]<ref name="intel_altera">{{cite web |url=https://newsroom.intel.com/news-releases/intel-completes-acquisition-of-altera/ |title=Intel completes acquisition of Altera |work=Intel Newsroom |access-date=15 November 2016}}</ref> supports partial reconfiguration of their FPGA devices on 28&nbsp;nm devices such as Stratix V,<ref name="stratixv_pr">{{cite web |url=https://www.altera.com/products/fpga/features/stxv-part-reconfig.html |title=Stratix V FPGAs: Ultimate Flexibility Through Partial and Dynamic Reconfiguration |access-date=15 November 2016}}</ref> and on the 20&nbsp;nm Arria 10 devices.<ref name="arria10_pr">{{cite web |url=https://www.altera.com/products/design-software/fpga-design/quartus-prime/features.html |title=Intel Quartus Prime Software Productivity Tools and Features |access-date=15 November 2016}}</ref> The Intel FPGA partial reconfiguration flow for Arria 10 is based on the hierarchical design methodology in the Quartus Prime Pro software where users create physical partitions of the FPGA that can be reconfigured<ref name="arria10_pr_docs">{{cite web |url=https://www.altera.com/en_US/pdfs/literature/hb/qts/qts-qps-5v1.pdf |title=Quartus Prime Standard Edition Handbook Volume 1: Design and Synthesis |publisher=Intel |access-date=15 November 2016 |pagepages=4–1}}</ref> at runtime while the remainder of the design continues to operate. The Quartus Prime Pro software also support hierarchical partial reconfiguration and simulation of partial reconfiguration.

== Classification of systems ==

{{RefimproveMore citations needed section|date=January 2015}}

{{Original research section|date=January 2015}}

As an emerging field, classifications of reconfigurable architectures are still being developed and refined as new architectures are developed; no unifying taxonomy has been suggested to date. However, several recurring parameters can be used to classify these systems.

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===Rate of reconfiguration===

Configuration of these reconfigurable systems can happen at deployment time, between execution phases or during execution. In a typical reconfigurable system, a bit stream is used to program the device at deployment time. Fine grained systems by their own nature require greater configuration time than more coarse-grained architectures due to more elements needing to be addressed and programmed. Therefore, more coarse-grained architectures gain from potential lower energy requirements, as less information is transferred and utilised. Intuitively, the slower the rate of reconfiguration the smaller the energypower consumption as the associated energy cost of reconfiguration are amortised over a longer period of time. Partial re-configuration aims to allow part of the device to be reprogrammed while another part is still performing active computation. Partial re-configuration allows smaller reconfigurable bit streams thus not wasting energy on transmitting redundant information in the bit stream. Compression of the bit stream is possible but careful analysis is to be carried out to ensure that the energy saved by using smaller bit streams is not outweighed by the computation needed to decompress the data.

===Host coupling===

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== Challenges for operating systems ==

One of the key challenges for reconfigurable computing is to enable higher design productivity and provide an easier way to use reconfigurable computing systems for users that are unfamiliar with the underlying concepts. One way of doing this is to provide standardization and abstraction, usually supported and enforced by an operating system.<ref name=":0">{{Cite journal|lastlast1=Eckert|firstfirst1=Marcel|last2=Meyer|first2=Dominik|last3=Haase|first3=Jan|last4=Klauer|first4=Bernd|date=2016-11-30|title=Operating System Concepts for Reconfigurable Computing: Review and Survey|journal=International Journal of Reconfigurable Computing|language=en|volume=2016|pages=1–11|doi=10.1155/2016/2478907|issn=1687-7195|doi-access=free}} [[File:CC-BY icon.svg|50px]] This article contains quotations from this source, which is available under the [https://creativecommons.org/licenses/by/4.0/ Creative Commons Attribution 4.0 International (CC BY 4.0)] license.</ref>

One of the major tasks of an operating system is to hide the hardware and present programs (and their programmers) with nice, clean, elegant, and consistent abstractions to work with instead. In other words, the two main tasks of an operating system are abstraction and [[Resource management (computing)|resource management]].<ref name=":0" />

Abstraction is a powerful mechanism to handle complex and different (hardware) tasks in a well-defined and common manner. One of the most elementary OS abstractions is a process. A process is a running application that has the perception (provided by the OS) that it is running on its own on the underlying virtual hardware. This can be relaxed by the concept of threads, allowing different tasks to run concurrently on this virtual hardware to exploit task level parallelism. To allow different processes and threads to coordinate their work, communication and synchronization methods have to be provided by the OS.<ref name=":0" />

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* S. Hauck and A. DeHon, ''Reconfigurable Computing: The Theory and Practice of FPGA-Based Computing'', [[Morgan Kaufmann]], 2008.

* J. Henkel, S. Parameswaran (editors): Designing Embedded Processors. A Low Power Perspective; Springer Verlag, March 2007

* J. Teich (editor) et al.: Reconfigurable Computing Systems. Special Topic Issue of Journal ''it — Information Technology'', Oldenbourg Verlag, Munich. [https://archive.istoday/20130101235837/http://www.atypon-link.com/OLD/toc/itit/49/3 Vol. 49(2007) Issue 3]

* T.J. Todman, G.A. Constantinides, S.J.E. Wilton, O. Mencer, W. Luk and P.Y.K. Cheung, "Reconfigurable Computing: Architectures and Design Methods", IEEE Proceedings: Computer & Digital Techniques, Vol. 152, No. 2, March 2005, pp.&nbsp;193–208.

* A. Zomaya (editor): Handbook of Nature-Inspired and Innovative Computing: Integrating Classical Models with Emerging Technologies; Springer Verlag, 2006

* J. M. Arnold and D. A. Buell, "VHDL programming on Splash 2," in More FPGAs, Will Moore and Wayne Luk, editors, Abingdon EE & CS Books, Oxford, England, 1994, pp.&nbsp;182–191. (Proceedings, International Workshop on Field-Programmable Logic, Oxford, 1993.)

* J. M. Arnold, D. A. Buell, D. Hoang, D. V. Pryor, N. Shirazi, M. R. Thistle, "Splash 2 and its applications, "Proceedings, International Conference on Computer Design, Cambridge, 1993, pp. 482–486.

* D. A. Buell and Kenneth L. Pocek, "Custom computing machines: An introduction," [[The Journal of Supercomputing]], v. 9, 1995, pp.&nbsp;219–230.

==External links==

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* [https://scale.engin.brown.edu/classes/EN2911XF14/ Lectures on Reconfigurable Computing at Brown University]

* [httphttps://wwwweb.archive.org/web/20160306094104/http://vlsi-world.com/content/view/48/47/ Introduction to Dynamic Partial Reconfiguration]

* [http://www12.informatik.uni-erlangen.de/research/recobus/ ReCoBus-Builder project for easily implementing complex reconfigurable systems]

* [http://www.dresd.org/ DRESD (Dynamic Reconfigurability in Embedded System Design) research project] {{Webarchive|url=https://web.archive.org/web/20080715053642/http://www.dresd.org/ |date=2008-07-15 }}

{{Programmable Logic}}

{{DEFAULTSORT:Reconfigurable Computing}}

[[Category:Digital electronics]]

[[Category:Reconfigurable computing| ]]

[[Category:Digital electronics]]