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Line 1: {{Short description\|Microprocessor with more than one processing unit}} {{See also\|Multiprocessor system architecture}} {{Redirect-distinguish\|Dual Core~~\|the nerdcore duo~~\|Dual Core (hip hop duo)}} [[File:Dual Core Generic.svg\|thumb\|Diagram of a generic dual-core processor with CPU-local level-1 caches and a shared, on-die level-2 cache]] [[File:E6750bs8.jpg\|thumb\|An [[Intel]] [[Core 2 Duo]] E6750 dual-core processor]] [[File:Athlon64x2-6400plus.jpg\|thumb\|An [[AMD]] [[Athlon 64 X2\|Athlon X2 6400+]] dual-core processor]] A '''multi-core processor''' ('''MCP''') is a [[microprocessor]] on a single [[integrated circuit]] (IC) with two or more separate [[~~Central~~central processing unit~~\|processing units~~]]s (CPUs), called ''cores'' to emphasize their multiplicity (for example, ~~each~~''dual-core'' ofor ~~which~~''quad-core''). Each core reads and executes [[Instruction set\|program instructions]].,<ref>{{cite web\|url= http://searchdatacenter.techtarget.com/sDefinition/0,,sid80_gci1015740,00.html\|publisher= TechTarget\|title= Definition: multi-core processor\|last= Rouse\|first= Margaret\|date= March 27, 2007\|access-date= March 6, 2013\|url-status= dead\|archive-url= https://web.archive.org/web/20100805052158/http://searchdatacenter.techtarget.com/sDefinition/0,,sid80_gci1015740,00.html\|archive-date= August 5, 2010}}</ref> ~~The instructions are~~specifically ordinary [[Instruction set\|CPU instructions]] (such as add, move data, and branch). ~~but~~However, the ~~single processor~~MCP can run instructions on separate cores at the same time, increasing overall speed for programs that support [[Multithreading (computer architecture)\|multithreading]] or other [[parallel computing]] techniques.<ref>{{cite web\|url=http://www.csa.com/discoveryguides/multicore/review.pdf\|title=Multicore Processors – A Necessity\|last=Schauer\|first=Bryan\|archive-url=https://web.archive.org/web/20111125035151/http://www.csa.com/discoveryguides/multicore/review.pdf\|archive-date=2011-11-25\|url-status=dead}}</ref> Manufacturers typically integrate the cores onto a single ~~integrated circuit~~IC [[Die (integrated circuit)\|die]], (known as a ''chip multiprocessor'' or (CMP), or onto multiple dies in a single [[Chip carrier\|chip package]]. As ~~The~~of ~~microprocessors~~2024, ~~currently~~the microprocessors used in almost all new [[personal ~~computers~~computer]]s are multi-core. A multi-core processor implements [[multiprocessing]] in a single physical package. Designers may couple cores in a multi-core device tightly or loosely. For example, cores may or may not share [[CPU cache\|caches]], and they may implement [[message passing]] or [[shared memory\|shared-memory]] inter-core communication methods. Common [[network topology\|network topologies]] used to interconnect cores include [[bus network\|bus]], [[ring network\|ring]], two-dimensional [[mesh networking\|mesh]], and [[crossbar switch\|crossbar]]. Homogeneous multi-core systems include only identical cores; [[heterogeneous computing\|heterogeneous]] multi-core systems have cores that are not identical (e.g. [[ARM big.LITTLE\|big.LITTLE]] have heterogeneous cores that share the same [[Instruction set architecture\|instruction set]], while [[AMD Accelerated Processing Unit]]s have cores that do not share the same instruction set). Just as with single-processor systems, cores in multi-core systems may implement architectures such as [[Very long instruction word\|VLIW]], [[Superscalar processor\|superscalar]], [[Vector processor\|vector]], or [[Multithreading (computer architecture)\|multithreading]]. Line 15 ⟶ 16: \|url = http://www.futurechips.org/tips-for-power-coders/parallel-programming.html \|archive-url = https://web.archive.org/web/20110529133159/http://www.futurechips.org/tips-for-power-coders/parallel-programming.html \|url-status = dead \|archive-date = May 29, 2011 \|title = What makes parallel programming hard? Line 27 ⟶ 28: The parallelization of software is a significant ongoing topic of research. Cointegration of multiprocessor applications provides flexibility in network architecture design. Adaptability within parallel models is an additional feature of systems utilizing these protocols.<ref>{{cite journal \|last1=Duran \|first1=A \|title=Ompss: a proposal for programming heterogeneous multi-core architectures \|journal=Parallel Processing Letters \|date=2011 \|volume=21 \|issue=2\|pages=173–193 \|doi=10.1142/S0129626411000151 }}</ref> In the consumer market, dual-core processors (that is, microprocessors with two units) started becoming commonplace on personal computers in the late 2000s.<ref>{{Cite web \|title=Definition of dual core \|url=https://www.pcmag.com/encyclopedia/term/dual-core \|access-date=2023-10-27 \|website=PCMAG \|language=en}}</ref> In the early 2010s, quad-core processors were also being adopted in that era for higher-end systems before becoming standard by the mid 2010s. In the late 2010s, hexa-core (six cores) started entering the mainstream<ref>{{Cite web \|title=Intel taking its six-core processors mainstream in 2018 with Coffee Lake family \|url=https://www.zdnet.com/article/intel-taking-its-six-core-processors-mainstream-in-2018-with-coffee-lake-family/ \|access-date=2023-10-27 \|website=ZDNET \|language=en}}</ref> and since the early 2020s has overtaken quad-core in many spaces.<ref>{{Cite news \|author1=Alan Dexter \|date=2022-04-05 \|title=Six-core CPUs are now more popular than quad-core chips on Steam \|url=https://www.pcgamer.com/six-core-cpus-are-now-more-popular-than-quad-core-chips-on-steam/ \|access-date=2024-05-22 \|work=PC Gamer \|language=en}}</ref> ==Terminology== Line 33 ⟶ 36: In contrast to multi-core systems, the term ''multi-CPU'' refers to multiple physically separate processing-units (which often contain special circuitry to facilitate communication between each other). The terms ''[[Manycore processor\|many-core]]'' and ''massively multi-core'' are sometimes used to describe multi-core architectures with an especially high number of cores (tens to thousands<ref>{{cite web\|url=https://fuse.wikichip.org/news/191/the-2048-core-pezy-sc2-sets-a-green500-record/\|title=The 2,048-core PEZY-SC2 sets a Green500 record\|last=Schor\|first=David\|publisher=WikiChip\|date=November 2017}}</ref>).<ref>{{cite book\|url=https://books.google.com/books?id=pSxa_anfiG0C&q=several+tens&pg=PA3\|title=Programming Many-Core Chips\|last=Vajda\|first=András\|page=3\|publisher=Springer\|isbn=978-1-4419-9739-5\|date=2011-06-10}}</ref> Some systems use many [[soft microprocessor]] cores placed on a single [[Field-programmable gate array\|FPGA]]. Each "core" can be considered a "[[semiconductor intellectual property core]]" as well as a CPU core.{{Citation needed\|date=February 2011}} Line 39 ⟶ 42: ==Development== While manufacturing technology improves, reducing the size of individual gates, physical limits of [[semiconductor]]-based [[microelectronics]] have become a major design concern. These physical limitations can cause significant heat dissipation and data synchronization problems. Various other methods are used to improve CPU performance. Some ''[[instruction-level parallelism]]'' (ILP) methods such as [[superscalar]] [[instruction pipelining\|pipelining]] are suitable for many applications, but are inefficient for others that contain difficult-to-predict code. Many applications are better suited to ''[[thread-level parallelism]]'' (TLP) methods, and multiple independent CPUs are commonly used to increase a system's overall TLP. A combination of increased available space (due to refined manufacturing processes) and the demand for increased TLP led to the development of multi-core CPUs. ===Early innovations: the Stanford Hydra project=== In the 1990s, [[Kunle Olukotun]] led the Stanford Hydra Chip Multiprocessor (CMP) research project. This initiative was among the first to demonstrate the viability of integrating multiple processors on a single chip, a concept that laid the groundwork for today's multicore processors. The Hydra project introduced support for thread-level speculation (TLS), enabling more efficient parallel execution of programs. ===Commercial incentives=== Several business motives drive the development of multi-core architectures. For decades, it was possible to improve performance of a CPU by shrinking the area of the integrated circuit (IC), which reduced the cost per device on the IC. Alternatively, for the same circuit area, more transistors could be used in the design, which increased functionality, especially for [[complex instruction set computing]] (CISC) architectures. [[Clock rate]]s also increased by orders of magnitude in the decades of the late 20th century, from several megahertz in the 1980s to several gigahertz in the early 2000s. As the rate of clock speed improvements slowed, increased use of parallel computing in the form of multi-core processors has been pursued to improve overall processing performance. Multiple cores were used on the same CPU chip, which could then lead to better sales of CPU chips with two or more cores. For example, [[Intel]] has produced a 48-core processor for research in cloud computing; each core has an [[x86]] architecture.<ref>{{cite web\|title=Intel Shows 48-core x86 Processor as Single-chip Cloud Computer\|url=http://www.pcper.com/reviews/Processors/Intel-Shows-48-core-x86-Processor-Single-chip-Cloud-Computer\|last=Shrout\|first=Ryan\|date=December 2, 2009\|access-date=May 17, 2015\|url-status=live\|archive-url=https://web.archive.org/web/20160105080008/http://www.pcper.com/reviews/Processors/Intel-Shows-48-core-x86-Processor-Single-chip-Cloud-Computer\|archive-date=January 5, 2016}}</ref><ref>{{cite news\|url=http://news.bbc.co.uk/2/hi/technology/8392392.stm\|title=Intel unveils 48-core cloud computing silicon chip\|publisher=BBC\|date=December 3, 2009\|access-date=March 6, 2013\|url-status=live\|archive-url=https://web.archive.org/web/20121206054225/http://news.bbc.co.uk/2/hi/technology/8392392.stm\|archive-date=December 6, 2012}}</ref> ===Technical factors=== Line 62 ⟶ 68: Assuming that the die can physically fit into the package, multi-core CPU designs require much less [[printed circuit board]] (PCB) space than do multi-chip [[symmetric multiprocessing\|SMP]] designs. Also, a dual-core processor uses slightly less power than two coupled single-core processors, principally because of the decreased power required to drive signals external to the chip. Furthermore, the cores share some circuitry, like the L2 cache and the interface to the [[front-side bus]] (FSB). In terms of competing technologies for the available silicon die area, multi-core design can make use of proven CPU core library designs and produce a product with lower risk of design error than devising a new wider-core design. Also, adding more cache suffers from diminishing returns. Multi-core chips also allow higher performance at lower energy. This can be a big factor in mobile devices that operate on batteries. Since each core in a multi-core CPU is generally more energy-efficient, the chip becomes more efficient than having a single large monolithic core. This allows higher performance with less energy. A challenge in this, however, is the additional overhead of writing parallel code.<ref>{{cite web\|title=Q & A: Do multicores save energy? Not really.\|url=http://www.futurechips.org/chip-design-for-all/a-multicore-save-energy.html\|last=Suleman\|first=Aater\|date=May 19, 2011\|access-date=March 6, 2013\|url-status=dead\|archive-url=https://web.archive.org/web/20121216051010/http://www.futurechips.org/chip-design-for-all/a-multicore-save-energy.html\|archive-date=December 16, 2012}}</ref> ===Disadvantages=== Maximizing the usage of the computing resources provided by multi-core processors requires adjustments both to the [[operating system]] (OS) support and to existing application software. Also, the ability of multi-core processors to increase application performance depends on the use of multiple threads within applications. Integration of a multi-core chip can lower the chip production yields. They are also more difficult to manage thermally than lower-density single-core designs. Intel has partially countered this first problem by creating its quad-core designs by combining two dual-core ones on a single die with a unified cache, hence any two working dual-core dies can be used, as opposed to producing four cores on a single die and requiring all four to work to produce a quad-core CPU. From an architectural point of view, ultimately, single CPU designs may make better use of the silicon surface area than multiprocessing cores, so a development commitment to this architecture may carry the risk of obsolescence. Finally, raw processing power is not the only constraint on system performance. Two processing cores sharing the same system bus and memory bandwidth limits the real-world performance advantage. In a 2009 report, Dr Jun Ni showed that if a single core is close to being memory-bandwidth limited, then going to dual-core might give 30% to 70% improvement; if memory bandwidth is not a problem, then a 90% improvement can be expected; however, [[Amdahl's law]] makes this claim dubious.<ref name="Enabling Technology of Multi-core Processing for Medical Imaging">{{cite web\|last=Ni\|first=Jun\|title=Enabling Technology of Multi-core Computing for Medical Imaging\|url=http://www.uiowa.edu/mihpclab/presentations/staffPresentations/2009_12_22_Multi-core%20Programming%20for%20Medical%20Imaging.pdf\|access-date=17 February 2013\|archive-url=https://web.archive.org/web/20100705213827/http://www.uiowa.edu/mihpclab/presentations/staffPresentations/2009_12_22_Multi-core%20Programming%20for%20Medical%20Imaging.pdf\|archive-date=2010-07-05\|url-status=dead}}</ref> It would be possible for an application that used two CPUs to end up running faster on a single-core one if communication between the CPUs was the limiting factor, which would count as more than 100% improvement. ==Hardware== ===Trends=== The trend in processor development has been towards an ever-increasing number of cores, as processors with hundreds or even thousands of cores become theoretically possible.<ref>{{cite web\|last1=Clark\|first1=Jack\|title=Intel: Why a 1,000-core chip is feasible\|url=~~http~~https://www.zdnet.com/article/intel-why-a-1000-core-chip-is-feasible/\|website=ZDNet\|access-date=6 August 2015\|url-status=live\|archive-url=https://web.archive.org/web/20150806181915/http://www.zdnet.com/article/intel-why-a-1000-core-chip-is-feasible/\|archive-date=6 August 2015}}</ref> In addition, multi-core chips mixed with [[simultaneous multithreading]], memory-on-chip, and special-purpose [[heterogeneous computing\|"heterogeneous"]] (or asymmetric) cores promise further performance and efficiency gains, especially in processing multimedia, recognition and networking applications. For example, a [[ARM big.LITTLE\|big.LITTLE]] core includes a high-performance core (called 'big') and a low-power core (called 'LITTLE'). There is also a trend towards improving energy-efficiency by focusing on performance-per-watt with advanced fine-grain or ultra fine-grain [[power management]] and dynamic [[dynamic voltage scaling\|voltage]] and [[dynamic frequency scaling\|frequency scaling]] (i.e. [[laptop]] computers and [[portable media player]]s). Chips designed from the outset for a large number of cores (rather than having evolved from single core designs) are sometimes referred to as [[Manycore processor\|manycore]] designs, emphasising qualitative differences. ===Architecture=== The composition and balance of the cores in multi-core architecture show great variety. Some architectures use one core design repeated consistently ("homogeneous"), while others use a mixture of different cores, each optimized for a different, "[[heterogeneous computing\|heterogeneous]]" role. How multiple cores are implemented and integrated significantly affects both the developer's programming skills and the consumer's expectations of apps and interactivity versus the device.<ref>{{cite web \|url= https://www.gizbot.com/mobile/features/these-5-myths-about-the-octa-core-phones-are-actually-true-034569.html \|website= Giz Bot \|first= Chakri \|last= Kudikala \|date= Aug 27, 2016 \|title= These 5 Myths About the Octa-Core Phones Are Actually True }}</ref> A device advertised as being octa-core will only have independent cores if advertised as ''True Octa-core'', or similar styling, as opposed to being merely two sets of quad-cores each with fixed clock speeds.<ref>{{cite press release \|url= https://www.mediatek.com/news-events/press-releases/mediatek-launches-mt6592-true-octa-core-mobile-platform \|title= MediaTek Launches MT6592 True Octa-Core Mobile Platform \|date= November 20, 2013 \|publisher= MediaTek \|archive-url= https://web.archive.org/web/20201029195636/https://www.mediatek.com/news-events/press-releases/mediatek-launches-mt6592-true-octa-core-mobile-platform \|archive-date= October 29, 2020 \|url-status= dead}}</ref><ref>{{cite web \|url= https://www.samsung.com/global/galaxy/what-is/octa-core-processor/ \|title= What is an Octa-core processor \|publisher= Samsung \|quote= Galaxy smartphones run on either Octa-core (2.3GHz Quad + 1.6GHz Quad) or Quad-core (2.15GHz + 1.6GHz Dual) processors \|archive-url=https://web.archive.org/web/20220117192737/https://www.samsung.com/global/galaxy/what-is/octa-core-processor/ \|archive-date=January 17, 2022 \|url-status=dead}}</ref> The article "CPU designers debate multi-core future" by Rick Merritt, EE Times 2008,<ref>{{cite web\|url=~~http~~https://www.eetimes.com~~/electronics-news/4076123~~/CPU-designers-debate-multi-core-future/\|title=CPU designers debate multi-core future\|last=Merritt\|first=Rick\|publisher=[[EE Times]]\|date=February 6, 2008\|access-date=~~March 6, 2013\|url-status=live\|archive-url=https://web.archive.org/web/20121114020257/http://eetimes.com/electronics-news/4076123/CPU-designers-debate-multi-core-future\|archive-date=November~~October 1421, ~~2012~~2023}}</ref> includes these comments: {{blockquote\|Chuck Moore<!-- No, this is not the Forth Chuck Moore, it's the Chuck Moore from IBM and then AMD - http://www.stanford.edu/class/ee380/Abstracts/080604.html --> [...] suggested computers should be like cellphones, using a variety of specialty cores to run modular software scheduled by a high-level applications programming interface. Line 93 ⟶ 99: Given the increasing emphasis on multi-core chip design, stemming from the grave thermal and power consumption problems posed by any further significant increase in processor clock speeds, the extent to which software can be multithreaded to take advantage of these new chips is likely to be the single greatest constraint on computer performance in the future. If developers are unable to design software to fully exploit the resources provided by multiple cores, then they will ultimately reach an insurmountable performance ceiling. The telecommunications market had been one of the first that needed a new design of parallel datapath packet processing because there was a very quick adoption of these multiple-core processors for the datapath and the control plane. These MPUs are going to replace<ref>{{cite web\|url=http://multicorepacketprocessing.com/\|title=Multicore Packet Processing Forum\|url-status=usurped\|archive-url=https://web.archive.org/web/20091221035434/http://www.multicorepacketprocessing.com/\|archive-date=2009-12-21}}</ref> the traditional Network Processors that were based on proprietary [[microcode]] or [[picocode]]. [[Parallel programming]] techniques can benefit from multiple cores directly. Some existing [[parallel programming model]]s such as [[Cilk Plus]], [[OpenMP]], [[OpenHMPP]], [[Algorithmic skeleton#FastFlow\|FastFlow]], Skandium, [[Message Passing Interface\|MPI]], and [[Erlang (programming language)\|Erlang]] can be used on multi-core platforms. Intel introduced a new abstraction for C++ parallelism called [[Threading Building Blocks\|TBB]]. Other research efforts include the [[Sieve C++ Parallel Programming System\|Codeplay Sieve System]], Cray's [[Chapel (programming language)\|Chapel]], Sun's [[Fortress programming language\|Fortress]], and IBM's [[X10 (programming language)\|X10]]. Line 150 ⟶ 156: == Digital signal processing == In [[digital signal processing]] the same trend applies: [[Texas Instruments]] has the three-core TMS320C6488 and four-core TMS320C5441, [[Freescale]] the four-core MSC8144 and six-core MSC8156 (and both have stated they are working on eight-core successors). Newer entries include the Storm-1 family from [https://web.archive.org/web/20101210220716/http://www.streamprocessors.com/streamprocessors/Home.html Stream Processors, Inc] with 40 and 80 general purpose ALUs per chip, all programmable in C as a SIMD engine and [[Picochip]] with 300 processors on a single die, focused on communication applications. == Heterogeneous systems == Line 178 ⟶ 184: [[Ryzen]], dual-, quad-, 6-, 8-, 12-, 16-, 24-, 32-, and 64-core desktop, mobile, and embedded platform processors. [[Epyc]], quad-, 8-, 12-, 16-, 24-, 32-, and 64-core server and embedded processors. ** [[Radeon]] and [[AMD FireStream\|FireStream]] ~~[[Graphics processing unit\|~~GPU]]/[[GPGPU]]. * [[Analog Devices]] [[Blackfin]] BF561, a symmetrical dual-core processor * [[ARM architecture\|ARM]] [[MPCore]] is a fully synthesizable multi-core container for [[ARM11 MPCore]] and [[ARM Cortex-A9 MPCore]] processor cores, intended for high-performance embedded and entertainment applications. * [[ASOCS]] ModemX, up to 128 cores, wireless applications. Line 189 ⟶ 195: SiByte SB1250, SB1255, SB1455 BCM2836, BCM2837, BCM2710 and BCM2711 quad-core ARM SoC (designed for different [[Raspberry Pi]] models) * [[Cadence Design Systems]] [[Tensilica]] Xtensa LX6, available in a dual-core configuration in [[Espressif Systems]]'s [[ESP32]] * [[ClearSpeed]] ** CSX700, 192-core processor, released in 2008 (32/64-bit floating point; Integer ALU). * Cradle Technologies CT3400 and CT3600, both multi-core DSPs. * [[Cavium Networks]] Octeon, a 32-core [[MIPS architecture\|MIPS]] [[Manycore ~~processing unit~~processior\|MPU]]. * [http://www.coherentlogix.com/ Coherent Logix] [http://www.coherentlogix.com/products/hyperx-processors/ hx3100 Processor], a 100-core DSP/GPP processor. * [[Freescale Semiconductor]] QorIQ series processors, up to 8 cores, [[Power ISA]] [[Manycore ~~processing unit~~processor\|MPU]]. * [[Hewlett-Packard]] [[PA-8800]] and [[PA-8900]], dual core [[PA-RISC]] processors. * [[IBM]] [[POWER4]], a dual-core [[PowerPC]] processor, released in 2001. Line 206 ⟶ 212: [[Power10]], a 15 or 30-core PowerPC processor, released in 2021. [[PowerPC 970]]MP, a dual-core PowerPC processor, used in the Apple [[Power Mac G5]]. [[Xenon (processor)\|Xenon]], a triple-core, [[Simultaneous multithreading\|SMT]]-capable, PowerPC microprocessor used in the [[Microsoft]] [[Xbox 360]] game console. [[IBM z10\|z10]], a quad-core [[z/Architecture]] processor, released in 2008. [[IBM z196\|z196]], a quad-core z/Architecture processor, released in 2010. Line 220 ⟶ 226: [[Intel Atom\|Atom]], single, dual-core, quad-core, 8-, 12-, and 16-core processors for [[Netbook\|netbooks]], [[Nettop\|nettops]], embedded applications, and [[Mobile Internet device\|mobile internet devices]] (MIDs).<ref>{{Cite web\|url=https://ark.intel.com/content/www/us/en/ark/products/series/97941/intel-atom-processor-c-series.html\|title=Intel® Atom™ Processor C Series Product Specifications\|website=ark.intel.com\|language=en\|access-date=2019-05-04}}</ref> [[Atom (system on chip)\|Atom SoC (system on a chip)]], single-core, dual-core, and quad-core processors for smartphones and tablets.<ref>{{Cite web\|url=https://ark.intel.com/content/www/us/en/ark/products/series/76761/intel-atom-processor-z-series.html\|title=Intel® Atom™ Processor Z Series Product Specifications\|website=ark.intel.com\|language=en\|access-date=2019-05-04}}</ref> [[Celeron]], the first dual-core (and, later, quad-core) processor for the budget/entry-level market.<ref>{{cite news\| url=http://www.xbitlabs.com/news/cpu/display/20071011171900.html\| title=Intel Preps Dual-Core Celeron Processors\| date=October 11, 2007\| access-date=November 12, 2007\| url-status=dead\| archive-url=https://web.archive.org/web/20071104025126/http://www.xbitlabs.com/news/cpu/display/20071011171900.html\| archive-date=November 4, 2007\| df=dmy-all}}</ref><ref>{{Cite web\|url=https://ark.intel.com/content/www/us/en/ark/products/series/77504/intel-celeron-processor-j-series.html\|title=Intel® Celeron® Processor J Series Product Specifications\|website=ark.intel.com\|language=en\|access-date=2019-05-04}}</ref> [[Core Duo]], a dual-core processor.<ref>{{Cite web\|url=https://ark.intel.com/content/www/us/en/ark/products/codename/2673/yonah.html\|title=Products formerly Yonah\|website=ark.intel.com\|access-date=2019-05-04}}</ref> [[Core 2 Duo]], a dual-core processor.<ref>{{Cite web\|url=https://ark.intel.com/content/www/us/en/ark/products/codename/2680/conroe.html\|title=Products formerly Conroe\|website=ark.intel.com\|access-date=2019-05-04}}</ref> Line 227 ⟶ 233: [[Itanium]], single, dual-core, quad-core, and 8-core processors.<ref>{{Cite web\|url=https://ark.intel.com/content/www/us/en/ark/products/series/451/intel-itanium-processor.html\|title=Intel® Itanium® Processor Product Specifications\|website=ark.intel.com\|language=en\|access-date=2019-05-04}}</ref> [[Pentium]], single, dual-core, and quad-core processors for the entry-level market.<ref>{{Cite web\|url=https://ark.intel.com/content/www/us/en/ark/products/series/91594/intel-pentium-processor-d-series.html\|title=Intel® Pentium® Processor D Series Product Specifications\|website=ark.intel.com\|language=en\|access-date=2019-05-04}}</ref> [[Teraflops Research Chip]] (Polaris), a 3.16 GHz, 80-core processor prototype, which the company originally stated would be released by 2011.<ref>{{cite web\|url=http://techfreep.com/intel-80-cores-by-2011.htm\|title=Intel: 80 Cores by 2011\|last=Zazaian\|first=Mike\|date=September 26, 2006\|url-status=dead\|archive-url=https://web.archive.org/web/20061109031744/http://techfreep.com/intel-80-cores-by-2011.htm\|archive-date=2006-11-09\|access-date=2006-09-28}}</ref> [[Xeon]] dual-, quad-, 6-, 8-, 10-, 12-, 14-, 15-, 16-, 18-, 20-, 22-, 24-, 26-, 28-, 32-, 48-, and 56-core processors.<ref>{{cite web\|url=http://techreport.com/news/26056/intel-releases-15-core-xeon-e7-v2-processor\|title=Intel releases 15-core Xeon E7 v2 processor\|last=Kowaliski\|first=Cyril\|date=February 18, 2014\|url-status=live\|archive-url=https://web.archive.org/web/20141011023442/http://techreport.com/news/26056/intel-releases-15-core-xeon-e7-v2-processor\|archive-date=2014-10-11}}</ref><ref>{{cite web\|url=http://ark.intel.com/products/family/78585/Intel-Xeon-Processor-E7-v3-Family\|title=Intel Xeon Processor E7 v3 Family\|publisher=[[Intel]]\|url-status=live\|archive-url=https://web.archive.org/web/20150707122129/http://ark.intel.com/products/family/78585/Intel-Xeon-Processor-E7-v3-Family\|archive-date=2015-07-07}}</ref><ref>{{cite web\|url=http://ark.intel.com/products/family/78584/Intel-Xeon-Processor-E7-v2-Family\|title=Intel Xeon Processor E7 v2 Family\|work=Intel® ARK (Product Specs) \|publisher=Intel\|url-status=live\|archive-url=https://web.archive.org/web/20150707120021/http://ark.intel.com/products/family/78584/Intel-Xeon-Processor-E7-v2-Family\|archive-date=2015-07-07}}</ref><ref>{{cite web\|url=http://ark.intel.com/products/family/78580/Intel-Xeon-Processor-E3-v2-Family\|title=Intel Xeon Processor E3 v2 Family\|work=Intel® ARK (Product Specs) \|publisher=Intel\|url-status=live\|archive-url=https://web.archive.org/web/20150707120142/http://ark.intel.com/products/family/78580/Intel-Xeon-Processor-E3-v2-Family\|archive-date=2015-07-07}}</ref><ref>{{Cite web\|url=https://www.techspot.com/news/79481-intel-announces-xeon-platinum-9200-series-cpus-up.html\|title=Intel shows off Xeon Platinum CPU with up to 56 cores and 112 threads\|website=TechSpot\|date=2 April 2019 \|language=en-US\|access-date=2019-05-04}}</ref><ref>{{Cite web\|url=https://www.intel.com/content/www/us/en/products/docs/processors/xeon/2nd-gen-xeon-scalable-processors-brief.html\|title=2nd Gen Intel® Xeon® Scalable Processors Brief\|last=PDF\|first=Download\|website=Intel\|language=en\|access-date=2019-05-04}}</ref> [[Intel MIC#Xeon Phi\|Xeon Phi]] 57-, 60-, 61-, 64-, 68-, and 72-core processors.<ref>{{Cite web\|url=https://ark.intel.com/content/www/us/en/ark/products/series/92649/intel-xeon-phi-x100-product-family.html\|title=Intel® Xeon Phi™ x100 Product Family Product Specifications\|website=ark.intel.com\|language=en\|access-date=2019-05-04}}</ref><ref>{{Cite web\|url=https://ark.intel.com/content/www/us/en/ark/products/series/132784/intel-xeon-phi-72x5-processor-family.html\|title=Intel® Xeon Phi™ 72x5 Processor Family Product Specifications\|website=ark.intel.com\|language=en\|access-date=2019-05-04}}</ref> * IntellaSys SEAforth 40C18, a 40-core processor.<ref>{{cite web\|url=https://www.embedded.com/~~electronics-products/electronic-product-reviews/embedded-tools/4107362/NEWS~~news-40-core-processor-with-~~Forth~~forth-based-~~IDE~~ide-tools-unveiled/\|title=40-core processor with Forth-based IDE tools unveiled\|last=Cole\|first=Bernard\|date=September 24, 2008}}</ref> SEAforth24, a 24-core processor designed by [[Charles H. Moore]]. * [[Kalray]] Line 239 ⟶ 245: XLR, an eight-core, quad-threaded MIPS64 processor. XLS, an eight-core, quad-threaded MIPS64 processor. * [[Samsung Electronics]] ** [[Samsung Exynos]] * [[Nvidia]] ** [[GeForce 30 series\|RTX 3090]] (~~10496~~128 ~~CUDA~~SM cores, ~~[[GPGPU]]~~10496 CUDA cores;<ref name="10496 CUDA cores">{{Cite web\|last=Smith\|first=Ryan\|title=NVIDIA Announces the GeForce RTX 30 Series: Ampere For Gaming, Starting With RTX 3080 & RTX 3090\|url=https://www.anandtech.com/show/16057/nvidia-announces-the-geforce-rtx-30-series-ampere-for-gaming-starting-with-rtx-3080-rtx-3090\|archive-url=https://web.archive.org/web/20200901181410/https://www.anandtech.com/show/16057/nvidia-announces-the-geforce-rtx-30-series-ampere-for-gaming-starting-with-rtx-3080-rtx-3090\|url-status=dead\|archive-date=September 1, 2020\|access-date=2020-09-15\|website=www.anandtech.com}}</ref> plus other more specialized cores). * [[Parallax, ~~Inc. (company)~~Propeller\|~~Parallax]] [[~~Parallax ~~Propeller\|~~Propeller P8X32]], an eight-core [[microcontroller]]. * [[picoChip]] PC200 series 200–300 cores per device for DSP & wireless. * [[Plurality (company)\|Plurality]] HAL series tightly coupled 16-256 cores, L1 shared memory, hardware synchronized processor. * Rapport [[Kilocore]] KC256, a 257-core microcontroller with a PowerPC core and 256 8-bit "processing elements". * Raspberry Pi Ltd. [[RP2040]], a dual [[ARM Cortex-M0+]] [[microcontroller]] * [[SiCortex]] "SiCortex node" has six MIPS64 cores on a single chip. * [[SiFive]] ** U74 includes 4 cores * [[Sony]]/[[IBM]]/[[Toshiba]]'s [[Cell (microprocessor)\|Cell]] processor, a nine-core processor with one general purpose [[PowerPC]] core and eight specialized SPUs (Synergistic Processing Unit) optimized for vector operations used in the [[Sony]] [[PlayStation 3]]. * [[Sun Microsystems]] [[MAJC]] 5200, two-core VLIW processor. Line 266 ⟶ 274: [[TILE64]], a 64-core 32-bit processor. ** [[TILE-Gx]], a 72-core 64-bit processor. * [[XMOS]] [[Software Defined Silicon]] quad-core XS1-G4. ===Free=== Line 283 ⟶ 291: ==Benchmarks== The research and development of multicore processors often compares many options, and benchmarks are developed to help such evaluations. Existing benchmarks include SPLASH-2, PARSEC, and COSMIC for heterogeneous systems.<ref>{{cite web\|url=~~http~~https://~~www~~eexu.home.ece.ust.hk~~/~eexu~~/COSMIC.html\|title=COSMIC ~~Heterogeneous~~:Statistical Multiprocessor Benchmark Suite~~\|archive-url=https://web.archive.org/web/20150703123808/http://www.ece.ust.hk/~eexu/COSMIC.html\|archive-date=2015-07-03~~}}</ref> ==See also== Line 291 ⟶ 299: * [[GPGPU]] * [[Hyper-threading]] * [[Manycore processor]] * [[Multicore Association]] * [[Computer multitasking\|Multitasking]] Line 309 ⟶ 317: ==Further reading== * {{cite conference \|author=Khondker S. Hasan \|author2=Nicolas G. Grounds \|author3=John K. Antonio \|title=Predicting CPU Availability of a Multi-core Processor Executing Concurrent Java Threads\|conference=17th International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA-11) \|pages=551–557 \|date=July 2011 \|___location=Las Vegas, Nevada, USA \|hdl=10657.1/2440}} * {{cite conference \|author=Khondker S. Hasan \|author2=John Antonio \|author3=Sridhar Radhakrishnan \|date=February 2014 \|title=A New Composite CPU/Memory Model for Predicting Efficiency of Multi-core Processing\|conference=The 20th IEEE International Conference on High Performance Computer Architecture (HPCA-14) workshop\|doi=10.13140/RG.2.1.3051.9207\|___location=Orlando, FL, USA}} Line 315 ⟶ 323: * [http://www.makeuseof.com/tag/processor-core-makeuseof-explains-2/ "What Is a Processor Core?"]—MakeUseOf * [https://web.archive.org/web/20110424130713/http://embedded-computing.com/embedded-moves-multicore "Embedded moves to multicore"]—''Embedded Computing Design'' * [https://spectrum.ieee.org/~~nov08/6912~~multicore-is-bad-news-for-supercomputers "Multicore Is Bad News for Supercomputers"]—''[[IEEE Spectrum]]'' * [http://www.slideshare.net/Talbott/architecting-solutions-for-the-manycore-future Architecting solutions for the Manycore future], published on Feb 19, 2010 (more than one dead link in the slide)