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{{Short description|Microprocessor with more than one processing unit}}
{{See also|Multiprocessor system architecture}}
{{Redirect-distinguish|Dual Core|Dual Core (hip hop duo)}}
[[File:Dual Core Generic.svg|thumb|Diagram of a generic dual-core processor with CPU-local level-1 caches and a shared, on-die level-2 cache]]
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The parallelization of software is a significant ongoing topic of research. Cointegration of multiprocessor applications provides flexibility in network architecture design. Adaptability within parallel models is an additional feature of systems utilizing these protocols.<ref>{{cite journal |last1=Duran |first1=A |title=Ompss: a proposal for programming heterogeneous multi-core architectures |journal=Parallel Processing Letters |date=2011 |volume=21 |issue=2|pages=173–193 |doi=10.1142/S0129626411000151 }}</ref>
In the consumer market, dual-core processors (that is, microprocessors with two units) started becoming commonplace on personal computers in the late 2000s.<ref>{{Cite web |title=Definition of dual core |url=https://www.pcmag.com/encyclopedia/term/dual-core |access-date=2023-10-27 |website=PCMAG |language=en}}</ref>
==Terminology==
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==Development==
While manufacturing technology improves, reducing the size of individual gates, physical limits of [[semiconductor]]-based [[microelectronics]] have become a major design concern. These physical limitations can cause significant heat dissipation and data synchronization problems. Various other methods are used to improve CPU performance. Some ''[[instruction-level parallelism]]'' (ILP) methods such as [[superscalar]] [[instruction pipelining|pipelining]] are suitable for many applications, but are inefficient for others that contain difficult-to-predict code. Many applications are better suited to ''[[thread-level parallelism]]'' (TLP) methods, and multiple independent CPUs are commonly used to increase a system's overall TLP. A combination of increased available space (due to refined manufacturing processes) and the demand for increased TLP led to the development of multi-core CPUs.
===Early innovations: the Stanford Hydra project===
In the 1990s, [[Kunle Olukotun]] led the Stanford Hydra Chip Multiprocessor (CMP) research project. This initiative was among the first to demonstrate the viability of integrating multiple processors on a single chip, a concept that laid the groundwork for today's multicore processors. The Hydra project introduced support for thread-level speculation (TLS), enabling more efficient parallel execution of programs.
===Commercial incentives===
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The trend in processor development has been towards an ever-increasing number of cores, as processors with hundreds or even thousands of cores become theoretically possible.<ref>{{cite web|last1=Clark|first1=Jack|title=Intel: Why a 1,000-core chip is feasible|url=https://www.zdnet.com/article/intel-why-a-1000-core-chip-is-feasible/|website=ZDNet|access-date=6 August 2015|url-status=live|archive-url=https://web.archive.org/web/20150806181915/http://www.zdnet.com/article/intel-why-a-1000-core-chip-is-feasible/|archive-date=6 August 2015}}</ref> In addition, multi-core chips mixed with [[simultaneous multithreading]], memory-on-chip, and special-purpose [[heterogeneous computing|"heterogeneous"]] (or asymmetric) cores promise further performance and efficiency gains, especially in processing multimedia, recognition and networking applications. For example, a [[ARM big.LITTLE|big.LITTLE]] core includes a high-performance core (called 'big') and a low-power core (called 'LITTLE'). There is also a trend towards improving energy-efficiency by focusing on performance-per-watt with advanced fine-grain or ultra fine-grain [[power management]] and dynamic [[dynamic voltage scaling|voltage]] and [[dynamic frequency scaling|frequency scaling]] (i.e. [[laptop]] computers and [[portable media player]]s).
Chips designed from the outset for a large number of cores (rather than having evolved from single core designs) are sometimes referred to as [[Manycore processor|manycore]] designs, emphasising qualitative differences.
===Architecture===
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Given the increasing emphasis on multi-core chip design, stemming from the grave thermal and power consumption problems posed by any further significant increase in processor clock speeds, the extent to which software can be multithreaded to take advantage of these new chips is likely to be the single greatest constraint on computer performance in the future. If developers are unable to design software to fully exploit the resources provided by multiple cores, then they will ultimately reach an insurmountable performance ceiling.
The telecommunications market had been one of the first that needed a new design of parallel datapath packet processing because there was a very quick adoption of these multiple-core processors for the datapath and the control plane. These MPUs are going to replace<ref>{{cite web|url=http://multicorepacketprocessing.com/|title=Multicore Packet Processing Forum|url-status=usurped|archive-url=https://web.archive.org/web/20091221035434/http://www.multicorepacketprocessing.com/|archive-date=2009-12-21}}</ref> the traditional Network Processors that were based on proprietary [[microcode]] or [[picocode]].
[[Parallel programming]] techniques can benefit from multiple cores directly. Some existing [[parallel programming model]]s such as [[Cilk Plus]], [[OpenMP]], [[OpenHMPP]], [[Algorithmic skeleton#FastFlow|FastFlow]], Skandium, [[Message Passing Interface|MPI]], and [[Erlang (programming language)|Erlang]] can be used on multi-core platforms. Intel introduced a new abstraction for C++ parallelism called [[Threading Building Blocks|TBB]]. Other research efforts include the [[Sieve C++ Parallel Programming System|Codeplay Sieve System]], Cray's [[Chapel (programming language)|Chapel]], Sun's [[Fortress programming language|Fortress]], and IBM's [[X10 (programming language)|X10]].
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** [[Pentium]], single, dual-core, and quad-core processors for the entry-level market.<ref>{{Cite web|url=https://ark.intel.com/content/www/us/en/ark/products/series/91594/intel-pentium-processor-d-series.html|title=Intel® Pentium® Processor D Series Product Specifications|website=ark.intel.com|language=en|access-date=2019-05-04}}</ref>
** [[Teraflops Research Chip]] (Polaris), a 3.16 GHz, 80-core processor prototype, which the company originally stated would be released by 2011.<ref>{{cite web|url=http://techfreep.com/intel-80-cores-by-2011.htm|title=Intel: 80 Cores by 2011|last=Zazaian|first=Mike|date=September 26, 2006|url-status=dead|archive-url=https://web.archive.org/web/20061109031744/http://techfreep.com/intel-80-cores-by-2011.htm|archive-date=2006-11-09|access-date=2006-09-28}}</ref>
** [[Xeon]] dual-, quad-, 6-, 8-, 10-, 12-, 14-, 15-, 16-, 18-, 20-, 22-, 24-, 26-, 28-, 32-, 48-, and 56-core processors.<ref>{{cite web|url=http://techreport.com/news/26056/intel-releases-15-core-xeon-e7-v2-processor|title=Intel releases 15-core Xeon E7 v2 processor|last=Kowaliski|first=Cyril|date=February 18, 2014|url-status=live|archive-url=https://web.archive.org/web/20141011023442/http://techreport.com/news/26056/intel-releases-15-core-xeon-e7-v2-processor|archive-date=2014-10-11}}</ref><ref>{{cite web|url=http://ark.intel.com/products/family/78585/Intel-Xeon-Processor-E7-v3-Family|title=Intel Xeon Processor E7 v3 Family|publisher=[[Intel]]|url-status=live|archive-url=https://web.archive.org/web/20150707122129/http://ark.intel.com/products/family/78585/Intel-Xeon-Processor-E7-v3-Family|archive-date=2015-07-07}}</ref><ref>{{cite web|url=http://ark.intel.com/products/family/78584/Intel-Xeon-Processor-E7-v2-Family|title=Intel Xeon Processor E7 v2 Family|work=Intel® ARK (Product Specs) |publisher=Intel|url-status=live|archive-url=https://web.archive.org/web/20150707120021/http://ark.intel.com/products/family/78584/Intel-Xeon-Processor-E7-v2-Family|archive-date=2015-07-07}}</ref><ref>{{cite web|url=http://ark.intel.com/products/family/78580/Intel-Xeon-Processor-E3-v2-Family|title=Intel Xeon Processor E3 v2 Family|work=Intel® ARK (Product Specs) |publisher=Intel|url-status=live|archive-url=https://web.archive.org/web/20150707120142/http://ark.intel.com/products/family/78580/Intel-Xeon-Processor-E3-v2-Family|archive-date=2015-07-07}}</ref><ref>{{Cite web|url=https://www.techspot.com/news/79481-intel-announces-xeon-platinum-9200-series-cpus-up.html|title=Intel shows off Xeon Platinum CPU with up to 56 cores and 112 threads|website=TechSpot|date=2 April 2019 |language=en-US|access-date=2019-05-04}}</ref><ref>{{Cite web|url=https://www.intel.com/content/www/us/en/products/docs/processors/xeon/2nd-gen-xeon-scalable-processors-brief.html|title=2nd Gen Intel® Xeon® Scalable Processors Brief|last=PDF|first=Download|website=Intel|language=en|access-date=2019-05-04}}</ref>
** [[Intel MIC#Xeon Phi|Xeon Phi]] 57-, 60-, 61-, 64-, 68-, and 72-core processors.<ref>{{Cite web|url=https://ark.intel.com/content/www/us/en/ark/products/series/92649/intel-xeon-phi-x100-product-family.html|title=Intel® Xeon Phi™ x100 Product Family Product Specifications|website=ark.intel.com|language=en|access-date=2019-05-04}}</ref><ref>{{Cite web|url=https://ark.intel.com/content/www/us/en/ark/products/series/132784/intel-xeon-phi-72x5-processor-family.html|title=Intel® Xeon Phi™ 72x5 Processor Family Product Specifications|website=ark.intel.com|language=en|access-date=2019-05-04}}</ref>
* IntellaSys
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** [[Samsung Exynos]]
* [[Nvidia]]
** [[GeForce 30 series|RTX 3090]] (128 SM cores, 10496 CUDA cores;<ref name="10496 CUDA cores">{{Cite web|last=Smith|first=Ryan|title=NVIDIA Announces the GeForce RTX 30 Series: Ampere For Gaming, Starting With RTX 3080 & RTX 3090|url=https://www.anandtech.com/show/16057/nvidia-announces-the-geforce-rtx-30-series-ampere-for-gaming-starting-with-rtx-3080-rtx-3090|archive-url=https://web.archive.org/web/20200901181410/https://www.anandtech.com/show/16057/nvidia-announces-the-geforce-rtx-30-series-ampere-for-gaming-starting-with-rtx-3080-rtx-3090|url-status=dead|archive-date=September 1, 2020|access-date=2020-09-15|website=www.anandtech.com}}</ref> plus other more specialized cores).
* [[Parallax Propeller|Parallax Propeller P8X32]], an eight-core [[microcontroller]].
* [[picoChip]] PC200 series 200–300 cores per device for DSP & wireless.
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