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{{Short description|Type of computer memory}}
{{Use American English|date=June 2025}}
{{Redirect|DRAM||Dram (disambiguation){{!}}Dram}}
{{Hatnote|{{BDprefix|p=b}}}}
[[Image:MT4C1024-HD.jpg
{{Memory types}}
▲[[Image:MT4C1024-HD.jpg|thumb|right|upright=1.8|A [[Die (integrated circuit)|die]] photograph of the [[Micron Technology]] MT4C1024 DRAM [[integrated circuit]] (1994). It has a capacity of 1 [[megabit]] equivalent to <math>2^{20}</math>bits or {{nowrap|128 [[KiB]].}}<ref name=mt4acid>{{cite web |access-date=2016-04-02 |date=2012-11-15 |title=How to "open" microchip and what's inside? : ZeptoBars |url=http://zeptobars.com/en/read/how-to-open-microchip-asic-what-inside |quote=Micron MT4C1024 — 1 mebibit (220 bit) dynamic ram. Widely used in 286 and 386-era computers, early 90s. Die size - 8662x3969μm. |url-status=live |archive-url=https://web.archive.org/web/20160314015357/http://zeptobars.com/en/read/how-to-open-microchip-asic-what-inside |archive-date=2016-03-14 }}</ref>]]
[[File:NeXTcube motherboard.jpg|thumb|[[Motherboard]] of the [[NeXTcube]] computer, 1990, with 64 MiB main memory DRAM (top left) and 256 KiB of [[Video RAM (dual-ported DRAM)|VRAM]]<ref>{{cite web|url=http://www.nextcomputers.org/NeXTfiles/Docs/Hardware/NeXTServiceManualPages1-160_OCR.pdf |title=NeXTServiceManualPages1-160 |date= |access-date=2022-03-09}}</ref> (lower edge, right of middle)]]
'''Dynamic random-access memory''' ('''dynamic RAM''' or '''DRAM''') is a type of
▲'''Dynamic random-access memory''' ('''dynamic RAM''' or '''DRAM''') is a type of [[random-access memory|random-access]] [[semiconductor memory]] that stores each [[bit]] of data in a [[memory cell (computing)|memory cell]], usually consisting of a tiny [[capacitor]] and a [[transistor]], both typically based on [[metal–oxide–semiconductor]] (MOS) technology. While most DRAM memory cell designs use a capacitor and transistor, some only use two transistors. In the designs where a capacitor is used, the capacitor can either be charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1. The [[electric charge]] on the capacitors gradually leaks away; without intervention the data on the capacitor would soon be lost. To prevent this, DRAM requires an external [[memory refresh]] circuit which periodically rewrites the data in the capacitors, restoring them to their original charge. This refresh process is the defining characteristic of dynamic random-access memory, in contrast to [[static random-access memory]] (SRAM) which does not require data to be refreshed. Unlike [[flash memory]], DRAM is [[volatile memory]] (vs. [[non-volatile memory]]), since it loses its data quickly when power is removed. However, DRAM does exhibit limited [[data remanence]].
DRAM typically takes the form of an [[integrated circuit]] chip, which can consist of dozens to billions of DRAM memory cells. DRAM chips are widely used in [[digital electronics]] where low-cost and high-capacity [[computer memory]] is required. One of the largest applications for DRAM is the ''[[main memory]]'' (colloquially called the RAM) in modern [[computer]]s and [[graphics card]]s (where the main memory is called the ''[[Video random access memory|graphics memory]]''). It is also used in many portable devices and [[video game]] consoles. In contrast, SRAM, which is faster and more expensive than DRAM, is typically used where speed is of greater concern than cost and size, such as the [[CPU cache|cache memories]] in [[Central processing unit|processor]]s.
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The [[cryptanalysis|cryptanalytic]] machine code-named ''Aquarius'' used at [[Bletchley Park]] during [[World War II]] incorporated a hard-wired dynamic memory. Paper tape was read and the characters on it "were remembered in a dynamic store." The store used a large bank of capacitors, which were either charged or not, a charged capacitor representing cross (1) and an uncharged capacitor dot (0). Since the charge gradually leaked away, a periodic pulse was applied to top up those still charged (hence the term 'dynamic')".<ref>{{cite book |first1=B. Jack |last1=Copeland |title=Colossus: The secrets of Bletchley Park's code-breaking computers |url=https://books.google.com/books?id=YiiQDwAAQBAJ&pg=PA301 |date=2010 |publisher=Oxford University Press |isbn=978-0-19-157366-8 |page=301}}</ref>
In November 1965, [[Toshiba]] introduced a bipolar dynamic RAM for its [[electronic calculator]] Toscal BC-1411.<ref name="toscal">{{cite web|url=http://www.oldcalculatormuseum.com/s-toshbc1411.html|title=Spec Sheet for Toshiba "TOSCAL" BC-1411|website=www.oldcalculatormuseum.com|access-date=8 May 2018|url-status=live|archive-url=https://web.archive.org/web/20170703071307/http://www.oldcalculatormuseum.com/s-toshbc1411.html|archive-date=3 July 2017}}</ref><ref>
The earliest forms of DRAM mentioned above used [[bipolar transistors]]. While it offered improved performance over [[magnetic-core memory]], bipolar DRAM could not compete with the lower price of the then-dominant magnetic-core memory.<ref>{{cite web |title=1966: Semiconductor RAMs Serve High-speed Storage Needs |url=https://www.computerhistory.org/siliconengine/semiconductor-rams-serve-high-speed-storage-needs/ |website=Computer History Museum}}</ref> Capacitors had also been used for earlier memory schemes, such as the drum of the [[Atanasoff–Berry Computer]], the [[Williams tube]] and the [[Selectron tube]].
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The same year, Honeywell asked [[Intel]] to make a DRAM using a three-transistor cell that they had developed. This became the Intel 1102 in early 1970.<ref>{{cite web|url=http://inventors.about.com/library/weekly/aa100898.htm|archive-url=https://archive.today/20130306105823/http://inventors.about.com/library/weekly/aa100898.htm|url-status=dead|archive-date=March 6, 2013|title=Who Invented the Intel 1103 DRAM Chip?|publisher=ThoughtCo|author=Mary Bellis|date=23 Feb 2018|access-date=27 Feb 2018}}</ref> However, the 1102 had many problems, prompting Intel to begin work on their own improved design, in secrecy to avoid conflict with Honeywell. This became the first commercially available DRAM, the [[Intel 1103]], in October 1970, despite initial problems with low yield until the fifth revision of the [[photomask|mask]]s. The 1103 was designed by Joel Karp and laid out by Pat Earhart. The masks were cut by Barbara Maness and Judy Garcia.<ref>{{cite web |url=http://archive.computerhistory.org/resources/still-image/PENDING/X3665.2007/Semi_SIG/Notes%20from%20interview%20with%20John%20Reed.pdf |title=Archived copy |access-date=2014-01-15 |url-status=dead |archive-url=https://web.archive.org/web/20140116124021/http://archive.computerhistory.org/resources/still-image/PENDING/X3665.2007/Semi_SIG/Notes%20from%20interview%20with%20John%20Reed.pdf |archive-date=2014-01-16 }}</ref>{{original research inline|date=December 2016}} MOS memory overtook magnetic-core memory as the dominant memory technology in the early 1970s.<ref name="computerhistory1970"/>
The first DRAM with multiplexed row and column [[address bus|address lines]] was the [[Mostek]] MK4096 4 Kbit DRAM designed by Robert Proebsting and introduced in 1973. This addressing scheme uses the same address pins to receive the low half and the high half of the address of the memory cell being referenced, switching between the two halves on alternating bus cycles. This was a radical advance, effectively halving the number of address lines required, which enabled it to fit into packages with fewer pins, a cost advantage that grew with every jump in memory size. The MK4096 proved to be a very robust design for customer applications. At the 16 Kbit density, the cost advantage increased; the 16 Kbit Mostek MK4116 DRAM,<ref>{{cite web |first=Ken |last=Shirriff |title=Reverse-engineering the classic MK4116 16-kilobit DRAM chip |date=November 2020 |url=
Early in 1985, [[Gordon Moore]] decided to withdraw Intel from producing DRAM.<ref>
By 1986, many, but not all, United States chip makers had stopped making DRAMs.<ref>{{cite book |first1=William R. |last1=Nester |title=American Industrial Policy: Free or Managed Markets? |url=https://books.google.com/books?id=hCi_DAAAQBAJ |date=2016 |publisher=Springer |isbn=978-1-349-25568-9 |page=115}}
</ref> Micron Technology and Texas Instruments continued to produce them commercially, and IBM produced them for internal use.
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|newspaper=New York Times
|date=3 August 1985}}
<
{{cite news |first1=Donald |last1=Woutat.
|url=https://www.latimes.com/archives/la-xpm-1985-12-04-fi-625-story.html |title=6 Japan Chip Makers Cited for Dumping
|newspaper=Los Angeles Times
|date=4 November 1985}}
<
{{cite news |url=https://www.latimes.com/archives/la-xpm-1986-03-14-fi-20761-story.html |title=More Japan Firms Accused: U.S. Contends 5 Companies Dumped Chips
|newspaper=Los Angeles Times
|date=1986}}
<
{{cite news |first1=David E. |last1=Sanger
|url=https://www.nytimes.com/1987/11/03/business/japanese-chip-dumping-has-ended-us-finds.html |title=Japanese Chip Dumping Has Ended, U.S. Finds
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Later, in 2001, Japanese DRAM makers accused Korean DRAM manufacturers of dumping.<ref>
{{cite web |author1=Kuriko Miyake
|url=
|date=2001}}
<
{{cite news |url=https://www.itworld.com/article/2794396/japanese-chip-makers-suspect-dumping-by-korean-firms.html |title=Japanese chip makers suspect dumping by Korean firms |newspaper=ITWorld
|date=2001}}
<
{{cite web |url=https://www.eetimes.com/dram-pricing-investigation-in-japan-targets-hynix-samsung/ |title=DRAM pricing investigation in Japan targets Hynix, Samsung
|date=2001 |publisher=EETimes }}
<
{{cite web |url=https://phys.org/news/2006-01-korean-dram-japan.html |title=Korean DRAM finds itself shut out of Japan |publisher=Phys.org
|date=2006 }}
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The row address of the row that will be refreshed next is maintained by external logic or a [[Counter (digital)|counter]] within the DRAM. A system that provides the row address (and the refresh command) does so to have greater control over when to refresh and which row to refresh. This is done to minimize conflicts with memory accesses, since such a system has both knowledge of the memory access patterns and the refresh requirements of the DRAM. When the row address is supplied by a counter within the DRAM, the system relinquishes control over which row is refreshed and only provides the refresh command. Some modern DRAMs are capable of self-refresh; no external logic is required to instruct the DRAM to refresh or to provide a row address.
Under some conditions, most of the data in DRAM can be recovered even if the DRAM has not been refreshed for several minutes.<ref>
===Memory timing===
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==Memory cell design==
{{See also|Memory cell (computing)}}
Each bit of data in a DRAM is stored as a positive or negative electrical charge in a capacitive structure. The structure providing the capacitance, as well as the transistors that control access to it, is collectively referred to as a ''DRAM cell''. They are the fundamental building block in DRAM arrays. Multiple DRAM memory cell variants exist, but the most commonly used variant in modern DRAMs is the one-transistor, one-capacitor (1T1C) cell. The transistor is used to admit current into the capacitor during writes, and to discharge the capacitor during reads. The access transistor is designed to maximize drive strength and minimize transistor-transistor leakage (Kenner,
The capacitor has two terminals, one of which is connected to its access transistor, and the other to either ground or V<sub>CC</sub>/2. In modern DRAMs, the latter case is more common, since it allows faster operation. In modern DRAMs, a voltage of +V<sub>CC</sub>/2 across the capacitor is required to store a logic one; and a voltage of
Reading or writing a logic one requires the wordline
===Capacitor design===
Up until the mid-1980s, the capacitors in DRAM cells were co-planar with the access transistor (they were constructed on the surface of the substrate), thus they were referred to as ''planar'' capacitors. The drive to increase both density and, to a lesser extent, performance, required denser designs. This was strongly motivated by economics, a major consideration for DRAM devices, especially commodity DRAMs. The minimization of DRAM cell area can produce a denser device and lower the cost per bit of storage. Starting in the mid-1980s, the capacitor was moved above or below the silicon substrate in order to meet these objectives. DRAM cells featuring capacitors above the substrate are referred to as ''stacked'' or ''folded plate'' capacitors. Those with capacitors buried beneath the substrate surface are referred to as ''trench'' capacitors. In the 2000s, manufacturers were sharply divided by the type of capacitor used in their DRAMs and the relative cost and long-term scalability of both designs have been the subject of extensive debate. The majority of DRAMs, from major manufactures such as [[Hynix]], [[Micron Technology]], [[Samsung Electronics]] use the stacked capacitor structure,<!--where a cylindrical and tall capacitor is stacked on top of the transistor--> whereas smaller manufacturers such Nanya Technology use the trench capacitor structure (Jacob, pp. 355–357).
The capacitor in the stacked capacitor scheme is constructed above the surface of the substrate. The capacitor is constructed from an oxide-nitride-oxide (ONO) dielectric sandwiched in between two layers of polysilicon plates (the top plate is shared by all DRAM cells in an IC), and its shape can be a rectangle, a cylinder, or some other more complex shape. There are two basic variations of the stacked capacitor, based on its ___location relative to the bitline—capacitor-
The trench capacitor is constructed by etching a deep hole into the silicon substrate. The substrate volume surrounding the hole is then heavily doped to produce a buried n<sup>+</sup> plate
Trench capacitors have numerous advantages. Since the capacitor is buried in the bulk of the substrate instead of lying on its surface, the area it occupies can be minimized to what is required to connect it to the access transistor's drain terminal without decreasing the capacitor's size, and thus capacitance (Jacob, pp. 356–357). Alternatively, the capacitance can be increased by etching a deeper hole without any increase to surface area (Kenner,
===Historical cell designs===
First-generation DRAM ICs (those with capacities of 1 Kbit),
===Proposed cell designs===
The one-transistor, zero-capacitor (1T, or 1T0C) DRAM cell has been a topic of research since the late-1990s. ''1T DRAM'' is a different way of constructing the basic DRAM memory cell, distinct from the classic one-transistor/one-capacitor (1T/1C) DRAM cell, which is also sometimes referred to as ''1T DRAM'', particularly in comparison to the 3T and 4T DRAM which it replaced in the 1970s.
In 1T DRAM cells, the bit of data is still stored in a capacitive region controlled by a transistor, but this capacitance is no longer provided by a separate capacitor. 1T DRAM is a "capacitorless" bit cell design that stores data using the parasitic body capacitance that is inherent to [[silicon on insulator
Refreshing of cells remains necessary, but unlike with 1T1C DRAM, reads in 1T DRAM are non-destructive; the stored charge causes a detectable shift in the [[threshold voltage]] of the transistor.<ref>{{cite conference|first=Jean-Michel|last=Sallese|title=Principles of the 1T Dynamic Access Memory Concept on SOI|
==Array structures==<!--The RSes for all points in this section: Jacob, pp 358–361; Kenner, pp. 65 75-->
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}}</ref> The extra memory bits are used to record [[RAM parity|parity]] and to enable missing data to be reconstructed by [[error-correcting code]] (ECC). Parity allows the detection of all single-bit errors (actually, any odd number of wrong bits). The most common error-correcting code, a [[Hamming code#Hamming codes with additional parity (SECDED)|SECDED Hamming code]], allows a single-bit error to be corrected and, in the usual configuration, with an extra parity bit, double-bit errors to be detected.<ref>{{cite web|author1=Mastipuram, Ritesh|author2=Wee, Edwin C|title=Soft errors' impact on system reliability|url=http://www.edn.com/article/CA454636.html|website=EDN|publisher=Cypress Semiconductor|archive-url=https://web.archive.org/web/20070416115228/http://www.edn.com/article/CA454636.html|archive-date=16 April 2007|date=30 September 2004}}</ref>
Recent studies give widely varying error rates with over seven orders of magnitude difference, ranging from {{nowrap|10<sup>−10</sup>−10<sup>−17</sup> error/bit·h}}, roughly one bit error, per hour, per gigabyte of memory to one bit error, per century, per gigabyte of memory.<ref name="Borucki1">Borucki, "Comparison of Accelerated DRAM Soft Error Rates Measured at Component and System Level", 46th Annual International Reliability Physics Symposium, Phoenix, 2008, pp. 482–487</ref><ref name="Schroeder1">[[Bianca Schroeder|Schroeder, Bianca]] et al. (2009). [http://www.cs.toronto.edu/~bianca/papers/sigmetrics09.pdf "DRAM errors in the wild: a large-scale field study"] {{webarchive|url=https://web.archive.org/web/20150310193355/http://www.cs.toronto.edu/~bianca/papers/sigmetrics09.pdf |date=2015-03-10 }}. ''Proceedings of the Eleventh International Joint Conference on Measurement and Modeling of Computer Systems'', pp. 193–204.</ref><ref name="Xin1">{{cite web|url=http://www.ece.rochester.edu/~xinli/usenix07/|title=A Memory Soft Error Measurement on Production Systems|website=www.ece.rochester.edu|access-date=8 May 2018|url-status=dead|archive-url=https://web.archive.org/web/20170214005146/http://www.ece.rochester.edu/~xinli/usenix07/|archive-date=14 February 2017}}</ref> The Schroeder et al. 2009 study reported a 32% chance that a given computer in their study would suffer from at least one correctable error per year, and provided evidence that most such errors are intermittent hard rather than soft errors and that trace amounts of radioactive material that had gotten into the chip packaging were emitting alpha particles and corrupting the data.<ref>{{cite web |url=https://spectrum.ieee.org/drams-damning-defects-and-how-they-cripple-computers |title=DRAM's Damning Defects—and How They Cripple Computers - IEEE Spectrum |access-date=2015-11-24 |url-status=live |archive-url=https://web.archive.org/web/20151124182515/https://spectrum.ieee.org/computing/hardware/drams-damning-defects-and-how-they-cripple-computers |archive-date=2015-11-24 }}</ref> A 2010 study at the University of Rochester also gave evidence that a substantial fraction of memory errors are intermittent hard errors.<ref>{{cite web|url=
==Security==
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# At the end of the required amount of time, {{overline|RAS}} must return high.
This can be done by supplying a row address and pulsing {{overline|RAS}} low; it is not necessary to perform any {{overline|CAS}} cycles. An external counter is needed to iterate over the row addresses in turn.<ref name=IBM96>{{cite tech report |type=Application Note |title=Understanding DRAM Operation |url=http://www.ece.cmu.edu/~ece548/localcpy/dramop.pdf|publisher=[[IBM]]|archive-url=https://web.archive.org/web/20170829153054/http://www.ece.cmu.edu/~ece548/localcpy/dramop.pdf|archive-date=29 August 2017|date=December 1996}}</ref> In some designs, the CPU handled RAM refresh. The [[Zilog Z80]] is perhaps the best known example, as it has an internal row counter R which supplies the address for a special refresh cycle generated after each instruction fetch.<!--And data transfer in string instructions, and during HALT, but that's more detail than we need here.--><ref>{{cite tech report |title=Z80 CPU |type=User Manual |url=
=====CAS before RAS refresh=====
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[[Image:Pair32mbEDO-DRAMdimms.jpg|thumb|A pair of 32 [[Megabyte|MB]] EDO DRAM modules]]
Extended data out DRAM (EDO DRAM) was invented and patented in the 1990s by [[Micron Technology]] who then licensed technology to many other memory manufacturers.<ref>{{cite book | author=S. Mueller | title=Upgrading and Repairing Laptops | year=2004 | publisher=Que; Har/Cdr Edition | page=221 | isbn=9780789728005 |url=https://books.google.com/books?id=xCXVGneKwScC}}</ref> EDO RAM, sometimes referred to as ''hyper page mode'' enabled DRAM, is similar to fast page mode DRAM with the additional feature that a new access cycle can be started while keeping the data output of the previous cycle active. This allows a certain amount of overlap in operation (pipelining), allowing somewhat improved performance.<ref name=IBM96b>{{cite tech report |type=Applications Note |title=EDO (Hyper Page Mode)|url=https://www.ardent-tool.com/memory/pdf/edo.pdf |publisher=[[IBM]]|date=6 June 1996|archive-url=https://web.archive.org/web/20211202232211/https://ardent-tool.com/memory/pdf/edo.pdf|archive-date=2021-12-02|quote=a new address can be provided for the next access cycle before completing the current cycle allowing a shorter {{overline|CAS}} pulse width, dramatically decreasing cycle times.}}</ref> It is up to 30% faster than FPM DRAM,<ref>{{cite web|last1=Lin|first1=Albert|title=Memory Grades, the Most Confusing Subject|url=
To be precise, EDO DRAM begins data output on the falling edge of {{overline|CAS}} but does not
Single-cycle EDO DRAM became very popular on video cards
====Burst EDO DRAM====
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Synchronous dynamic RAM (SDRAM) significantly revises the asynchronous memory interface, adding a clock (and a clock enable) line. All other signals are received on the rising edge of the clock.
The {{overline|RAS}} and {{overline|CAS}} inputs no longer act as strobes, but are instead, along with {{overline|WE}}, part of a 3-bit command
{| class="wikitable"
|+ SDRAM Command summary
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Many timing parameters remain under the control of the DRAM controller. For example, a minimum time must elapse between a row being activated and a read or write command. One important parameter must be programmed into the SDRAM chip itself, namely the [[CAS latency]]. This is the number of clock cycles allowed for internal operations between a read command and the first data word appearing on the data bus. The ''Load mode register'' command is used to transfer this value to the SDRAM chip. Other configurable parameters include the length of read and write bursts, i.e. the number of words transferred per read or write command.
The most significant change, and the primary reason that SDRAM has supplanted asynchronous RAM, is the support for multiple internal banks inside the DRAM chip. Using a few bits of ''bank address'' that accompany each command, a second bank can be activated and begin reading data ''while a read from the first bank is in progress''. By alternating banks,
====Single data rate synchronous DRAM====
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====Video DRAM====
{{Main|
Video DRAM (VRAM) is a [[dual-ported RAM|dual-ported]] variant of DRAM that was once commonly used to store the frame
===={{Anchor|WRAM}}Window DRAM====
Window DRAM (WRAM) is a variant of VRAM that was once used in graphics
===={{Anchor|MDRAM}}Multibank DRAM====
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===={{Anchor|SGRAM}}Synchronous graphics RAM====
Synchronous graphics RAM (SGRAM) is a specialized form of SDRAM for graphics
====Graphics double data rate SDRAM====
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[[File:Sapphire Ultimate HD 4670 512MB - Qimonda HYB18H512321BF-10-93577.jpg|alt=|thumb|A 512-MBit [[Qimonda]] GDDR3 SDRAM package]]
[[File:SAMSUNG@QDDR3-SDRAM@256MBit@K5J55323QF-GC16 Stack-DSC01340-DSC01367 - ZS-retouched.jpg|thumb|Inside a Samsung GDDR3 256-MBit package]]
Graphics double data rate SDRAM is a type of specialized [[Double data rate|DDR]] [[Synchronous dynamic random-access memory|SDRAM]] designed to be used as the main memory of [[graphics processing unit]]s (GPUs). GDDR SDRAM is distinct from commodity types of DDR SDRAM such as DDR3, although they share some core technologies. Their primary characteristics are higher clock frequencies for both the DRAM core and I/O interface, which provides greater memory bandwidth for GPUs. As of
==={{Anchor|PSRAM}}Pseudostatic RAM===
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==External links==
* {{cite book |url=http://www.eecs.berkeley.edu/~culler/courses/cs252-s05/lectures/cs252s05-lec01-intro.ppt#359,15,Memory%20Capacity%20%20(Single%20Chip%20DRAM |first1=David |last1=Culler |chapter=Memory Capacity (Single Chip DRAM) |page=15 |title=EECS 252 Graduate Computer Architecture: Lecture 1 |publisher=Electrical Engineering and Computer Sciences,University of California, Berkeley |year=2005}} Logarithmic graph 1980–2003 showing size and cycle time.
* [
* [http://www.tezzaron.com/about/papers/soft_errors_1_1_secure.pdf Tezzaron Semiconductor Soft Error White Paper] 1994 literature review of memory error rate measurements.
* {{cite web |url=http://www.nepp.nasa.gov/docuploads/40D7D6C9-D5AA-40FC-829DC2F6A71B02E9/Scal-00.pdf |title=Scaling and Technology Issues for Soft Error Rates |first1=A. |last1=Johnston |work=4th Annual Research Conference on Reliability Stanford University |date=October 2000|url-status=dead |archive-url=https://web.archive.org/web/20041103124422/http://www.nepp.nasa.gov/docuploads/40D7D6C9-D5AA-40FC-829DC2F6A71B02E9/Scal-00.pdf |archive-date=2004-11-03 }}
* {{cite journal |url=http://www.research.ibm.com/journal/rd/462/mandelman.html |title=Challenges and future directions for the scaling of dynamic random-access memory (DRAM) |date=2002 |doi=10.1147/rd.462.0187|archive-url=https://web.archive.org/web/20050322211513/http://www.research.ibm.com/journal/rd/462/mandelman.html|archive-date=2005-03-22|last1=Mandelman |first1=J. A. |last2=Dennard |first2=R. H. |last3=Bronner |first3=G. B. |last4=Debrosse |first4=J. K. |last5=Divakaruni |first5=R. |last6=Li |first6=Y. |last7=Radens |first7=C. J. |journal=IBM Journal of Research and Development |volume=46 |issue=2.3 |pages=187–212 }}
* [https://arstechnica.com/paedia/r/ram_guide/ram_guide.part1-2.html Ars Technica: RAM Guide]
* {{cite thesis|first1=David Tawei |last1=Wang|title=Modern DRAM Memory Systems: Performance Analysis and a High Performance, Power-Constrained DRAM-Scheduling Algorithm|type=PhD |publisher=University of Maryland, College Park|year=2005|url=
* [
* {{cite web |url=https://lwn.net/Articles/250967/ |title=What every programmer should know about memory |first1=Ulrich |last1=Drepper |year=2007}}
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