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The same year, Honeywell asked [[Intel]] to make a DRAM using a three-transistor cell that they had developed. This became the Intel 1102 in early 1970.<ref>{{cite web|url=http://inventors.about.com/library/weekly/aa100898.htm|archive-url=https://archive.today/20130306105823/http://inventors.about.com/library/weekly/aa100898.htm|url-status=dead|archive-date=March 6, 2013|title=Who Invented the Intel 1103 DRAM Chip?|publisher=ThoughtCo|author=Mary Bellis|date=23 Feb 2018|access-date=27 Feb 2018}}</ref> However, the 1102 had many problems, prompting Intel to begin work on their own improved design, in secrecy to avoid conflict with Honeywell. This became the first commercially available DRAM, the [[Intel 1103]], in October 1970, despite initial problems with low yield until the fifth revision of the [[photomask|mask]]s. The 1103 was designed by Joel Karp and laid out by Pat Earhart. The masks were cut by Barbara Maness and Judy Garcia.<ref>{{cite web |url=http://archive.computerhistory.org/resources/still-image/PENDING/X3665.2007/Semi_SIG/Notes%20from%20interview%20with%20John%20Reed.pdf |title=Archived copy |access-date=2014-01-15 |url-status=dead |archive-url=https://web.archive.org/web/20140116124021/http://archive.computerhistory.org/resources/still-image/PENDING/X3665.2007/Semi_SIG/Notes%20from%20interview%20with%20John%20Reed.pdf |archive-date=2014-01-16 }}</ref>{{original research inline|date=December 2016}} MOS memory overtook magnetic-core memory as the dominant memory technology in the early 1970s.<ref name="computerhistory1970"/>
The first DRAM with multiplexed row and column [[address bus|address lines]] was the [[Mostek]] MK4096 4 Kbit DRAM designed by Robert Proebsting and introduced in 1973. This addressing scheme uses the same address pins to receive the low half and the high half of the address of the memory cell being referenced, switching between the two halves on alternating bus cycles. This was a radical advance, effectively halving the number of address lines required, which enabled it to fit into packages with fewer pins, a cost advantage that grew with every jump in memory size. The MK4096 proved to be a very robust design for customer applications. At the 16 Kbit density, the cost advantage increased; the 16 Kbit Mostek MK4116 DRAM,<ref>{{cite web |first=Ken |last=Shirriff |title=Reverse-engineering the classic MK4116 16-kilobit DRAM chip |date=November 2020 |url=
Early in 1985, [[Gordon Moore]] decided to withdraw Intel from producing DRAM.<ref>{{cite web |url=http://www.shmj.or.jp/makimoto/en/pdf/makimoto_E_01_12.pdf |title=Outbreak of Japan-US Semiconductor War |archive-url=https://web.archive.org/web/20200229223250/http://www.shmj.or.jp/makimoto/en/pdf/makimoto_E_01_12.pdf |archive-date=2020-02-29 }}</ref>
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Later, in 2001, Japanese DRAM makers accused Korean DRAM manufacturers of dumping.<ref>
{{cite web |author1=Kuriko Miyake
|url=
|date=2001}}
</ref><ref>
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}}</ref> The extra memory bits are used to record [[RAM parity|parity]] and to enable missing data to be reconstructed by [[error-correcting code]] (ECC). Parity allows the detection of all single-bit errors (actually, any odd number of wrong bits). The most common error-correcting code, a [[Hamming code#Hamming codes with additional parity (SECDED)|SECDED Hamming code]], allows a single-bit error to be corrected and, in the usual configuration, with an extra parity bit, double-bit errors to be detected.<ref>{{cite web|author1=Mastipuram, Ritesh|author2=Wee, Edwin C|title=Soft errors' impact on system reliability|url=http://www.edn.com/article/CA454636.html|website=EDN|publisher=Cypress Semiconductor|archive-url=https://web.archive.org/web/20070416115228/http://www.edn.com/article/CA454636.html|archive-date=16 April 2007|date=30 September 2004}}</ref>
Recent studies give widely varying error rates with over seven orders of magnitude difference, ranging from {{nowrap|10<sup>−10</sup>−10<sup>−17</sup> error/bit·h}}, roughly one bit error, per hour, per gigabyte of memory to one bit error, per century, per gigabyte of memory.<ref name="Borucki1">Borucki, "Comparison of Accelerated DRAM Soft Error Rates Measured at Component and System Level", 46th Annual International Reliability Physics Symposium, Phoenix, 2008, pp. 482–487</ref><ref name="Schroeder1">[[Bianca Schroeder|Schroeder, Bianca]] et al. (2009). [http://www.cs.toronto.edu/~bianca/papers/sigmetrics09.pdf "DRAM errors in the wild: a large-scale field study"] {{webarchive|url=https://web.archive.org/web/20150310193355/http://www.cs.toronto.edu/~bianca/papers/sigmetrics09.pdf |date=2015-03-10 }}. ''Proceedings of the Eleventh International Joint Conference on Measurement and Modeling of Computer Systems'', pp. 193–204.</ref><ref name="Xin1">{{cite web|url=http://www.ece.rochester.edu/~xinli/usenix07/|title=A Memory Soft Error Measurement on Production Systems|website=www.ece.rochester.edu|access-date=8 May 2018|url-status=dead|archive-url=https://web.archive.org/web/20170214005146/http://www.ece.rochester.edu/~xinli/usenix07/|archive-date=14 February 2017}}</ref> The Schroeder et al. 2009 study reported a 32% chance that a given computer in their study would suffer from at least one correctable error per year, and provided evidence that most such errors are intermittent hard rather than soft errors and that trace amounts of radioactive material that had gotten into the chip packaging were emitting alpha particles and corrupting the data.<ref>{{cite web |url=https://spectrum.ieee.org/drams-damning-defects-and-how-they-cripple-computers |title=DRAM's Damning Defects—and How They Cripple Computers - IEEE Spectrum |access-date=2015-11-24 |url-status=live |archive-url=https://web.archive.org/web/20151124182515/https://spectrum.ieee.org/computing/hardware/drams-damning-defects-and-how-they-cripple-computers |archive-date=2015-11-24 }}</ref> A 2010 study at the University of Rochester also gave evidence that a substantial fraction of memory errors are intermittent hard errors.<ref>{{cite web|url=
==Security==
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# At the end of the required amount of time, {{overline|RAS}} must return high.
This can be done by supplying a row address and pulsing {{overline|RAS}} low; it is not necessary to perform any {{overline|CAS}} cycles. An external counter is needed to iterate over the row addresses in turn.<ref name=IBM96>{{cite tech report |type=Application Note |title=Understanding DRAM Operation |url=http://www.ece.cmu.edu/~ece548/localcpy/dramop.pdf|publisher=[[IBM]]|archive-url=https://web.archive.org/web/20170829153054/http://www.ece.cmu.edu/~ece548/localcpy/dramop.pdf|archive-date=29 August 2017|date=December 1996}}</ref> In some designs, the CPU handled RAM refresh. The [[Zilog Z80]] is perhaps the best known example, as it has an internal row counter R which supplies the address for a special refresh cycle generated after each instruction fetch.<!--And data transfer in string instructions, and during HALT, but that's more detail than we need here.--><ref>{{cite tech report |title=Z80 CPU |type=User Manual |url=
=====CAS before RAS refresh=====
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===={{Anchor|WRAM}}Window DRAM====
Window DRAM (WRAM) is a variant of VRAM that was once used in graphics adapters such as the [[Matrox]] Millennium and [[Rage Pro#3D Rage Pro & Rage IIc|ATI 3D Rage Pro]]. WRAM was designed to perform better and cost less than VRAM. WRAM offered up to 25% greater bandwidth than VRAM and accelerated commonly used graphical operations such as text drawing and block fills.<ref name="wramdef">{{cite web |url=
===={{Anchor|MDRAM}}Multibank DRAM====
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[[File:Sapphire Ultimate HD 4670 512MB - Qimonda HYB18H512321BF-10-93577.jpg|alt=|thumb|A 512-MBit [[Qimonda]] GDDR3 SDRAM package]]
[[File:SAMSUNG@QDDR3-SDRAM@256MBit@K5J55323QF-GC16 Stack-DSC01340-DSC01367 - ZS-retouched.jpg|thumb|Inside a Samsung GDDR3 256-MBit package]]
Graphics double data rate SDRAM is a type of specialized [[Double data rate|DDR]] [[Synchronous dynamic random-access memory|SDRAM]] designed to be used as the main memory of [[graphics processing unit]]s (GPUs). GDDR SDRAM is distinct from commodity types of DDR SDRAM such as DDR3, although they share some core technologies. Their primary characteristics are higher clock frequencies for both the DRAM core and I/O interface, which provides greater memory bandwidth for GPUs. As of
==={{Anchor|PSRAM}}Pseudostatic RAM===
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==External links==
* {{cite book |url=http://www.eecs.berkeley.edu/~culler/courses/cs252-s05/lectures/cs252s05-lec01-intro.ppt#359,15,Memory%20Capacity%20%20(Single%20Chip%20DRAM |first1=David |last1=Culler |chapter=Memory Capacity (Single Chip DRAM) |page=15 |title=EECS 252 Graduate Computer Architecture: Lecture 1 |publisher=Electrical Engineering and Computer Sciences,University of California, Berkeley |year=2005}} Logarithmic graph 1980–2003 showing size and cycle time.
* [
* [http://www.tezzaron.com/about/papers/soft_errors_1_1_secure.pdf Tezzaron Semiconductor Soft Error White Paper] 1994 literature review of memory error rate measurements.
* {{cite web |url=http://www.nepp.nasa.gov/docuploads/40D7D6C9-D5AA-40FC-829DC2F6A71B02E9/Scal-00.pdf |title=Scaling and Technology Issues for Soft Error Rates |first1=A. |last1=Johnston |work=4th Annual Research Conference on Reliability Stanford University |date=October 2000|url-status=dead |archive-url=https://web.archive.org/web/20041103124422/http://www.nepp.nasa.gov/docuploads/40D7D6C9-D5AA-40FC-829DC2F6A71B02E9/Scal-00.pdf |archive-date=2004-11-03 }}
* {{cite journal |url=http://www.research.ibm.com/journal/rd/462/mandelman.html |title=Challenges and future directions for the scaling of dynamic random-access memory (DRAM) |date=2002 |doi=10.1147/rd.462.0187|archive-url=https://web.archive.org/web/20050322211513/http://www.research.ibm.com/journal/rd/462/mandelman.html|archive-date=2005-03-22|last1=Mandelman |first1=J. A. |last2=Dennard |first2=R. H. |last3=Bronner |first3=G. B. |last4=Debrosse |first4=J. K. |last5=Divakaruni |first5=R. |last6=Li |first6=Y. |last7=Radens |first7=C. J. |journal=IBM Journal of Research and Development |volume=46 |issue=2.3 |pages=187–212 }}
* [https://arstechnica.com/paedia/r/ram_guide/ram_guide.part1-2.html Ars Technica: RAM Guide]
* {{cite thesis|first1=David Tawei |last1=Wang|title=Modern DRAM Memory Systems: Performance Analysis and a High Performance, Power-Constrained DRAM-Scheduling Algorithm|type=PhD |publisher=University of Maryland, College Park|year=2005|url=
* [
* {{cite web |url=https://lwn.net/Articles/250967/ |title=What every programmer should know about memory |first1=Ulrich |last1=Drepper |year=2007}}
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