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{{Short description |Model that
{{Broader|Computer architecture}}
{{Distinguish|Industry Standard Architecture}}
{{Machine code}}
In general, an ISA defines the
An ISA specifies the behavior
If an [[operating system]] maintains a standard and compatible [[application binary interface]] (ABI) for a particular ISA, machine code will run on future implementations of that ISA and operating system. However, if an ISA supports running multiple operating systems, it does not guarantee that machine code for one operating system will run on another operating system, unless the first operating system supports running machine code built for the other operating system.
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==Classification of ISAs==
{{See also|Comparison of instruction set architectures}}
An ISA may be classified in a number of different ways. A common classification is by architectural ''complexity''. A [[complex instruction set computer]] (CISC) has many specialized instructions, some of which may only be rarely used in practical programs. A [[reduced instruction set computer]] (RISC) simplifies the processor by efficiently implementing only the instructions that are frequently used in programs, while the less common operations are implemented as subroutines, having their resulting additional processor execution time offset by infrequent use.<ref>{{cite web |last1=Chen |first1=Crystal |last2=Novick |first2=Greg |last3=Shimano |first3=Kirk |date=December 16, 2006 |title=RISC Architecture: RISC vs. CISC |url=http://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/risccisc/ |url-status=dead |archive-url=https://web.archive.org/web/20150221071744/http://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/risccisc/ |archive-date=February 21, 2015 |access-date=February 21, 2015 |website=cs.stanford.edu}}</ref>
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*''[[Conditional branch|Conditionally branch]]'' to another ___location if a certain condition holds.
*''[[Indirect branch|Indirectly branch]]'' to another ___location.
*''Skip'' one
*''Trap'' Explicitly cause an [[interrupt]], either conditionally or unconditionally.
*''[[Subroutine|Call]]'' another block of code, while saving, e.g., the ___location of the next instruction, as a point to return to.
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*Load/store data to and from a coprocessor or exchanging with CPU registers.
*Perform coprocessor operations.
:Some examples of coprocessor instructions include those for the [[IBM 3090]] [[IBM 3090#Vector facility|Vector facility]] and the [[Intel 8087]].
===Complex instructions===
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*''{{vanchor|[[SIMD]] instruction|SIMD instruction}}s'', a single instruction performing an operation on many homogeneous values in parallel, possibly in dedicated [[SIMD register]]s
*performing an atomic [[test-and-set]] instruction or other [[read–modify–write]] [[atomic instruction]]
*instructions that perform [[arithmetic logic unit|ALU]] operations with an operand from memory rather than a register: exceptions to this rule being architectures that were designed as memory-based from the ground up, such as the [[CDC STAR-100]].
Complex instructions are more common in CISC instruction sets than in RISC instruction sets, but RISC instruction sets may include them as well. RISC instruction sets generally do not include ALU operations with memory operands, or instructions to move large blocks of memory, but most RISC instruction sets include [[Single instruction, multiple data|SIMD]] or [[vector processing|vector]] instructions that perform the same arithmetic operation on multiple pieces of data at the same time. SIMD instructions have the ability of manipulating large vectors and matrices in minimal time. SIMD instructions allow easy [[parallelization]] of algorithms commonly involved in sound, image, and video processing. Various SIMD implementations have been brought to market under trade names such as [[MMX (instruction set)|MMX]], [[3DNow!]], and [[AltiVec]].
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Most [[stack machine]]s have "[[0-operand instruction set|0-operand]]" instruction sets in which arithmetic and logical operations lack any operand specifier fields; only instructions that push operands onto the evaluation stack or that pop operands from the stack into variables have operand specifiers. The instruction set carries out most ALU actions with postfix ([[reverse Polish notation]]) operations that work only on the expression [[Stack (abstract data type)|stack]], not on data registers or arbitrary main memory cells. This can be very convenient for compiling high-level languages, because most arithmetic expressions can be easily translated into postfix notation.<ref>{{cite web|url=http://www.cs.kent.edu/~durand/CS0/Notes/Chapter05/isa.html|title=Instruction Set Architecture (ISA)|work=Introduction to Computer Science CS 0|first=Paul|last=Durand}}</ref>
====Conditional instructions====
<!-- A conditional branch that falls though may still have other effects, e.g., decrementing a count register. -->
Conditional instructions often have a predicate field—a few bits that encode the specific condition to cause an operation to be performed rather than not performed. For example, a conditional branch instruction will transfer control if the condition is true, so that execution proceeds to a different part of the program, and not transfer control if the condition is false, so that execution continues sequentially. Some instruction sets also have conditional moves, so that the move will be executed, and the data stored in the target ___location, if the condition is true, and not executed, and the target ___location not modified, if the condition is false. Similarly, IBM [[z/Architecture]] has a conditional store instruction. A few instruction sets include a predicate field in every instruction. Having predicates
====Number of operands====
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*more operands—some CISC machines permit a variety of addressing modes that allow more than 3 operands (registers or memory accesses), such as the [[VAX]] "POLY" polynomial evaluation instruction.
Due to the large number of bits needed to encode the three registers of a 3-operand instruction, RISC architectures that have 16-bit instructions are invariably 2-operand designs, such as the Atmel AVR, [[TI MSP430]], and some versions of [[ARM Thumb]]. RISC architectures that have 32-bit instructions are usually 3-operand designs, such as the [[ARM architecture family|ARM]], [[AVR32]], [[MIPS architecture|MIPS]], [[Power ISA]], and [[SPARC]] architectures. However even 3-operand RISC architectures will, at considerable cost, have [[Multiply%E2%80%93accumulate_operation#Fused_multiply%E2%80%93add|Fused multiply-and-add]] 4-operand instructions out of necessity, due to the increased accuracy provided. Modern examples include [[Power ISA]] and [[RISC-V]].
Each instruction specifies some number of operands (registers, memory locations, or immediate values) ''explicitly''. Some instructions give one or both operands implicitly, such as by being stored on top of the [[stack (data structure)|stack]] or in an implicit register. If some of the operands are given implicitly, fewer operands need be specified in the instruction. When a "destination operand" explicitly specifies the destination, an additional operand must be supplied. Consequently, the number of operands encoded in an instruction may differ from the mathematically necessary number of arguments for a logical or arithmetic operation (the [[arity]]). Operands are either encoded in the "opcode" representation of the instruction, or else are given as values or addresses following the opcode.
==={{Anchor|REGISTER-PRESSURE}}Register pressure===
''Register pressure'' measures the availability of free registers at any point in time during the program execution. Register pressure is high when a large number of the available registers are in use
While embedded instruction sets such as [[ARM Thumb|Thumb]] suffer from extremely high register pressure because they have small register sets, general-purpose RISC ISAs like [[MIPS architecture|MIPS]] and [[DEC Alpha|Alpha]] enjoy low register pressure. CISC ISAs like x86-64 offer low register pressure despite having smaller register sets. This is due to the many addressing modes and optimizations (such as sub-register addressing, memory operands in ALU instructions, absolute addressing, PC-relative addressing, and register-to-register spills) that CISC ISAs offer.<ref>{{cite conference |last1=Venkat |first1=Ashish |last2=Tullsen |first2=Dean M. |title=Harnessing ISA Diversity: Design of a Heterogeneous-ISA Chip Multiprocessor |year=2014 |conference=41st Annual International Symposium on Computer Architecture |url=http://dl.acm.org/citation.cfm?id=2665692}}</ref>
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The design of instruction sets is a complex issue. There were two stages in history for the microprocessor. The first was the CISC (complex instruction set computer), which had many different instructions. In the 1970s, however, places like IBM did research and found that many instructions in the set could be eliminated. The result was the RISC (reduced instruction set computer), an architecture that uses a smaller set of instructions. A simpler instruction set may offer the potential for higher speeds, reduced processor size, and reduced power consumption. However, a more complex set may optimize common operations, improve memory and [[CPU cache|cache]] efficiency, or simplify programming.
Some instruction set designers reserve one or more opcodes for some kind of [[system call]] or [[software interrupt]]. For example, [[MOS Technology 6502]] uses 00<sub>H</sub>, [[Zilog Z80]] uses the eight codes C7,CF,D7,DF,E7,EF,F7,FF<sub>H</sub><ref>{{cite web|last=Ganssle|first=Jack|url=https://www.embedded.com/electronics-blogs/break-points/4023293/Proactive-Debugging|title=Proactive Debugging|date=February 26, 2001|website=embedded.com}}</ref> while [[Motorola 68000]] use codes in the range
Fast virtual machines are much easier to implement if an instruction set meets the [[Popek and Goldberg virtualization requirements]].{{Clarify|date=October 2012}}
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{{CPU technologies}}
{{Authority control}}
{{Instruction set extensions}}
[[Category:Central processing unit]]
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