Field-programmable gate array: Difference between revisions

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A '''field-programmable gate array''' ('''FPGA''') is a type of configurable [[{{wikidata|property|P279}}integrated circuit]] that can be repeatedly programmed after manufacturing. FPGAs are a subset of logic devices referred to as [[programmable logic devices]] (PLDs). They consist of ana grid-connected array of [[programmable logic device|programmable]] [[logic block|logic blocks]] with a connecting grid, that can be configured "in the field" to interconnect with other logic blocks to perform various digital functions. FPGAs are often used in limited (low) quantity production of custom-made products, and in research and development, where the higher cost of individual FPGAs is not as important, and where creating and manufacturing a custom circuit wouldn'twould not be feasible. Other applications for FPGAs include the telecommunications, automotive, aerospace, and industrial sectors, which benefit from their flexibility, high signal processing speed, and parallel processing abilities.

A FPGA configuration is generally written using a [[hardware description language]] (HDL) e.g. [[VHDL]], similar to the ones used for [[application-specific integrated circuit]]s (ASICs). [[Circuit diagram|Circuit diagrams]] were formerly used to write the configuration.

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The logic blocks of an FPGA can be configured to perform complex [[combinational logic|combinational functions]], or act as simple [[logic gate]]s like [[AND gate|AND]] and [[XOR gate|XOR]]. In most FPGAs, logic blocks also include [[Memory cell (computing)|memory elements]], which may be simple [[flip-flop (electronics)|flip-flops]] or more sophisticated blocks of memory.<ref name="FPGA" /> Many FPGAs can be reprogrammed to implement different [[Boolean function|logic functions]], allowing flexible [[reconfigurable computing]] as performed in [[computer software]].

FPGAs also have a role in [[embedded system]] development due to their capability to start system software development simultaneously with hardware, enable system performance simulations at a very early phase of the development, and allow various system trials and design iterations before finalizing the system architecture.<ref>{{cite book |last1=Simpson |first1=P. A. |date=2015 |title=FPGA Design, Best Practices for Team Based Reuse, 2nd edition |___location=Switzerland |publisher=Springer International Publishing AG |page=16 |isbn=978-3-319-17924-7 }}</ref>

FPGAs are also commonly used during the development of ASICs to speed up the simulation process.

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Companies like Microsoft have started to use FPGAs to accelerate high-performance, computationally intensive systems (like the [[data center]]s that operate their [[Bing search engine]]), due to the [[performance per watt]] advantage FPGAs deliver.<ref>{{cite magazine|url=https://www.wired.com/2014/06/microsoft-fpga/|title=Microsoft Supercharges Bing Search With Programmable Chips|date=16 June 2014|magazine=WIRED}}</ref> Microsoft began using FPGAs to [[Hardware acceleration|accelerate]] Bing in 2014, and in 2018 began deploying FPGAs across other data center workloads for their [[Microsoft Azure|Azure]] [[cloud computing]] platform.<ref name="ProjCatapult" />

Since 2019, modern generation of FPGAs have been integrated with other architectures like [[AI engine|AI engines]] to target workloads in artificial intelligence ___domain.<ref>{{Cite book |last1=Gaide |first1=Brian |last2=Gaitonde |first2=Dinesh |last3=Ravishankar |first3=Chirag |last4=Bauer |first4=Trevor |chapter=Xilinx Adaptive Compute Acceleration Platform: Versal ^TM Architecture |date=2019-02-20 |title=Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays |chapter-url=https://dl.acm.org/doi/10.1145/3289602.3293906 |language=en |publisher=ACM |pages=84–93 |doi=10.1145/3289602.3293906 |isbn=978-1-4503-6137-8|chapter-url-access=subscription }}</ref>

===Growth===

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=== Logic blocks ===

{{Main|Logic block}}

[[File:FPGA cell example.png|thumb|Simplified example illustration of a logic cell (LUT&nbsp;&ndash;– [[lookup table]], FA&nbsp;&ndash;– [[full adder]], DFF&nbsp;&ndash;– [[D-type flip-flop]])]]

The most common FPGA architecture consists of an array of [[logic block]]s called configurable logic blocks (CLBs) or logic array blocks (LABs) (depending on vendor), [[I/O address|I/O pads]], and routing channels.<ref name="FPGA" /> Generally, all the routing channels have the same width (number of signals). Multiple I/O pads may fit into the height of one row or the width of one column in the array.

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"An application circuit must be mapped into an FPGA with adequate resources. While the number of logic blocks and I/Os required is easily determined from the design, the number of routing channels needed may vary considerably even among designs with the same amount of logic. For example, a [[crossbar switch]] requires much more routing than a [[systolic array]] with the same gate count. Since unused routing channels increase the cost (and decrease the performance) of the FPGA without providing any benefit, FPGA manufacturers try to provide just enough channels so that most designs that will fit in terms of [[Lookup table#Hardware LUTs|lookup tables]] (LUTs) and I/Os can be [[Routing (electronic design automation)|routed]]. This is determined by estimates such as those derived from [[Rent's rule]] or by experiments with existing designs."<ref>{{Cite journal |last1=M.b |first1=Swami |last2=V.p |first2=Pawar |date=2014-07-31 |title=VLSI DESIGN: A NEW APPROACH |url=https://bioinfopublication.org/pages/article.php?id=BIA0002301 |journal=Journal of Intelligence Systems |language=En |volume=4 |issue=1 |pages=60–63 |issn=2229-7057}}</ref>

In general, a logic block consists of a few logical cells. A typical cell consists of a 4-input LUT, a [[Adder (electronics)|full adder]] (FA) and a [[D-type flip-flop]]. The LUT might be split into two 3-input LUTs. In ''normal mode'' those are combined into a 4-input LUT through the first [[multiplexer]] (mux). In ''arithmetic'' mode, their outputs are fed to the adder. The selection of mode is programmed into the second mux. The output can be either [[Synchronous circuit|synchronous]] or [[Asynchronous circuit|asynchronous]], depending on the programming of the third mux. In practice, the entire adder or parts of it are [[Shannon expansion|stored as functions]] into the LUTs in order to save [[Circuit utilization|space]].<ref>[http://www.altera.com/literature/hb/cyc2/cyc2_cii51002.pdf 2. CycloneII Architecture] {{Webarchive|url=https://web.archive.org/web/20101214055643/http://www.altera.com/literature/hb/cyc2/cyc2_cii51002.pdf |date=2010-12-14 }}. Altera. February 2007</ref><ref>{{cite web |url=http://www.altera.com/literature/hb/stratix-iv/stx4_5v1_01.pdf |title=Documentation: Stratix IV Devices |publisher=Altera.com |date=2008-06-11 |access-date=2013-05-01 |archive-url=https://web.archive.org/web/20110926214034/http://www.altera.com/literature/hb/stratix-iv/stx4_5v1_01.pdf |archive-date=2011-09-26 |url-status=dead}}</ref><ref>[http://www.xilinx.com/support/documentation/user_guides/ug070.pdf Virtex-4 FPGA User Guide] (December 1st, 2008). Xilinx, Inc.</ref>

=== Hard blocks ===

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=== Integration ===

In 2012 the coarse-grained architectural approach was taken a step further by combining the [[logic block]]s and interconnects of traditional FPGAs with embedded [[microprocessor]]s and related peripherals to form a complete [[System on a chip|system on a programmable chip]]. Examples of such hybrid technologies can be found in the [[Xilinx]] Zynq-7000 all [[Programmableprogrammable SoC]],<ref name="Xilinx-Inc-Oct-2011-8-K">{{cite web|url=http://edgar.secdatabase.com/520/95012311090713/filing-main.htm |title=Xilinx Inc, Form 8-K, Current Report, Filing Date Oct 19, 2011 |publisher=secdatabase.com |access-date =May 6, 2018}}</ref> which includes a 1.0&nbsp;[[GHz]] dual-core [[ARM Cortex-A9]] MPCore processor [[Embedded system|embedded]] within the FPGA's logic fabric,<ref name="Xilinx-Inc-May-2011-10-K">{{cite web|url=http://edgar.secdatabase.com/1249/95012311055454/filing-main.htm |title=Xilinx Inc, Form 10-K, Annual Report, Filing Date May 31, 2011 |publisher=secdatabase.com |access-date =May 6, 2018}}</ref> or in the [[Altera]] Arria V FPGA, which includes an 800&nbsp;MHz [[dual-core]] [[ARM Cortex-A9]] MPCore. The [[Atmel]] FPSLIC is another such device, which uses an [[Atmel AVR|AVR]] processor in combination with Atmel's programmable logic architecture. The [[Microsemi]] [[SmartFusion]] devices incorporate an ARM Cortex-M3 hard processor core (with up to 512&nbsp;kB of [[Flash memory|flash]] and 64&nbsp;kB of RAM) and analog [[peripheral]]s such as a multi-channel [[analog-to-digital converter]]s and [[digital-to-analog converter]]s in their [[flash memory]]-based FPGA fabric.{{cn|date=November 2022}}

=== Clocking ===

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== Manufacturers ==

In 2016, long-time industry rivals [[Xilinx]] (now part of [[AMD]]) and [[Altera]] (now part of [[Intel|İntel]]) were the FPGA market leaders.<ref>{{cite web |first=Paul |last=Dillien |work=EETimes | url=http://www.eetimes.com/author.asp?doc_id=1331443 | archive-url =https://web.archive.org/web/20190105015123/http://www.eetimes.com/author.asp?doc_id=1331443 |title=And the Winner of Best FPGA of 2016 is... |date=March 6, 2017 |access-date=September 7, 2017 |archive-date=January 5, 2019 }}</ref> At that time, they controlled nearly 90 percent of the market.

Both Xilinx (now AMD) and Altera (now Intel) provide [[proprietary software|proprietary]] [[electronic design automation]] software for [[Windows]] and [[Linux]] ([[Xilinx ISE|ISE]]/[[Vivado]] and [[Intel Quartus Prime|Quartus]]) which enables engineers to [[Hardware design|design]], analyze, [[simulate]], and [[Logic synthesis|synthesize]] ([[compile]]) their designs.<ref>{{Cite web|url=https://www.xilinx.com/products/design-tools/ise-design-suite.html|title=Xilinx ISE Design Suite|website=www.xilinx.com|access-date=2018-12-01}}</ref><ref>{{Cite web|url=https://www.altera.com/products/design-software/fpga-design/quartus-prime/overview.html|title=FPGA Design Software - Intel Quartus Prime|website=Intel|language=en|access-date=2018-12-01}}</ref>

In March 2010, [[Tabula (company)|Tabula]] announced their FPGA technology that uses [[Time-division multiplexing|time-multiplexed]] logic and interconnect that claims potential cost savings for high-density applications.<ref>{{cite web |title=Tabula's Time Machine&nbsp;— Micro Processor Report |url=http://www.tabula.com/news/M11_Tabula_Reprint.pdf |url-status=dead |archive-url=https://web.archive.org/web/20110410094902/http://www.tabula.com/news/M11_Tabula_Reprint.pdf |archive-date=2011-04-10}}</ref> On March 24, 2015, Tabula officially shut down.<ref>[http://www.bizjournals.com/sanjose/news/2015/02/11/tabula-to-shut-down-120-jobs-lost-at-fabless-chip.html Tabula to shut down; 120 jobs lost at fabless chip company] Silicon Valley Business Journal</ref>

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Other manufacturers include:

* [[Achronix]], manufacturing SRAM based FPGAs with 1.5&nbsp;GHz fabric speed<ref>{{Cite press release |url=http://newsroom.intel.com/community/intel_newsroom/blog/2010/11/01/chip-shot-achronix-to-use-intel-s-22nm-manufacturing |title=Achronix to Use Intel's 22nm Manufacturing |date=2010-11-01 |work=Intel Newsroom |access-date=2018-12-01 |language=en-US |archive-date=2015-09-30 |archive-url=https://web.archive.org/web/20150930082224/http://newsroom.intel.com/community/intel_newsroom/blog/2010/11/01/chip-shot-achronix-to-use-intel-s-22nm-manufacturing |url-status=dead }}{{better source needed|{{subst:DATE}}|date=September 2024}}</ref>

*[[Altium]], provides system-on-FPGA hardware-software design environment.<ref>{{cite book |last1=Maxfield |first1=Clive |title=The Design Warrior's Guide to FPGAs |date=16 June 2004 |publisher=Elsevier Science |isbn=9780080477138 |url=https://books.google.com/books?id=dnuwr2xOFpUC&dq=fpga+altium&pg=PA117}}</ref>

* Cologne Chip, German Government government-backed designer and producer of FPGAs<ref>{{Cite web |title=About the company – Cologne Chip |url=https://colognechip.com/about-the-company/ |access-date=2024-02-27 |language=en-US}}{{better source needed|{{subst:DATE}}|date=September 2024}}</ref>

* [[Efinix]] offers small to medium-sized FPGAs. They combine logic and routing interconnects into a configurable XLR cell.{{cn|date=September 2024}}

* [[GOWIN Semiconductors]], manufacturing small and medium-sized SRAM and Flashflash-based FPGAs. They also offer pin-compatible replacements for a few Xilinx, Altera and Lattice products.{{cn|date=September 2024}}

* [[Lattice Semiconductor]] manufactures [[Low-power electronics|low-power]] SRAM-based FPGAs featuring integrated configuration flash, [[instant-on]] and live [[Reconfigurable computing|reconfiguration]]

** [[SiliconBlue Technologies]] provides extremely low-power SRAM-based FPGAs with optional integrated [[Non-volatile memory|nonvolatile]] configuration memory; acquired by Lattice in 2011

* [[Microchip Technology|Microchip]]:

** [[Microsemi]] (previously [[Actel]]), producing [[antifuse]], flash-based, [[mixed-signal]] FPGAs; acquired by Microchip in 2018

** [[Atmel]], a second source of some Altera-compatible devices; also FPSLIC{{Clarify|reason=|date=December 2018}} mentioned above;<ref>{{Cite news|url=http://sourcetech411.com/2013/04/top-fpga-companies-for-2013/|title=Top FPGA Companies For 2013|date=2013-04-28|work=SourceTech411|access-date=2018-12-01|language=en-US|archive-date=2018-08-24|archive-url=https://web.archive.org/web/20180824135219/https://sourcetech411.com/2013/04/top-fpga-companies-for-2013/|url-status=dead}}</ref> acquired by Microchip in 2016

* QuickLogic manufactures ultra-low-power sensor hubs, extremely-low-powered, low-density SRAM-based FPGAs, with display bridges MIPI and RGB inputs; MIPI, RGB and LVDS outputs.<ref>{{Cite web|url=http://www.quicklogic.com/|title=QuickLogic — Customizable Semiconductor Solutions for Mobile Devices|website=www.quicklogic.com|publisher=QuickLogic Corporation|language=en|access-date=2018-10-07}}{{better source needed|{{subst:DATE}}|date=September 2024}}</ref>

== Applications ==

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The evolution of FPGAs has motivated an increase in the use of these devices, whose architecture allows the development of hardware solutions optimized for complex tasks, such as 3D MRI image segmentation, 3D discrete wavelet transform, tomographic image reconstruction, or PET/MRI systems.<ref>{{Cite journal |last1=Alcaín |first1=Eduardo |last2=Fernández |first2=Pedro R. |last3=Nieto |first3=Rubén |last4=Montemayor |first4=Antonio S. |last5=Vilas |first5=Jaime |last6=Galiana-Bordera |first6=Adrian |last7=Martinez-Girones |first7=Pedro Miguel |last8=Prieto-de-la-Lastra |first8=Carmen |last9=Rodriguez-Vila |first9=Borja |last10=Bonet |first10=Marina |last11=Rodriguez-Sanchez |first11=Cristina |date=2021-12-15 |title=Hardware Architectures for Real-Time Medical Imaging |journal=Electronics |language=en |volume=10 |issue=24 |pages=3118 |doi=10.3390/electronics10243118 |issn=2079-9292|doi-access=free }}</ref><ref>{{Cite journal |last1=Nagornov |first1=Nikolay N. |last2=Lyakhov |first2=Pavel A. |last3=Valueva |first3=Maria V. |last4=Bergerman |first4=Maxim V. |date=2022 |title=RNS-Based FPGA Accelerators for High-Quality 3D Medical Image Wavelet Processing Using Scaled Filter Coefficients |journal=IEEE Access |volume=10 |pages=19215–19231 |doi=10.1109/ACCESS.2022.3151361 |s2cid=246895876 |issn=2169-3536|doi-access=free |bibcode=2022IEEEA..1019215N }}</ref> The developed solutions can perform intensive computation tasks with parallel processing, are dynamically reprogrammable, and have a low cost, all while meeting the hard real-time requirements associated with medical imaging.

Another trend in the use of FPGAs is [[hardware acceleration]], where one can use the FPGA to accelerate certain parts of an algorithm and share part of the computation between the FPGA and a general-purpose processor. The search engine [[Bing (search engine)|Bing]] is noted for adopting FPGA acceleration for its search algorithm in 2014.<ref name="BingFPGA">{{cite news |last1=Morgan |first1=Timothy Pricket |title=How Microsoft Is Using FPGAs To Speed Up Bing Search |url=https://www.enterprisetech.com/2014/09/03/microsoft-using-fpgas-speed-bing-search/ |access-date=2018-09-18 |publisher=Enterprise Tech |date=2014-09-03 }}{{Dead link|date=April 2025 |bot=InternetArchiveBot |fix-attempted=yes }}</ref> {{as of|2018}}, FPGAs are seeing increased use as [[AI accelerator]]s including Microsoft's Project Catapult<ref name="ProjCatapult">{{cite web|url=https://www.microsoft.com/en-us/research/project/project-catapult/|title=Project Catapult|date=July 2018|website=Microsoft Research}}</ref> and for accelerating [[artificial neural network]]s for [[machine learning]] applications.

Originally,{{When|date=October 2018}} FPGAs were reserved for specific [[vertical application]]s where the volume of production is small. For these low-volume applications, the premium that companies pay in hardware cost per unit for a programmable chip is more affordable than the development resources spent on creating an ASIC. Often a custom-made chip would be cheaper if made in larger quantities, but FPGAs may be chosen to quickly bring a product to market. By 2017, new cost and performance dynamics broadened the range of viable applications.{{cn|date=December 2024}}<!--[[User:Kvng/RTH]]-->

Other uses for FPGAs include:

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* Space (with [[radiation hardening]]<ref>{{Cite web|url=https://www.militaryaerospace.com/articles/2016/06/radiation-hardened-space-fpga.html|title=FPGA development devices for radiation-hardened space applications introduced by Microsemi|website=www.militaryaerospace.com|access-date=2018-11-02|date=2016-06-03}}</ref>)

* [[Hardware security module]]s<ref name="auto">{{cite web|title=CrypTech: Building Transparency into Cryptography t |url=https://cryptech.is/wp-content/uploads/2016/02/CrypTech_Building_Transparency.pdf |archive-url=https://web.archive.org/web/20160807180252/https://cryptech.is/wp-content/uploads/2016/02/CrypTech_Building_Transparency.pdf |archive-date=2016-08-07 |url-status=live}}</ref>

* High-speed financial transactions<ref>{{Cite web |last=Mann |first=Tobias |date=2023-03-08 |title=While Intel XPUs are delayed, here's some more FPGAs to tide you over |url=https://www.theregister.com/2023/03/08/intel_fpga_agilex/ |website=The Register}}</ref><ref>{{Cite conference |url=https://ieeexplore.ieee.org/document/6044837 |title=High Frequency Trading Acceleration Using FPGAs |last1=Leber |first1=Christian |last2=Geib |first2=Benjamin |last3=Litz |first3=Heiner |doi=10.1109/FPL.2011.64 |publisher=IEEE |date=September 2011 |conference=International Conference on Field Programmable Logic and Applications}}</ref>

* [[Retrocomputing]] (e.g. the MARS and [[MiSTer]] FPGA projects)<ref>{{citationcite web needed|dateurl=December 2023}}<!--I don't know if MiSTer FPGA News is considered an acceptable source for this purpose, but it's out there: https://www.retrorgb.com/tag/the-diy-mister-handheld.html |title=The DIY MiSTer Handheld |date=16 December 2024 |access--date=}}</ref>

* Large scale integrated [[digital differential analyzer]]s, a form of an [[analog computer]] based on digital computing elements<ref>[https://people.ece.cornell.edu/land/courses/ece5760/DDA/index.htm DDA on FPGA - A modern Analog Computer]</ref>

=== Usage by United States military ===

FPGAs play a crucial role in modern military communications, especially in systems like the [[Joint Tactical Radio System]] (JTRS) and in devices from companies such as [[Thales Group|Thales]] and [[Harris Corporation]]. Their flexibility and programmability make them ideal for military communications, offering customizable and secure signal processing. In the JTRS, used by the US military, FPGAs provide adaptability and real-time processing, crucial for meeting various communication standards and encryption methods. Thales uses FPGA technology in designing communication devices that fulfill the rigorous demands of military use, including rapid reconfiguration and robust security. Similarly, Harris Corporation, now part of [[L3Harris Technologies]], incorporates FPGAs in its defense and commercial communication solutions, enhancing signal processing and system security.<ref>{{Cite web |date=2004-12-01 |title=Software-defined radio and JTRS |url=https://www.militaryaerospace.com/computers/article/16710419/softwaredefined-radio-and-jtrs |access-date=2024-01-17 |website=Military Aerospace}}</ref>

==== L3Harris ====

# '''Rapidly adaptable standards-compliant radio (RASOR):''' A modular open system approach (MOSA) solution supporting over 50 data links and waveforms.

# '''ASPEN technology platform:''' Consists of proven hardware modules with programmable software and FPGA options for advanced, configurable data links.

# '''[[AN/PRC-117|AN/PRC-117F(C)]] radios:''' Supported the [[Electronic Systems Center|U.S. Air Force Electronic Systems Command]], strengthening Harris' role as a full-spectrum communications system supplier.

==== Thales ====

# '''SYNAPS radio damily:''' Utilizes [[software-defined radio]] (SDR) technology, typically involving FPGA for enhanced flexibility and performance.

# '''[[AN/PRC-148]] (multiband inter/intra team radio - MBITR):''' A small-form-factor, multiband, multi-mode SDR used in Afghanistan and Iraq.

# '''[[JTRS]] Cluster 2 handheld radio:''' Currently in development, recently completed a successful early operational assessment.

== Security ==

Concerning [[hardware security]], FPGAs have both advantages and disadvantages as compared to ASICs or secure microprocessors, concerning [[hardware security]]. FPGAs' flexibility makes malicious modifications during [[Semiconductor device fabrication|fabrication]] a lower risk.<ref name="paper">{{Cite journal |doi=10.1109/MDT.2008.166 |title=Managing Security in FPGA-Based Embedded Systems |journal=IEEE Design & Test of Computers |volume=25 |issue=6 |pages=590–598 |year=2008 |last1=Huffmire |first1=Ted |last2=Brotherton |first2=Brett |last3=Sherwood |first3=Timothy |last4=Kastner |first4=Ryan |last5=Levin |first5=Timothy |last6=Nguyen |first6=Thuy D. |last7=Irvine |first7=Cynthia|bibcode=2008IDTC...25..590H |s2cid=115840 |hdl=10945/7159 |hdl-access=free }}</ref> Previously, for many FPGAs, the design [[bitstream]] was exposed while the FPGA loads it from external memory, (typically onduring every power-on)powerup. All major FPGA vendors now offer a spectrum of security solutions to designers such as bitstream [[encryption]] and [[authentication]]. For example, [[Altera]] and [[Xilinx]] offer [[Advanced Encryption Standard|AES]] encryption (up to 256-bit) for bitstreams stored in an external flash memory. [[Physical unclonable function]]s (PUFs) are integrated circuits that have their own unique signatures, due to processing, and can also be used to secure FPGAs while taking up very little hardware space.<ref>{{Cite journal |last1=Babaei |first1=Armin |last2=Schiele |first2=Gregor |last3=Zohner |first3=Michael |date=2022-07-26 |title=Reconfigurable Security Architecture (RESA) Based on PUF for FPGA-Based IoT Devices |journal=Sensors |language=en |volume=22 |issue=15 |pages=5577 |doi=10.3390/s22155577 |issn=1424-8220 |pmc=9331300 |pmid=35898079 |bibcode=2022Senso..22.5577B |doi-access=free }}</ref>

FPGAs that store their configuration internally in nonvolatile flash memory, such as [[Microsemi]]'s ProAsic &nbsp;3 or [[Lattice Semiconductor|Lattice]]'s XP2 programmable devices, do not expose the bitstream and do not need [[encryption]]. In addition, flash memory for a [[lookup table]] provides [[single event upset]] protection for space applications.{{clarify|date=January 2013}} Customers wanting a higher guarantee of tamper resistance can use write-once, antifuse FPGAs from vendors such as [[Microsemi]].

FPGAs have both advantages and disadvantages as compared to ASICs or secure microprocessors, concerning [[hardware security]]. FPGAs' flexibility makes malicious modifications during [[Semiconductor device fabrication|fabrication]] a lower risk.<ref name="paper">{{Cite journal |doi=10.1109/MDT.2008.166 |title=Managing Security in FPGA-Based Embedded Systems |journal=IEEE Design & Test of Computers |volume=25 |issue=6 |pages=590–598 |year=2008 |last1=Huffmire |first1=Ted |last2=Brotherton |first2=Brett |last3=Sherwood |first3=Timothy |last4=Kastner |first4=Ryan |last5=Levin |first5=Timothy |last6=Nguyen |first6=Thuy D. |last7=Irvine |first7=Cynthia|s2cid=115840 |hdl=10945/7159 |hdl-access=free }}</ref> Previously, for many FPGAs, the design [[bitstream]] was exposed while the FPGA loads it from external memory (typically on every power-on). All major FPGA vendors now offer a spectrum of security solutions to designers such as bitstream [[encryption]] and [[authentication]]. For example, [[Altera]] and [[Xilinx]] offer [[Advanced Encryption Standard|AES]] encryption (up to 256-bit) for bitstreams stored in an external flash memory. [[Physical unclonable function]]s (PUFs) are integrated circuits that have their own unique signatures, due to processing, and can also be used to secure FPGAs while taking up very little hardware space.<ref>{{Cite journal |last1=Babaei |first1=Armin |last2=Schiele |first2=Gregor |last3=Zohner |first3=Michael |date=2022-07-26 |title=Reconfigurable Security Architecture (RESA) Based on PUF for FPGA-Based IoT Devices |journal=Sensors |language=en |volume=22 |issue=15 |pages=5577 |doi=10.3390/s22155577 |issn=1424-8220 |pmc=9331300 |pmid=35898079 |bibcode=2022Senso..22.5577B |doi-access=free }}</ref>

FPGAs that store their configuration internally in nonvolatile flash memory, such as [[Microsemi]]'s ProAsic 3 or [[Lattice Semiconductor|Lattice]]'s XP2 programmable devices, do not expose the bitstream and do not need [[encryption]]. In addition, flash memory for a [[lookup table]] provides [[single event upset]] protection for space applications.{{clarify|date=January 2013}} Customers wanting a higher guarantee of tamper resistance can use write-once, antifuse FPGAs from vendors such as [[Microsemi]].

With its Stratix 10 FPGAs and SoCs, [[Altera]] introduced a Secure Device Manager and [[physical unclonable function]]s to provide high levels of protection against physical attacks.<ref>{{cite web|url=https://www.intrinsic-id.com/eetimes-security-features-for-non-security-experts/|title=EETimes on PUF: Security features for non-security experts – Intrinsic ID|work=Intrinsic ID|date=2015-06-09|access-date=2015-07-12|archive-date=2015-07-13|archive-url=https://web.archive.org/web/20150713093531/https://www.intrinsic-id.com/eetimes-security-features-for-non-security-experts/|url-status=dead}}</ref>

In 2012 researchers Sergei Skorobogatov and Christopher Woods demonstrated that some FPGAs can be vulnerable to hostile intent. They discovered a critical [[Backdoor (computing)|backdoor]] [[Vulnerability (computing)|vulnerability]] had been manufactured in silicon as part of the Actel/Microsemi ProAsic &nbsp;3 making it vulnerable on many levels such as reprogramming crypto and [[access key]]s, accessing unencrypted bitstream, modifying [[low-level]] silicon features, and extracting [[Computer configuration|configuration]] data.<ref>{{cite book |volume=7428|pages=23–40|doi=10.1007/978-3-642-33027-8_2|series = Lecture Notes in Computer Science|year = 2012|last1 = Skorobogatov|first1 = Sergei|title=Cryptographic Hardware and Embedded Systems – CHES 2012|last2=Woods|first2=Christopher|isbn=978-3-642-33026-1|chapter=Breakthrough Silicon Scanning Discovers Backdoor in Military Chip}}</ref>

In 2020 a critical vulnerability (named "Starbleed") was discovered in all Xilinx&nbsp;7 7seriesseries FPGAs that rendered bitstream encryption useless. There is no workaround. Xilinx did not produce a hardware revision. Ultrascale and later devices, already on the market at the time, were not affected.{{cn|date=July 2025}}

== Similar technologies ==

Historically, FPGAs have been slower, less energy efficient and generally achieved less functionality than their fixed ASIC counterparts. A study from 2006 showed that designs implemented on FPGAs need on average 40 times as much area, draw 12 times as much dynamic power, and run at one third the speed of corresponding ASIC implementations.<ref name="FPGA-ASIC-comparison">{{cite conference|doi=10.1145/1117201.1117205|chapter=Measuring the gap between FPGAs and ASICs|title=Proceedings of the international symposium on Field programmable gate arrays – FPGA'06|pages=21–30|year=2006|last1=Kuon|first1=Ian|last2=Rose|first2=Jonathan|isbn=1-59593-292-5|publisher=ACM|___location=New York, NY|chapter-url=http://ece.gmu.edu/coursewebpages/ECE/ECE448/S09/viewgraphs/Gap_between_FPGAs_and_ASICs.pdf|conference=|access-date=2017-10-25|archive-date=2010-06-22|archive-url=https://web.archive.org/web/20100622170541/http://ece.gmu.edu/coursewebpages/ECE/ECE448/S09/viewgraphs/Gap_between_FPGAs_and_ASICs.pdf|url-status=dead}}</ref>

Advantages of FPGAs include the ability to reprogram equipment in the field to fix [[Bug (computer programming)|bugs]] or make other improvements. Some FPGAs have the capability of [[partial re-configuration]] that lets one portion of the device be re-programmed while other portions continue running.<ref>{{Cite web|url=https://www.intel.com/content/www/us/en/programmable/documentation/ekx1496870149834.html|title=AN 818: Static Update Partial Reconfiguration Tutorial: for Intel Stratix 10 GX FPGA Development Board|website=www.intel.com|access-date=2018-12-01}}</ref><ref>{{Cite web|url=https://electronics.stackexchange.com/questions/45115/can-fpgas-dynamically-modify-their-logic|title=Can FPGAs dynamically modify their logic?|website=Electrical Engineering Stack Exchange|access-date=2018-12-01}}</ref> Other advantages may include shorter [[time to market]] and lower [[non-recurring engineering]] costs. Vendors can also take a middle road via [[FPGA prototyping]]: developing their prototype hardware on FPGAs, but manufacturing their final version as an ASIC after the design has been committed. This is often also the case with new processor designs.<ref>{{cite web|url=https://www.anandtech.com/show/14798/xilinx-announces-world-largest-fpga-virtex-ultrascale-vu19p-with-9m-cells|archive-url=https://web.archive.org/web/20190827160514/https://www.anandtech.com/show/14798/xilinx-announces-world-largest-fpga-virtex-ultrascale-vu19p-with-9m-cells|url-status=dead|archive-date=August 27, 2019|title=Xilinx Announces World Largest FPGA: Virtex Ultrascale+ VU19P with 9m Cells|first=Ian|last=Cutress|date=August 27, 2019|website=[[AnandTech]]}}</ref><!--[[User:Kvng/RTH]]-->

Historically, FPGAs have been slower, less energy efficient and generally achieved less functionality than their fixed ASIC counterparts. A study from 2006 showed that designs implemented on FPGAs need on average 40 times as much area, draw 12 times as much dynamic power, and run at one third the speed of corresponding ASIC implementations.<ref name="FPGA-ASIC-comparison">{{cite conference|doi=10.1145/1117201.1117205|chapter=Measuring the gap between FPGAs and ASICs|title=Proceedings of the international symposium on Field programmable gate arrays – FPGA'06|pages=21–30|year=2006|last1=Kuon|first1=Ian|last2=Rose|first2=Jonathan|isbn=1-59593-292-5|publisher=ACM|___location=New York, NY|chapter-url=http://ece.gmu.edu/coursewebpages/ECE/ECE448/S09/viewgraphs/Gap_between_FPGAs_and_ASICs.pdf|conference=|access-date=2017-10-25|archive-date=2010-06-22|archive-url=https://web.archive.org/web/20100622170541/http://ece.gmu.edu/coursewebpages/ECE/ECE448/S09/viewgraphs/Gap_between_FPGAs_and_ASICs.pdf|url-status=dead}}</ref>

Advantages of FPGAs include the ability to re-program when already deployed (i.e. "in the field") to fix [[Bug (computer programming)|bugs]], and often include shorter [[time to market]] and lower [[non-recurring engineering]] costs. Vendors can also take a middle road via [[FPGA prototyping]]: developing their prototype hardware on FPGAs, but manufacture their final version as an ASIC so that it can no longer be modified after the design has been committed. This is often also the case with new processor designs.<ref>{{cite web|url=https://www.anandtech.com/show/14798/xilinx-announces-world-largest-fpga-virtex-ultrascale-vu19p-with-9m-cells|title=Xilinx Announces World Largest FPGA: Virtex Ultrascale+ VU19P with 9m Cells|first=Ian|last=Cutress|date=August 27, 2019|website=[[AnandTech]]}}</ref> Some FPGAs have the capability of [[partial re-configuration]] that lets one portion of the device be re-programmed while other portions continue running.<ref>{{Cite web|url=https://www.intel.com/content/www/us/en/programmable/documentation/ekx1496870149834.html|title=AN 818: Static Update Partial Reconfiguration Tutorial: for Intel Stratix 10 GX FPGA Development Board|website=www.intel.com|access-date=2018-12-01}}</ref><ref>{{Cite web|url=https://electronics.stackexchange.com/questions/45115/can-fpgas-dynamically-modify-their-logic|title=Can FPGAs dynamically modify their logic?|website=Electrical Engineering Stack Exchange|access-date=2018-12-01}}</ref>

The primary differences between [[complex programmable logic device]]s (CPLDs) and FPGAs are [[Computer architecture|architectural]]. A CPLD has a comparatively restrictive structure consisting of one or more programmable [[Canonical normal form|sum-of-products]] logic arrays feeding a relatively small number of clocked [[Register (computing)|registers]]. As a result, CPLDs are less flexible but have the advantage of more predictable [[Latency (engineering)|timing delays]] and {{Citation needed span|text=a higher logic-to-interconnect ratio.|date=December 2018|reason=}} FPGA architectures, on the other hand, are dominated by [[Communications subsystem|interconnect]]. This makes them far more flexible (in terms of the range of designs that are practical for implementation on them) but also far more complex to design for, or at least requiring more complex [[electronic design automation]] (EDA) software. In practice, the distinction between FPGAs and CPLDs is often one of size as FPGAs are usually much larger in terms of resources than CPLDs. Typically only FPGAs contain more complex [[Functional unit|embedded functions]] such as [[Adder (electronics)|adders]], [[Binary multiplier|multipliers]], [[Computer memory|memory]], and [[SerDes|serializer/deserializers]]. Another common distinction is that CPLDs contain embedded [[flash memory]] to store their configuration while FPGAs usually require external [[non-volatile memory]] (but not always). When a design requires simple instant-on [[glue logic|(logic is already configured at power-up)]] CPLDs are generally preferred. For most other applications FPGAs are generally preferred. Sometimes both CPLDs and FPGAs are used in a single system design. In those designs, CPLDs generally perform glue logic functions and are responsible for "[[booting]]" the FPGA as well as controlling [[Reset (computing)|reset]] and boot sequence of the complete circuit board. Therefore, depending on the application it may be judicious to use both FPGAs and CPLDs in a single design.<ref>{{cite web|url=https://numato.com/kb/cpld-vs-fpga-differences-one-use/|title=CPLD vs FPGA: Differences between them and which one to use? – Numato Lab Help Center|website=numato.com|date=2017-11-29}}</ref>

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* [[FPGA Mezzanine Card]]

* [[CRUVI FPGA Card|CRUVI]] FPGA daughtercarddaughter card standard]] of Standardization Group for Embedded Technologies e.V. (SGET)

* [[List of HDL simulators]]

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* {{cite book |first1=Hartmut F.-W. |last1=Sadrozinski |first2=Jinyuan |last2=Wu |title=Applications of Field-Programmable Gate Arrays in Scientific Research |year=2010 |publisher=Taylor & Francis |isbn=978-1-4398-4133-4}}

* {{cite book|title=Digital Circuit Design An Introduction Textbook |first=Niklaus |last=Wirth |publisher=Springer |year=1995 |isbn=978-3-540-58577-0}}

* {{cite journal|title=An FPGA-Based Phase Measurement System |journal=IEEE Transactions on Very Large Scale Integration (VLSI) Systems |volume=26 |pages=133–142 |first=Jubin |last=Mitra |publisher=IEEE |year=2018 |issue=1 |doi=10.1109/TVLSI.2017.2758807|bibcode=2018ITVL...26..133M |s2cid=4920719 |doi-access=free }}

* Mencer, Oskar et al. (2020). "The history, status, and future of FPGAs". Communications of the ACM. ACM. Vol. 63, No. 10. doi:[[doi:10.1145/3410669|10.1145/3410669]]

== External links ==